root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h

INCLUDED FROM

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DC_STREAM_ENCODER_DCN20_H__
  27 #define __DC_STREAM_ENCODER_DCN20_H__
  28 
  29 #include "stream_encoder.h"
  30 #include "dcn10/dcn10_stream_encoder.h"
  31 
  32 
  33 #define SE_DCN2_REG_LIST(id)\
  34         SE_COMMON_DCN_REG_LIST(id),\
  35         SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
  36         SRI(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \
  37         SRI(DP_DSC_CNTL, DP, id), \
  38         SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
  39         SRI(DME_CONTROL, DIG, id),\
  40         SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
  41         SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
  42         SRI(DP_SEC_FRAMING4, DP, id)
  43 
  44 #define SE_COMMON_MASK_SH_LIST_DCN20(mask_sh)\
  45         SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
  46         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
  47         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
  48         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
  49         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
  50         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\
  51         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\
  52         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\
  53         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\
  54         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\
  55         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\
  56         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\
  57         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\
  58         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\
  59         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\
  60         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\
  61         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\
  62         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\
  63         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\
  64         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\
  65         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\
  66         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\
  67         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\
  68         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\
  69         SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\
  70         SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\
  71         SE_SF(DP0_DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, mask_sh),\
  72         SE_SF(DP0_DP_DSC_BYTES_PER_PIXEL, DP_DSC_BYTES_PER_PIXEL, mask_sh),\
  73         SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\
  74         SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\
  75         SE_SF(DIG0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\
  76         SE_SF(DIG0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\
  77         SE_SF(DIG0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\
  78         SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\
  79         SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
  80         SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\
  81         SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\
  82         SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\
  83         SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\
  84         SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\
  85         SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, mask_sh),\
  86         SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh)
  87 
  88 void dcn20_stream_encoder_construct(
  89         struct dcn10_stream_encoder *enc1,
  90         struct dc_context *ctx,
  91         struct dc_bios *bp,
  92         enum engine_id eng_id,
  93         const struct dcn10_stream_enc_registers *regs,
  94         const struct dcn10_stream_encoder_shift *se_shift,
  95         const struct dcn10_stream_encoder_mask *se_mask);
  96 
  97 void enc2_stream_encoder_dp_set_stream_attribute(
  98         struct stream_encoder *enc,
  99         struct dc_crtc_timing *crtc_timing,
 100         enum dc_color_space output_color_space,
 101         uint32_t enable_sdp_splitting);
 102 
 103 void enc2_stream_encoder_dp_unblank(
 104         struct stream_encoder *enc,
 105         const struct encoder_unblank_param *param);
 106 
 107 void enc2_set_dynamic_metadata(struct stream_encoder *enc,
 108                 bool enable_dme,
 109                 uint32_t hubp_requestor_id,
 110                 enum dynamic_metadata_mode dmdata_mode);
 111 
 112 #endif /* __DC_STREAM_ENCODER_DCN20_H__ */