root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c

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DEFINITIONS

This source file includes following definitions.
  1. optc2_enable_crtc
  2. optc2_set_timing_db_mode
  3. optc2_set_gsl
  4. optc2_use_gsl_as_master_update_lock
  5. optc2_set_gsl_window
  6. optc2_set_vupdate_keepout
  7. optc2_set_gsl_source_select
  8. optc2_set_dsc_encoder_frame_start
  9. optc2_set_dsc_config
  10. optc2_set_odm_bypass
  11. optc2_set_odm_combine
  12. optc2_get_optc_source
  13. optc2_set_dwb_source
  14. optc2_triplebuffer_lock
  15. optc2_triplebuffer_unlock
  16. optc2_lock_doublebuffer_enable
  17. optc2_lock_doublebuffer_disable
  18. optc2_setup_manual_trigger
  19. optc2_program_manual_trigger
  20. dcn20_timing_generator_init
   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #include "reg_helper.h"
  27 #include "dcn20_optc.h"
  28 #include "dc.h"
  29 
  30 #define REG(reg)\
  31         optc1->tg_regs->reg
  32 
  33 #define CTX \
  34         optc1->base.ctx
  35 
  36 #undef FN
  37 #define FN(reg_name, field_name) \
  38         optc1->tg_shift->field_name, optc1->tg_mask->field_name
  39 
  40 /**
  41  * Enable CRTC
  42  * Enable CRTC - call ASIC Control Object to enable Timing generator.
  43  */
  44 bool optc2_enable_crtc(struct timing_generator *optc)
  45 {
  46         /* TODO FPGA wait for answer
  47          * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
  48          * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
  49          */
  50         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  51 
  52         /* opp instance for OTG. For DCN1.0, ODM is remoed.
  53          * OPP and OPTC should 1:1 mapping
  54          */
  55         REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
  56                         OPTC_SEG0_SRC_SEL, optc->inst);
  57 
  58         /* VTG enable first is for HW workaround */
  59         REG_UPDATE(CONTROL,
  60                         VTG0_ENABLE, 1);
  61 
  62         /* Enable CRTC */
  63         REG_UPDATE_2(OTG_CONTROL,
  64                         OTG_DISABLE_POINT_CNTL, 3,
  65                         OTG_MASTER_EN, 1);
  66 
  67         return true;
  68 }
  69 
  70 /**
  71  * DRR double buffering control to select buffer point
  72  * for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers
  73  * Options: anytime, start of frame, dp start of frame (range timing)
  74  */
  75 void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable)
  76 {
  77         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  78 
  79         uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
  80 
  81         REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
  82                 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable);
  83 }
  84 
  85 /**
  86  *For the below, I'm not sure how your GSL parameters are stored in your env,
  87  * so I will assume a gsl_params struct for now
  88  */
  89 void optc2_set_gsl(struct timing_generator *optc,
  90                    const struct gsl_params *params)
  91 {
  92         struct optc *optc1 = DCN10TG_FROM_TG(optc);
  93 
  94 /**
  95  * There are (MAX_OPTC+1)/2 gsl groups available for use.
  96  * In each group (assign an OTG to a group by setting OTG_GSLX_EN = 1,
  97  * set one of the OTGs to be the master (OTG_GSL_MASTER_EN = 1) and the rest are slaves.
  98  */
  99         REG_UPDATE_5(OTG_GSL_CONTROL,
 100                 OTG_GSL0_EN, params->gsl0_en,
 101                 OTG_GSL1_EN, params->gsl1_en,
 102                 OTG_GSL2_EN, params->gsl2_en,
 103                 OTG_GSL_MASTER_EN, params->gsl_master_en,
 104                 OTG_GSL_MASTER_MODE, params->gsl_master_mode);
 105 }
 106 
 107 
 108 /* Use the gsl allow flip as the master update lock */
 109 void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc,
 110                    const struct gsl_params *params)
 111 {
 112         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 113 
 114         REG_UPDATE(OTG_GSL_CONTROL,
 115                 OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en);
 116 }
 117 
 118 /* You can control the GSL timing by limiting GSL to a window (X,Y) */
 119 void optc2_set_gsl_window(struct timing_generator *optc,
 120                    const struct gsl_params *params)
 121 {
 122         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 123 
 124         REG_SET_2(OTG_GSL_WINDOW_X, 0,
 125                 OTG_GSL_WINDOW_START_X, params->gsl_window_start_x,
 126                 OTG_GSL_WINDOW_END_X, params->gsl_window_end_x);
 127         REG_SET_2(OTG_GSL_WINDOW_Y, 0,
 128                 OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y,
 129                 OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y);
 130 }
 131 
 132 /**
 133  * Vupdate keepout can be set to a window to block the update lock for that pipe from changing.
 134  * Start offset begins with vstartup and goes for x number of clocks,
 135  * end offset starts from end of vupdate to x number of clocks.
 136  */
 137 void optc2_set_vupdate_keepout(struct timing_generator *optc,
 138                    const struct vupdate_keepout_params *params)
 139 {
 140         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 141 
 142         REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
 143                 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset,
 144                 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset,
 145                 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
 146 }
 147 
 148 void optc2_set_gsl_source_select(
 149                 struct timing_generator *optc,
 150                 int group_idx,
 151                 uint32_t gsl_ready_signal)
 152 {
 153         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 154 
 155         switch (group_idx) {
 156         case 1:
 157                 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
 158                 break;
 159         case 2:
 160                 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
 161                 break;
 162         case 3:
 163                 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);
 164                 break;
 165         default:
 166                 break;
 167         }
 168 }
 169 
 170 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 171 /* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
 172 void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
 173                                         int x_position,
 174                                         int line_num)
 175 {
 176         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 177 
 178         REG_SET_2(OTG_DSC_START_POSITION, 0,
 179                         OTG_DSC_START_POSITION_X, x_position,
 180                         OTG_DSC_START_POSITION_LINE_NUM, line_num);
 181 }
 182 
 183 /* Set DSC-related configuration.
 184  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
 185  *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
 186  *   dsc_slice_width: Slice width in pixels
 187  */
 188 void optc2_set_dsc_config(struct timing_generator *optc,
 189                                         enum optc_dsc_mode dsc_mode,
 190                                         uint32_t dsc_bytes_per_pixel,
 191                                         uint32_t dsc_slice_width)
 192 {
 193         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 194 
 195         REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
 196                 OPTC_DSC_MODE, dsc_mode);
 197 
 198         REG_SET(OPTC_BYTES_PER_PIXEL, 0,
 199                 OPTC_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
 200 
 201         REG_UPDATE(OPTC_WIDTH_CONTROL,
 202                 OPTC_DSC_SLICE_WIDTH, dsc_slice_width);
 203 }
 204 #endif
 205 
 206 /**
 207  * PTI i think is already done somewhere else for 2ka
 208  * (opp?, please double check.
 209  * OPTC side only has 1 register to set for PTI_ENABLE)
 210  */
 211 
 212 void optc2_set_odm_bypass(struct timing_generator *optc,
 213                 const struct dc_crtc_timing *dc_crtc_timing)
 214 {
 215         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 216         uint32_t h_div_2 = 0;
 217 
 218         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 219                         OPTC_NUM_OF_INPUT_SEGMENT, 0,
 220                         OPTC_SEG0_SRC_SEL, optc->inst,
 221                         OPTC_SEG1_SRC_SEL, 0xf);
 222         REG_WRITE(OTG_H_TIMING_CNTL, 0);
 223 
 224         h_div_2 = optc1_is_two_pixels_per_containter(dc_crtc_timing);
 225         REG_UPDATE(OTG_H_TIMING_CNTL,
 226                         OTG_H_TIMING_DIV_BY2, h_div_2);
 227         REG_SET(OPTC_MEMORY_CONFIG, 0,
 228                         OPTC_MEM_SEL, 0);
 229         optc1->opp_count = 1;
 230 }
 231 
 232 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
 233                 struct dc_crtc_timing *timing)
 234 {
 235         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 236         int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
 237                         / opp_cnt;
 238         uint32_t memory_mask;
 239         uint32_t data_fmt = 0;
 240 
 241         ASSERT(opp_cnt == 2);
 242 
 243         /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
 244          * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
 245          * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
 246          * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
 247          *              MASTER_UPDATE_LOCK_DB_X, 160,
 248          *              MASTER_UPDATE_LOCK_DB_Y, 240);
 249          */
 250 
 251         /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
 252          * however, for ODM combine we can simplify by always using 4.
 253          * To make sure there's no overlap, each instance "reserves" 2 memories and
 254          * they are uniquely combined here.
 255          */
 256         memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
 257 
 258         if (REG(OPTC_MEMORY_CONFIG))
 259                 REG_SET(OPTC_MEMORY_CONFIG, 0,
 260                         OPTC_MEM_SEL, memory_mask);
 261 
 262         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
 263                 data_fmt = 1;
 264         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 265                 data_fmt = 2;
 266 
 267         REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
 268 
 269         REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
 270                         OPTC_NUM_OF_INPUT_SEGMENT, 1,
 271                         OPTC_SEG0_SRC_SEL, opp_id[0],
 272                         OPTC_SEG1_SRC_SEL, opp_id[1]);
 273 
 274         REG_UPDATE(OPTC_WIDTH_CONTROL,
 275                         OPTC_SEGMENT_WIDTH, mpcc_hactive);
 276 
 277         REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
 278         optc1->opp_count = opp_cnt;
 279 }
 280 
 281 void optc2_get_optc_source(struct timing_generator *optc,
 282                 uint32_t *num_of_src_opp,
 283                 uint32_t *src_opp_id_0,
 284                 uint32_t *src_opp_id_1)
 285 {
 286         uint32_t num_of_input_segments;
 287         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 288 
 289         REG_GET_3(OPTC_DATA_SOURCE_SELECT,
 290                         OPTC_NUM_OF_INPUT_SEGMENT, &num_of_input_segments,
 291                         OPTC_SEG0_SRC_SEL, src_opp_id_0,
 292                         OPTC_SEG1_SRC_SEL, src_opp_id_1);
 293 
 294         if (num_of_input_segments == 1)
 295                 *num_of_src_opp = 2;
 296         else
 297                 *num_of_src_opp = 1;
 298 
 299         /* Work around VBIOS not updating OPTC_NUM_OF_INPUT_SEGMENT */
 300         if (*src_opp_id_1 == 0xf)
 301                 *num_of_src_opp = 1;
 302 }
 303 
 304 void optc2_set_dwb_source(struct timing_generator *optc,
 305                 uint32_t dwb_pipe_inst)
 306 {
 307         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 308 
 309         if (dwb_pipe_inst == 0)
 310                 REG_UPDATE(DWB_SOURCE_SELECT,
 311                                 OPTC_DWB0_SOURCE_SELECT, optc->inst);
 312         else if (dwb_pipe_inst == 1)
 313                 REG_UPDATE(DWB_SOURCE_SELECT,
 314                                 OPTC_DWB1_SOURCE_SELECT, optc->inst);
 315 }
 316 
 317 void optc2_triplebuffer_lock(struct timing_generator *optc)
 318 {
 319         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 320 
 321         REG_SET(OTG_GLOBAL_CONTROL0, 0,
 322                 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
 323 
 324         REG_SET(OTG_VUPDATE_KEEPOUT, 0,
 325                 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
 326 
 327         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 328                 OTG_MASTER_UPDATE_LOCK, 1);
 329 
 330         if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
 331                 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
 332                                 UPDATE_LOCK_STATUS, 1,
 333                                 1, 10);
 334 }
 335 
 336 void optc2_triplebuffer_unlock(struct timing_generator *optc)
 337 {
 338         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 339 
 340         REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
 341                 OTG_MASTER_UPDATE_LOCK, 0);
 342 
 343         REG_SET(OTG_VUPDATE_KEEPOUT, 0,
 344                 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 0);
 345 
 346 }
 347 
 348 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
 349 {
 350         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 351         uint32_t v_blank_start = 0;
 352         uint32_t h_blank_start = 0;
 353 
 354         REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
 355 
 356         REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
 357                         DIG_UPDATE_LOCATION, 20);
 358 
 359         REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
 360 
 361         REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
 362 
 363         REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
 364                         MASTER_UPDATE_LOCK_DB_X,
 365                         h_blank_start - 200 - 1,
 366                         MASTER_UPDATE_LOCK_DB_Y,
 367                         v_blank_start - 1);
 368 }
 369 
 370 void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
 371 {
 372         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 373 
 374         REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
 375                                 MASTER_UPDATE_LOCK_DB_X,
 376                                 0,
 377                                 MASTER_UPDATE_LOCK_DB_Y,
 378                                 0);
 379 
 380         REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0,
 381                                 DIG_UPDATE_LOCATION, 0);
 382 
 383         REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);
 384 }
 385 
 386 void optc2_setup_manual_trigger(struct timing_generator *optc)
 387 {
 388         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 389 
 390         REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
 391                         MANUAL_FLOW_CONTROL, 1);
 392 
 393         REG_SET(OTG_GLOBAL_CONTROL2, 0,
 394                         MANUAL_FLOW_CONTROL_SEL, optc->inst);
 395 
 396         REG_SET_8(OTG_TRIGA_CNTL, 0,
 397                         OTG_TRIGA_SOURCE_SELECT, 22,
 398                         OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
 399                         OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
 400                         OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
 401                         OTG_TRIGA_POLARITY_SELECT, 0,
 402                         OTG_TRIGA_FREQUENCY_SELECT, 0,
 403                         OTG_TRIGA_DELAY, 0,
 404                         OTG_TRIGA_CLEAR, 1);
 405 }
 406 
 407 void optc2_program_manual_trigger(struct timing_generator *optc)
 408 {
 409         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 410 
 411         REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
 412                         OTG_TRIGA_MANUAL_TRIG, 1);
 413 }
 414 
 415 static struct timing_generator_funcs dcn20_tg_funcs = {
 416                 .validate_timing = optc1_validate_timing,
 417                 .program_timing = optc1_program_timing,
 418                 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
 419                 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
 420                 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
 421                 .program_global_sync = optc1_program_global_sync,
 422                 .enable_crtc = optc2_enable_crtc,
 423                 .disable_crtc = optc1_disable_crtc,
 424                 /* used by enable_timing_synchronization. Not need for FPGA */
 425                 .is_counter_moving = optc1_is_counter_moving,
 426                 .get_position = optc1_get_position,
 427                 .get_frame_count = optc1_get_vblank_counter,
 428                 .get_scanoutpos = optc1_get_crtc_scanoutpos,
 429                 .get_otg_active_size = optc1_get_otg_active_size,
 430                 .set_early_control = optc1_set_early_control,
 431                 /* used by enable_timing_synchronization. Not need for FPGA */
 432                 .wait_for_state = optc1_wait_for_state,
 433                 .set_blank = optc1_set_blank,
 434                 .is_blanked = optc1_is_blanked,
 435                 .set_blank_color = optc1_program_blank_color,
 436                 .enable_reset_trigger = optc1_enable_reset_trigger,
 437                 .enable_crtc_reset = optc1_enable_crtc_reset,
 438                 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
 439                 .triplebuffer_lock = optc2_triplebuffer_lock,
 440                 .triplebuffer_unlock = optc2_triplebuffer_unlock,
 441                 .disable_reset_trigger = optc1_disable_reset_trigger,
 442                 .lock = optc1_lock,
 443                 .unlock = optc1_unlock,
 444                 .lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
 445                 .lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
 446                 .enable_optc_clock = optc1_enable_optc_clock,
 447                 .set_drr = optc1_set_drr,
 448                 .set_static_screen_control = optc1_set_static_screen_control,
 449                 .program_stereo = optc1_program_stereo,
 450                 .is_stereo_left_eye = optc1_is_stereo_left_eye,
 451                 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
 452                 .tg_init = optc1_tg_init,
 453                 .is_tg_enabled = optc1_is_tg_enabled,
 454                 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
 455                 .clear_optc_underflow = optc1_clear_optc_underflow,
 456                 .setup_global_swap_lock = NULL,
 457                 .get_crc = optc1_get_crc,
 458                 .configure_crc = optc1_configure_crc,
 459 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 460                 .set_dsc_config = optc2_set_dsc_config,
 461 #endif
 462                 .set_dwb_source = optc2_set_dwb_source,
 463                 .set_odm_bypass = optc2_set_odm_bypass,
 464                 .set_odm_combine = optc2_set_odm_combine,
 465                 .get_optc_source = optc2_get_optc_source,
 466                 .set_gsl = optc2_set_gsl,
 467                 .set_gsl_source_select = optc2_set_gsl_source_select,
 468                 .set_vtg_params = optc1_set_vtg_params,
 469                 .program_manual_trigger = optc2_program_manual_trigger,
 470                 .setup_manual_trigger = optc2_setup_manual_trigger,
 471                 .is_matching_timing = optc1_is_matching_timing
 472 };
 473 
 474 void dcn20_timing_generator_init(struct optc *optc1)
 475 {
 476         optc1->base.funcs = &dcn20_tg_funcs;
 477 
 478         optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
 479         optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
 480 
 481         optc1->min_h_blank = 32;
 482         optc1->min_v_blank = 3;
 483         optc1->min_v_blank_interlace = 5;
 484         optc1->min_h_sync_width = 4;//  Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
 485         optc1->min_v_sync_width = 1;
 486 }
 487
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