drivers/gpu/drm/amd/display/dc/dce/dce

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   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 
  27 #ifndef _DCE_DMCU_H_
  28 #define _DCE_DMCU_H_
  29 
  30 #include "dmcu.h"
  31 
  32 #define DMCU_COMMON_REG_LIST_DCE_BASE() \
  33         SR(DMCU_CTRL), \
  34         SR(DMCU_STATUS), \
  35         SR(DMCU_RAM_ACCESS_CTRL), \
  36         SR(DMCU_IRAM_WR_CTRL), \
  37         SR(DMCU_IRAM_WR_DATA), \
  38         SR(MASTER_COMM_DATA_REG1), \
  39         SR(MASTER_COMM_DATA_REG2), \
  40         SR(MASTER_COMM_DATA_REG3), \
  41         SR(MASTER_COMM_CMD_REG), \
  42         SR(MASTER_COMM_CNTL_REG), \
  43         SR(DMCU_IRAM_RD_CTRL), \
  44         SR(DMCU_IRAM_RD_DATA), \
  45         SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
  46         SR(SMU_INTERRUPT_CONTROL), \
  47         SR(DC_DMCU_SCRATCH)
  48 
  49 #define DMCU_DCE80_REG_LIST() \
  50         SR(DMCU_CTRL), \
  51         SR(DMCU_STATUS), \
  52         SR(DMCU_RAM_ACCESS_CTRL), \
  53         SR(DMCU_IRAM_WR_CTRL), \
  54         SR(DMCU_IRAM_WR_DATA), \
  55         SR(MASTER_COMM_DATA_REG1), \
  56         SR(MASTER_COMM_DATA_REG2), \
  57         SR(MASTER_COMM_DATA_REG3), \
  58         SR(MASTER_COMM_CMD_REG), \
  59         SR(MASTER_COMM_CNTL_REG), \
  60         SR(DMCU_IRAM_RD_CTRL), \
  61         SR(DMCU_IRAM_RD_DATA), \
  62         SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
  63         SR(SMU_INTERRUPT_CONTROL), \
  64         SR(DC_DMCU_SCRATCH)
  65 
  66 #define DMCU_DCE110_COMMON_REG_LIST() \
  67         DMCU_COMMON_REG_LIST_DCE_BASE(), \
  68         SR(DCI_MEM_PWR_STATUS)
  69 
  70 #define DMCU_DCN10_REG_LIST()\
  71         DMCU_COMMON_REG_LIST_DCE_BASE(), \
  72         SR(DMU_MEM_PWR_CNTL)
  73 
  74 #define DMCU_SF(reg_name, field_name, post_fix)\
  75         .field_name = reg_name ## __ ## field_name ## post_fix
  76 
  77 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
  78         DMCU_SF(DMCU_CTRL, \
  79                         DMCU_ENABLE, mask_sh), \
  80         DMCU_SF(DMCU_STATUS, \
  81                         UC_IN_STOP_MODE, mask_sh), \
  82         DMCU_SF(DMCU_STATUS, \
  83                         UC_IN_RESET, mask_sh), \
  84         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
  85                         IRAM_HOST_ACCESS_EN, mask_sh), \
  86         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
  87                         IRAM_WR_ADDR_AUTO_INC, mask_sh), \
  88         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
  89                         IRAM_RD_ADDR_AUTO_INC, mask_sh), \
  90         DMCU_SF(MASTER_COMM_CMD_REG, \
  91                         MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
  92         DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
  93         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
  94                         STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
  95         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
  96                         STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
  97         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
  98                         STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
  99         DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
 100                         STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
 101         DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 102 
 103 #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
 104         DMCU_SF(DMCU_CTRL, \
 105                         DMCU_ENABLE, mask_sh), \
 106         DMCU_SF(DMCU_STATUS, \
 107                         UC_IN_STOP_MODE, mask_sh), \
 108         DMCU_SF(DMCU_STATUS, \
 109                         UC_IN_RESET, mask_sh), \
 110         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 111                         IRAM_HOST_ACCESS_EN, mask_sh), \
 112         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 113                         IRAM_WR_ADDR_AUTO_INC, mask_sh), \
 114         DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
 115                         IRAM_RD_ADDR_AUTO_INC, mask_sh), \
 116         DMCU_SF(MASTER_COMM_CMD_REG, \
 117                         MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 118         DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
 119         DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 120 
 121 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
 122         DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 123         DMCU_SF(DCI_MEM_PWR_STATUS, \
 124                 DMCU_IRAM_MEM_PWR_STATE, mask_sh)
 125 
 126 #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
 127         DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 128         DMCU_SF(DMU_MEM_PWR_CNTL, \
 129                         DMCU_IRAM_MEM_PWR_STATE, mask_sh)
 130 
 131 #define DMCU_REG_FIELD_LIST(type) \
 132         type DMCU_IRAM_MEM_PWR_STATE; \
 133         type IRAM_HOST_ACCESS_EN; \
 134         type IRAM_WR_ADDR_AUTO_INC; \
 135         type IRAM_RD_ADDR_AUTO_INC; \
 136         type DMCU_ENABLE; \
 137         type UC_IN_STOP_MODE; \
 138         type UC_IN_RESET; \
 139         type MASTER_COMM_CMD_REG_BYTE0; \
 140         type MASTER_COMM_INTERRUPT; \
 141         type DPHY_RX_FAST_TRAINING_CAPABLE; \
 142         type DPHY_LOAD_BS_COUNT; \
 143         type STATIC_SCREEN1_INT_TO_UC_EN; \
 144         type STATIC_SCREEN2_INT_TO_UC_EN; \
 145         type STATIC_SCREEN3_INT_TO_UC_EN; \
 146         type STATIC_SCREEN4_INT_TO_UC_EN; \
 147         type DP_SEC_GSP0_LINE_NUM; \
 148         type DP_SEC_GSP0_PRIORITY; \
 149         type DC_SMU_INT_ENABLE
 150 
 151 struct dce_dmcu_shift {
 152         DMCU_REG_FIELD_LIST(uint8_t);
 153 };
 154 
 155 struct dce_dmcu_mask {
 156         DMCU_REG_FIELD_LIST(uint32_t);
 157 };
 158 
 159 struct dce_dmcu_registers {
 160         uint32_t DMCU_CTRL;
 161         uint32_t DMCU_STATUS;
 162         uint32_t DMCU_RAM_ACCESS_CTRL;
 163         uint32_t DCI_MEM_PWR_STATUS;
 164         uint32_t DMU_MEM_PWR_CNTL;
 165         uint32_t DMCU_IRAM_WR_CTRL;
 166         uint32_t DMCU_IRAM_WR_DATA;
 167 
 168         uint32_t MASTER_COMM_DATA_REG1;
 169         uint32_t MASTER_COMM_DATA_REG2;
 170         uint32_t MASTER_COMM_DATA_REG3;
 171         uint32_t MASTER_COMM_CMD_REG;
 172         uint32_t MASTER_COMM_CNTL_REG;
 173         uint32_t DMCU_IRAM_RD_CTRL;
 174         uint32_t DMCU_IRAM_RD_DATA;
 175         uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
 176         uint32_t SMU_INTERRUPT_CONTROL;
 177         uint32_t DC_DMCU_SCRATCH;
 178 };
 179 
 180 struct dce_dmcu {
 181         struct dmcu base;
 182         const struct dce_dmcu_registers *regs;
 183         const struct dce_dmcu_shift *dmcu_shift;
 184         const struct dce_dmcu_mask *dmcu_mask;
 185 };
 186 
 187 /*******************************************************************
 188  *   MASTER_COMM_DATA_REG1   Bit position    Data
 189  *                           7:0                    hyst_frames[7:0]
 190  *                           14:8               hyst_lines[6:0]
 191  *                           15             RFB_UPDATE_AUTO_EN
 192  *                           18:16              phy_num[2:0]
 193  *                           21:19              dcp_sel[2:0]
 194  *                           22             phy_type
 195  *                           23             frame_cap_ind
 196  *                           26:24              aux_chan[2:0]
 197  *                           30:27              aux_repeat[3:0]
 198  *                           31:31              reserved[31:31]
 199  ******************************************************************/
 200 union dce_dmcu_psr_config_data_reg1 {
 201         struct {
 202                 unsigned int timehyst_frames:8;                  /*[7:0]*/
 203                 unsigned int hyst_lines:7;                       /*[14:8]*/
 204                 unsigned int rfb_update_auto_en:1;               /*[15:15]*/
 205                 unsigned int dp_port_num:3;                      /*[18:16]*/
 206                 unsigned int dcp_sel:3;                          /*[21:19]*/
 207                 unsigned int phy_type:1;                         /*[22:22]*/
 208                 unsigned int frame_cap_ind:1;                    /*[23:23]*/
 209                 unsigned int aux_chan:3;                         /*[26:24]*/
 210                 unsigned int aux_repeat:4;                       /*[30:27]*/
 211                 unsigned int allow_smu_optimizations:1;         /*[31:31]*/
 212         } bits;
 213         unsigned int u32All;
 214 };
 215 
 216 /*******************************************************************
 217  *   MASTER_COMM_DATA_REG2
 218  *******************************************************************/
 219 union dce_dmcu_psr_config_data_reg2 {
 220         struct {
 221                 unsigned int dig_fe:3;                  /*[2:0]*/
 222                 unsigned int dig_be:3;                  /*[5:3]*/
 223                 unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
 224                 unsigned int reserved:9;                /*[15:7]*/
 225                 unsigned int frame_delay:8;             /*[23:16]*/
 226                 unsigned int smu_phy_id:4;              /*[27:24]*/
 227                 unsigned int num_of_controllers:4;      /*[31:28]*/
 228         } bits;
 229         unsigned int u32All;
 230 };
 231 
 232 /*******************************************************************
 233  *   MASTER_COMM_DATA_REG3
 234  *******************************************************************/
 235 union dce_dmcu_psr_config_data_reg3 {
 236         struct {
 237                 unsigned int psr_level:16;      /*[15:0]*/
 238                 unsigned int link_rate:4;       /*[19:16]*/
 239                 unsigned int reserved:12;        /*[31:20]*/
 240         } bits;
 241         unsigned int u32All;
 242 };
 243 
 244 union dce_dmcu_psr_config_data_wait_loop_reg1 {
 245         struct {
 246                 unsigned int wait_loop:16; /* [15:0] */
 247                 unsigned int reserved:16; /* [31:16] */
 248         } bits;
 249         unsigned int u32;
 250 };
 251 
 252 struct dmcu *dce_dmcu_create(
 253         struct dc_context *ctx,
 254         const struct dce_dmcu_registers *regs,
 255         const struct dce_dmcu_shift *dmcu_shift,
 256         const struct dce_dmcu_mask *dmcu_mask);
 257 
 258 struct dmcu *dcn10_dmcu_create(
 259         struct dc_context *ctx,
 260         const struct dce_dmcu_registers *regs,
 261         const struct dce_dmcu_shift *dmcu_shift,
 262         const struct dce_dmcu_mask *dmcu_mask);
 263 
 264 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 265 struct dmcu *dcn20_dmcu_create(
 266         struct dc_context *ctx,
 267         const struct dce_dmcu_registers *regs,
 268         const struct dce_dmcu_shift *dmcu_shift,
 269         const struct dce_dmcu_mask *dmcu_mask);
 270 #endif
 271 
 272 void dce_dmcu_destroy(struct dmcu **dmcu);
 273 
 274 static const uint32_t abm_gain_stepsize = 0x0060;
 275 
 276 #endif /* _DCE_ABM_H_ */
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root/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

INCLUDED FROM
