root/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

INCLUDED FROM

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 
  27 #ifndef _DCE_ABM_H_
  28 #define _DCE_ABM_H_
  29 
  30 #include "abm.h"
  31 
  32 #define ABM_COMMON_REG_LIST_DCE_BASE() \
  33         SR(BL_PWM_PERIOD_CNTL), \
  34         SR(BL_PWM_CNTL), \
  35         SR(BL_PWM_CNTL2), \
  36         SR(BL_PWM_GRP1_REG_LOCK), \
  37         SR(LVTMA_PWRSEQ_REF_DIV), \
  38         SR(MASTER_COMM_CNTL_REG), \
  39         SR(MASTER_COMM_CMD_REG), \
  40         SR(MASTER_COMM_DATA_REG1)
  41 
  42 #define ABM_DCE110_COMMON_REG_LIST() \
  43         ABM_COMMON_REG_LIST_DCE_BASE(), \
  44         SR(DC_ABM1_HG_SAMPLE_RATE), \
  45         SR(DC_ABM1_LS_SAMPLE_RATE), \
  46         SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
  47         SR(DC_ABM1_HG_MISC_CTRL), \
  48         SR(DC_ABM1_IPCSC_COEFF_SEL), \
  49         SR(BL1_PWM_CURRENT_ABM_LEVEL), \
  50         SR(BL1_PWM_TARGET_ABM_LEVEL), \
  51         SR(BL1_PWM_USER_LEVEL), \
  52         SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
  53         SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
  54         SR(BIOS_SCRATCH_2)
  55 
  56 #define ABM_DCN10_REG_LIST(id)\
  57         ABM_COMMON_REG_LIST_DCE_BASE(), \
  58         SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
  59         SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
  60         SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
  61         SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
  62         SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
  63         SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
  64         SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
  65         SRI(BL1_PWM_USER_LEVEL, ABM, id), \
  66         SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
  67         SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
  68         NBIO_SR(BIOS_SCRATCH_2)
  69 
  70 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
  71 #define ABM_DCN20_REG_LIST() \
  72         ABM_COMMON_REG_LIST_DCE_BASE(), \
  73         SR(DC_ABM1_HG_SAMPLE_RATE), \
  74         SR(DC_ABM1_LS_SAMPLE_RATE), \
  75         SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
  76         SR(DC_ABM1_HG_MISC_CTRL), \
  77         SR(DC_ABM1_IPCSC_COEFF_SEL), \
  78         SR(BL1_PWM_CURRENT_ABM_LEVEL), \
  79         SR(BL1_PWM_TARGET_ABM_LEVEL), \
  80         SR(BL1_PWM_USER_LEVEL), \
  81         SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
  82         SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
  83         NBIO_SR(BIOS_SCRATCH_2)
  84 #endif
  85 
  86 #define ABM_SF(reg_name, field_name, post_fix)\
  87         .field_name = reg_name ## __ ## field_name ## post_fix
  88 
  89 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
  90         ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
  91         ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
  92         ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
  93         ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
  94         ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
  95         ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
  96         ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
  97         ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
  98         ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
  99         ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
 100         ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 101         ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
 102         ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
 103 
 104 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \
 105         ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 106         ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 107                         ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 108         ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 109                         ABM1_HG_VMAX_SEL, mask_sh), \
 110         ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 111                         ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
 112         ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 113                         ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
 114         ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 115                         ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
 116         ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 117                         ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
 118         ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
 119                         BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
 120         ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
 121                         BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
 122         ABM_SF(BL1_PWM_USER_LEVEL, \
 123                         BL1_PWM_USER_LEVEL, mask_sh), \
 124         ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 125                         ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
 126         ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 127                         ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
 128         ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 129                         ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 130         ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 131                         ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 132         ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 133                         ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 134 
 135 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \
 136         ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 137         ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 138                         ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 139         ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 140                         ABM1_HG_VMAX_SEL, mask_sh), \
 141         ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 142                         ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
 143         ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 144                         ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
 145         ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 146                         ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
 147         ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 148                         ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
 149         ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
 150                         BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
 151         ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
 152                         BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
 153         ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
 154                         BL1_PWM_USER_LEVEL, mask_sh), \
 155         ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 156                         ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
 157         ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 158                         ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
 159         ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 160                         ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 161         ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 162                         ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 163         ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 164                         ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 165 
 166 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 167 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
 168 #endif
 169 
 170 #define ABM_REG_FIELD_LIST(type) \
 171         type ABM1_HG_NUM_OF_BINS_SEL; \
 172         type ABM1_HG_VMAX_SEL; \
 173         type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
 174         type ABM1_IPCSC_COEFF_SEL_R; \
 175         type ABM1_IPCSC_COEFF_SEL_G; \
 176         type ABM1_IPCSC_COEFF_SEL_B; \
 177         type BL1_PWM_CURRENT_ABM_LEVEL; \
 178         type BL1_PWM_TARGET_ABM_LEVEL; \
 179         type BL1_PWM_USER_LEVEL; \
 180         type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
 181         type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
 182         type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
 183         type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
 184         type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
 185         type BL_PWM_PERIOD; \
 186         type BL_PWM_PERIOD_BITCNT; \
 187         type BL_ACTIVE_INT_FRAC_CNT; \
 188         type BL_PWM_FRACTIONAL_EN; \
 189         type MASTER_COMM_INTERRUPT; \
 190         type MASTER_COMM_CMD_REG_BYTE0; \
 191         type MASTER_COMM_CMD_REG_BYTE1; \
 192         type MASTER_COMM_CMD_REG_BYTE2; \
 193         type BL_PWM_REF_DIV; \
 194         type BL_PWM_EN; \
 195         type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
 196         type BL_PWM_GRP1_REG_LOCK; \
 197         type BL_PWM_GRP1_REG_UPDATE_PENDING
 198 
 199 struct dce_abm_shift {
 200         ABM_REG_FIELD_LIST(uint8_t);
 201 };
 202 
 203 struct dce_abm_mask {
 204         ABM_REG_FIELD_LIST(uint32_t);
 205 };
 206 
 207 struct dce_abm_registers {
 208         uint32_t BL_PWM_PERIOD_CNTL;
 209         uint32_t BL_PWM_CNTL;
 210         uint32_t BL_PWM_CNTL2;
 211         uint32_t LVTMA_PWRSEQ_REF_DIV;
 212         uint32_t DC_ABM1_HG_SAMPLE_RATE;
 213         uint32_t DC_ABM1_LS_SAMPLE_RATE;
 214         uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
 215         uint32_t DC_ABM1_HG_MISC_CTRL;
 216         uint32_t DC_ABM1_IPCSC_COEFF_SEL;
 217         uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
 218         uint32_t BL1_PWM_TARGET_ABM_LEVEL;
 219         uint32_t BL1_PWM_USER_LEVEL;
 220         uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
 221         uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
 222         uint32_t MASTER_COMM_CNTL_REG;
 223         uint32_t MASTER_COMM_CMD_REG;
 224         uint32_t MASTER_COMM_DATA_REG1;
 225         uint32_t BIOS_SCRATCH_2;
 226         uint32_t BL_PWM_GRP1_REG_LOCK;
 227 };
 228 
 229 struct dce_abm {
 230         struct abm base;
 231         const struct dce_abm_registers *regs;
 232         const struct dce_abm_shift *abm_shift;
 233         const struct dce_abm_mask *abm_mask;
 234 };
 235 
 236 struct abm *dce_abm_create(
 237         struct dc_context *ctx,
 238         const struct dce_abm_registers *regs,
 239         const struct dce_abm_shift *abm_shift,
 240         const struct dce_abm_mask *abm_mask);
 241 
 242 void dce_abm_destroy(struct abm **abm);
 243 
 244 #endif /* _DCE_ABM_H_ */