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26 #ifndef _DCE_DCE_TRANSFORM_H_
27 #define _DCE_DCE_TRANSFORM_H_
28
29
30 #include "transform.h"
31
32 #define TO_DCE_TRANSFORM(transform)\
33 container_of(transform, struct dce_transform, base)
34
35 #define LB_TOTAL_NUMBER_OF_ENTRIES 1712
36 #define LB_BITS_PER_ENTRY 144
37
38 #define XFM_COMMON_REG_LIST_DCE_BASE(id) \
39 SRI(LB_DATA_FORMAT, LB, id), \
40 SRI(GAMUT_REMAP_CONTROL, DCP, id), \
41 SRI(GAMUT_REMAP_C11_C12, DCP, id), \
42 SRI(GAMUT_REMAP_C13_C14, DCP, id), \
43 SRI(GAMUT_REMAP_C21_C22, DCP, id), \
44 SRI(GAMUT_REMAP_C23_C24, DCP, id), \
45 SRI(GAMUT_REMAP_C31_C32, DCP, id), \
46 SRI(GAMUT_REMAP_C33_C34, DCP, id), \
47 SRI(OUTPUT_CSC_C11_C12, DCP, id), \
48 SRI(OUTPUT_CSC_C13_C14, DCP, id), \
49 SRI(OUTPUT_CSC_C21_C22, DCP, id), \
50 SRI(OUTPUT_CSC_C23_C24, DCP, id), \
51 SRI(OUTPUT_CSC_C31_C32, DCP, id), \
52 SRI(OUTPUT_CSC_C33_C34, DCP, id), \
53 SRI(OUTPUT_CSC_CONTROL, DCP, id), \
54 SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
55 SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
56 SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
57 SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
58 SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
59 SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
60 SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
61 SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
62 SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
63 SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
64 SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
65 SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
66 SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
67 SRI(REGAMMA_LUT_INDEX, DCP, id), \
68 SRI(REGAMMA_LUT_DATA, DCP, id), \
69 SRI(REGAMMA_CONTROL, DCP, id), \
70 SRI(DENORM_CONTROL, DCP, id), \
71 SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
72 SRI(OUT_ROUND_CONTROL, DCP, id), \
73 SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
74 SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
75 SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
76 SRI(SCL_MODE, SCL, id), \
77 SRI(SCL_TAP_CONTROL, SCL, id), \
78 SRI(SCL_CONTROL, SCL, id), \
79 SRI(SCL_BYPASS_CONTROL, SCL, id), \
80 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
81 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
82 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
83 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
84 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
85 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
86 SRI(VIEWPORT_START, SCL, id), \
87 SRI(VIEWPORT_SIZE, SCL, id), \
88 SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
89 SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
90 SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
91 SRI(SCL_VERT_FILTER_INIT, SCL, id), \
92 SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
93 SRI(LB_MEMORY_CTRL, LB, id), \
94 SRI(SCL_UPDATE, SCL, id), \
95 SRI(SCL_F_SHARP_CONTROL, SCL, id)
96
97 #define XFM_COMMON_REG_LIST_DCE80(id) \
98 XFM_COMMON_REG_LIST_DCE_BASE(id), \
99 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
100
101 #define XFM_COMMON_REG_LIST_DCE100(id) \
102 XFM_COMMON_REG_LIST_DCE_BASE(id), \
103 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
104 SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
105
106 #define XFM_COMMON_REG_LIST_DCE110(id) \
107 XFM_COMMON_REG_LIST_DCE_BASE(id), \
108 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
109 SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
110
111 #define XFM_SF(reg_name, field_name, post_fix)\
112 .field_name = reg_name ## __ ## field_name ## post_fix
113
114 #define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
115 XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
116 XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
117 XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
118 XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
119 XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
120 XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
121 XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
122 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
123 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
124 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
125 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
126 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
127 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
128 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
129 XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
130 XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
131 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
132 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
133 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
134 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
135 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
136 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
137 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
138 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
139 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
140 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
141 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
142 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
143 XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
144 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
145 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
146 XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
147 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
148 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
149 XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
150 XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
151 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
152 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
153 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
154 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
155 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
156 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
157 XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
158 XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
159 XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
160 XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
161 XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
162 XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
163 XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
164 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
165 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
166 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
167 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
168 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
169 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
170 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
171 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
172 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
173 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
174 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
175 XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
176 XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
177 XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
178 XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
179 XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
180 XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
181 XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
182 XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
183 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
184 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
185 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
186 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
187 XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
188 XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
189 XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
190 XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
191
192 #define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \
193 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
194 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
195 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
196 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
197
198 #define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \
199 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
200 XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
201 XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
202 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
203 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
204 XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
205 XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
206
207 #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
208 XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
209 XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
210 XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
211 XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
212 XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
213 XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
214 XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
215 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
216 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
217 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
218 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
219 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
220 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
221 XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \
222 XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
223 XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
224 XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
225 XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
226 XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
227 XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
228 XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
229 XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
230 XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
231 XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
232 XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
233 XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
234 XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
235 XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
236 XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
237 XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
238 XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
239 XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
240 XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
241 XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
242 XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
243 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
244 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
245 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
246 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
247 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
248 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
249 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
250 XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
251 XFM_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
252 XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
253 XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
254 XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
255 XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
256 XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
257 XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
258 XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
259 XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
260 XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
261 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
262 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
263 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
264 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
265 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
266 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
267 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
268 XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
269 XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
270 XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
271 XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
272 XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
273 XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
274 XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
275 XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
276 XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
277 XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
278 XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
279 XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
280 XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
281 XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
282 XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
283 XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \
284 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
285 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
286 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
287 XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
288 XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh)
289
290 #define XFM_REG_FIELD_LIST(type) \
291 type OUT_CLAMP_MIN_B_CB; \
292 type OUT_CLAMP_MAX_B_CB; \
293 type OUT_CLAMP_MIN_G_Y; \
294 type OUT_CLAMP_MAX_G_Y; \
295 type OUT_CLAMP_MIN_R_CR; \
296 type OUT_CLAMP_MAX_R_CR; \
297 type OUT_ROUND_TRUNC_MODE; \
298 type DCP_SPATIAL_DITHER_EN; \
299 type DCP_SPATIAL_DITHER_MODE; \
300 type DCP_SPATIAL_DITHER_DEPTH; \
301 type DCP_FRAME_RANDOM_ENABLE; \
302 type DCP_RGB_RANDOM_ENABLE; \
303 type DCP_HIGHPASS_RANDOM_ENABLE; \
304 type DENORM_MODE; \
305 type PIXEL_DEPTH; \
306 type PIXEL_EXPAN_MODE; \
307 type GAMUT_REMAP_C11; \
308 type GAMUT_REMAP_C12; \
309 type GAMUT_REMAP_C13; \
310 type GAMUT_REMAP_C14; \
311 type GAMUT_REMAP_C21; \
312 type GAMUT_REMAP_C22; \
313 type GAMUT_REMAP_C23; \
314 type GAMUT_REMAP_C24; \
315 type GAMUT_REMAP_C31; \
316 type GAMUT_REMAP_C32; \
317 type GAMUT_REMAP_C33; \
318 type GAMUT_REMAP_C34; \
319 type GRPH_GAMUT_REMAP_MODE; \
320 type OUTPUT_CSC_C11; \
321 type OUTPUT_CSC_C12; \
322 type OUTPUT_CSC_GRPH_MODE; \
323 type DCP_REGAMMA_MEM_PWR_DIS; \
324 type DCP_LUT_MEM_PWR_DIS; \
325 type REGAMMA_LUT_LIGHT_SLEEP_DIS; \
326 type DCP_LUT_LIGHT_SLEEP_DIS; \
327 type REGAMMA_CNTLA_EXP_REGION_START; \
328 type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \
329 type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \
330 type REGAMMA_CNTLA_EXP_REGION_END; \
331 type REGAMMA_CNTLA_EXP_REGION_END_BASE; \
332 type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \
333 type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \
334 type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \
335 type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \
336 type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \
337 type DCP_REGAMMA_MEM_PWR_STATE; \
338 type REGAMMA_LUT_MEM_PWR_STATE; \
339 type REGAMMA_LUT_WRITE_EN_MASK; \
340 type GRPH_REGAMMA_MODE; \
341 type SCL_MODE; \
342 type SCL_BYPASS_MODE; \
343 type SCL_PSCL_EN; \
344 type SCL_H_NUM_OF_TAPS; \
345 type SCL_V_NUM_OF_TAPS; \
346 type SCL_BOUNDARY_MODE; \
347 type EXT_OVERSCAN_LEFT; \
348 type EXT_OVERSCAN_RIGHT; \
349 type EXT_OVERSCAN_TOP; \
350 type EXT_OVERSCAN_BOTTOM; \
351 type SCL_COEFF_MEM_PWR_DIS; \
352 type SCL_COEFF_MEM_PWR_STATE; \
353 type SCL_C_RAM_FILTER_TYPE; \
354 type SCL_C_RAM_PHASE; \
355 type SCL_C_RAM_TAP_PAIR_IDX; \
356 type SCL_C_RAM_EVEN_TAP_COEF_EN; \
357 type SCL_C_RAM_EVEN_TAP_COEF; \
358 type SCL_C_RAM_ODD_TAP_COEF_EN; \
359 type SCL_C_RAM_ODD_TAP_COEF; \
360 type VIEWPORT_X_START; \
361 type VIEWPORT_Y_START; \
362 type VIEWPORT_HEIGHT; \
363 type VIEWPORT_WIDTH; \
364 type SCL_H_SCALE_RATIO; \
365 type SCL_V_SCALE_RATIO; \
366 type SCL_H_INIT_INT; \
367 type SCL_H_INIT_FRAC; \
368 type SCL_V_INIT_INT; \
369 type SCL_V_INIT_FRAC; \
370 type LB_MEMORY_CONFIG; \
371 type LB_MEMORY_SIZE; \
372 type SCL_V_2TAP_HARDCODE_COEF_EN; \
373 type SCL_H_2TAP_HARDCODE_COEF_EN; \
374 type SCL_COEF_UPDATE_COMPLETE; \
375 type ALPHA_EN
376
377 struct dce_transform_shift {
378 XFM_REG_FIELD_LIST(uint8_t);
379 };
380
381 struct dce_transform_mask {
382 XFM_REG_FIELD_LIST(uint32_t);
383 };
384
385 struct dce_transform_registers {
386 uint32_t LB_DATA_FORMAT;
387 uint32_t GAMUT_REMAP_CONTROL;
388 uint32_t GAMUT_REMAP_C11_C12;
389 uint32_t GAMUT_REMAP_C13_C14;
390 uint32_t GAMUT_REMAP_C21_C22;
391 uint32_t GAMUT_REMAP_C23_C24;
392 uint32_t GAMUT_REMAP_C31_C32;
393 uint32_t GAMUT_REMAP_C33_C34;
394 uint32_t OUTPUT_CSC_C11_C12;
395 uint32_t OUTPUT_CSC_C13_C14;
396 uint32_t OUTPUT_CSC_C21_C22;
397 uint32_t OUTPUT_CSC_C23_C24;
398 uint32_t OUTPUT_CSC_C31_C32;
399 uint32_t OUTPUT_CSC_C33_C34;
400 uint32_t OUTPUT_CSC_CONTROL;
401 uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
402 uint32_t REGAMMA_CNTLA_START_CNTL;
403 uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
404 uint32_t REGAMMA_CNTLA_END_CNTL1;
405 uint32_t REGAMMA_CNTLA_END_CNTL2;
406 uint32_t REGAMMA_CNTLA_REGION_0_1;
407 uint32_t REGAMMA_CNTLA_REGION_2_3;
408 uint32_t REGAMMA_CNTLA_REGION_4_5;
409 uint32_t REGAMMA_CNTLA_REGION_6_7;
410 uint32_t REGAMMA_CNTLA_REGION_8_9;
411 uint32_t REGAMMA_CNTLA_REGION_10_11;
412 uint32_t REGAMMA_CNTLA_REGION_12_13;
413 uint32_t REGAMMA_CNTLA_REGION_14_15;
414 uint32_t REGAMMA_LUT_WRITE_EN_MASK;
415 uint32_t REGAMMA_LUT_INDEX;
416 uint32_t REGAMMA_LUT_DATA;
417 uint32_t REGAMMA_CONTROL;
418 uint32_t DENORM_CONTROL;
419 uint32_t DCP_SPATIAL_DITHER_CNTL;
420 uint32_t OUT_ROUND_CONTROL;
421 uint32_t OUT_CLAMP_CONTROL_R_CR;
422 uint32_t OUT_CLAMP_CONTROL_G_Y;
423 uint32_t OUT_CLAMP_CONTROL_B_CB;
424 uint32_t SCL_MODE;
425 uint32_t SCL_TAP_CONTROL;
426 uint32_t SCL_CONTROL;
427 uint32_t SCL_BYPASS_CONTROL;
428 uint32_t EXT_OVERSCAN_LEFT_RIGHT;
429 uint32_t EXT_OVERSCAN_TOP_BOTTOM;
430 uint32_t SCL_VERT_FILTER_CONTROL;
431 uint32_t SCL_HORZ_FILTER_CONTROL;
432 uint32_t DCFE_MEM_PWR_CTRL;
433 uint32_t DCFE_MEM_PWR_STATUS;
434 uint32_t SCL_COEF_RAM_SELECT;
435 uint32_t SCL_COEF_RAM_TAP_DATA;
436 uint32_t VIEWPORT_START;
437 uint32_t VIEWPORT_SIZE;
438 uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
439 uint32_t SCL_VERT_FILTER_SCALE_RATIO;
440 uint32_t SCL_HORZ_FILTER_INIT;
441 uint32_t SCL_VERT_FILTER_INIT;
442 uint32_t SCL_AUTOMATIC_MODE_CONTROL;
443 uint32_t LB_MEMORY_CTRL;
444 uint32_t SCL_UPDATE;
445 uint32_t SCL_F_SHARP_CONTROL;
446 };
447
448 struct init_int_and_frac {
449 uint32_t integer;
450 uint32_t fraction;
451 };
452
453 struct scl_ratios_inits {
454 uint32_t h_int_scale_ratio;
455 uint32_t v_int_scale_ratio;
456 struct init_int_and_frac h_init;
457 struct init_int_and_frac v_init;
458 };
459
460 enum ram_filter_type {
461 FILTER_TYPE_RGB_Y_VERTICAL = 0,
462 FILTER_TYPE_CBCR_VERTICAL = 1,
463 FILTER_TYPE_RGB_Y_HORIZONTAL = 2,
464 FILTER_TYPE_CBCR_HORIZONTAL = 3,
465 FILTER_TYPE_ALPHA_VERTICAL = 4,
466 FILTER_TYPE_ALPHA_HORIZONTAL = 5,
467 };
468
469 struct dce_transform {
470 struct transform base;
471 const struct dce_transform_registers *regs;
472 const struct dce_transform_shift *xfm_shift;
473 const struct dce_transform_mask *xfm_mask;
474
475 const uint16_t *filter_v;
476 const uint16_t *filter_h;
477 const uint16_t *filter_v_c;
478 const uint16_t *filter_h_c;
479 int lb_pixel_depth_supported;
480 int lb_memory_size;
481 int lb_bits_per_entry;
482 bool prescaler_on;
483 };
484
485 void dce_transform_construct(struct dce_transform *xfm_dce,
486 struct dc_context *ctx,
487 uint32_t inst,
488 const struct dce_transform_registers *regs,
489 const struct dce_transform_shift *xfm_shift,
490 const struct dce_transform_mask *xfm_mask);
491
492 bool dce_transform_get_optimal_number_of_taps(
493 struct transform *xfm,
494 struct scaler_data *scl_data,
495 const struct scaling_taps *in_taps);
496
497 void dce110_opp_set_csc_adjustment(
498 struct transform *xfm,
499 const struct out_csc_color_matrix *tbl_entry);
500
501 void dce110_opp_set_csc_default(
502 struct transform *xfm,
503 const struct default_adjustment *default_adjust);
504
505
506 void dce110_opp_power_on_regamma_lut(
507 struct transform *xfm,
508 bool power_on);
509
510 void dce110_opp_program_regamma_pwl(
511 struct transform *xfm,
512 const struct pwl_params *params);
513
514 void dce110_opp_set_regamma_mode(struct transform *xfm,
515 enum opp_regamma mode);
516
517 #endif