root/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h

INCLUDED FROM

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef _DCE_IPP_H_
  27 #define _DCE_IPP_H_
  28 
  29 #include "ipp.h"
  30 
  31 #define TO_DCE_IPP(ipp)\
  32         container_of(ipp, struct dce_ipp, base)
  33 
  34 #define IPP_COMMON_REG_LIST_DCE_BASE(id) \
  35         SRI(CUR_UPDATE, DCP, id), \
  36         SRI(CUR_CONTROL, DCP, id), \
  37         SRI(CUR_POSITION, DCP, id), \
  38         SRI(CUR_HOT_SPOT, DCP, id), \
  39         SRI(CUR_COLOR1, DCP, id), \
  40         SRI(CUR_COLOR2, DCP, id), \
  41         SRI(CUR_SIZE, DCP, id), \
  42         SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
  43         SRI(CUR_SURFACE_ADDRESS, DCP, id), \
  44         SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
  45         SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \
  46         SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
  47         SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
  48         SRI(INPUT_GAMMA_CONTROL, DCP, id), \
  49         SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
  50         SRI(DC_LUT_RW_MODE, DCP, id), \
  51         SRI(DC_LUT_CONTROL, DCP, id), \
  52         SRI(DC_LUT_RW_INDEX, DCP, id), \
  53         SRI(DC_LUT_SEQ_COLOR, DCP, id), \
  54         SRI(DEGAMMA_CONTROL, DCP, id)
  55 
  56 #define IPP_DCE100_REG_LIST_DCE_BASE(id) \
  57         IPP_COMMON_REG_LIST_DCE_BASE(id), \
  58         SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
  59 
  60 #define IPP_DCE110_REG_LIST_DCE_BASE(id) \
  61         IPP_COMMON_REG_LIST_DCE_BASE(id), \
  62         SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
  63 
  64 #define IPP_SF(reg_name, field_name, post_fix)\
  65         .field_name = reg_name ## __ ## field_name ## post_fix
  66 
  67 #define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
  68         IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
  69         IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
  70         IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
  71         IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
  72         IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
  73         IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
  74         IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
  75         IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
  76         IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
  77         IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
  78         IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
  79         IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
  80         IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
  81         IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
  82         IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
  83         IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
  84         IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
  85         IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
  86         IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
  87         IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
  88         IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
  89         IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
  90         IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
  91         IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
  92         IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
  93         IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
  94         IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
  95         IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
  96         IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
  97         IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
  98         IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
  99         IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
 100         IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
 101         IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
 102         IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
 103         IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
 104         IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
 105 
 106 #define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
 107         IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 108         IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
 109 
 110 #define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \
 111         IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
 112         IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \
 113         IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \
 114         IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
 115         IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
 116         IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
 117         IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
 118         IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
 119         IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
 120         IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
 121         IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
 122         IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
 123         IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
 124         IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
 125         IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
 126         IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \
 127         IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
 128         IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
 129         IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
 130         IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
 131         IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
 132         IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
 133         IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
 134         IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
 135         IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
 136         IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
 137         IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
 138         IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
 139         IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
 140         IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
 141         IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
 142         IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
 143         IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
 144         IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
 145         IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
 146         IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
 147         IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
 148         IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
 149 
 150 #define IPP_REG_FIELD_LIST(type) \
 151         type CURSOR_UPDATE_LOCK; \
 152         type CURSOR_EN; \
 153         type CURSOR_X_POSITION; \
 154         type CURSOR_Y_POSITION; \
 155         type CURSOR_HOT_SPOT_X; \
 156         type CURSOR_HOT_SPOT_Y; \
 157         type CURSOR_MODE; \
 158         type CURSOR_2X_MAGNIFY; \
 159         type CUR_INV_TRANS_CLAMP; \
 160         type CUR_COLOR1_BLUE; \
 161         type CUR_COLOR1_GREEN; \
 162         type CUR_COLOR1_RED; \
 163         type CUR_COLOR2_BLUE; \
 164         type CUR_COLOR2_GREEN; \
 165         type CUR_COLOR2_RED; \
 166         type CURSOR_WIDTH; \
 167         type CURSOR_HEIGHT; \
 168         type CURSOR_SURFACE_ADDRESS_HIGH; \
 169         type CURSOR_SURFACE_ADDRESS; \
 170         type GRPH_PRESCALE_BYPASS; \
 171         type GRPH_PRESCALE_SCALE_R; \
 172         type GRPH_PRESCALE_BIAS_R; \
 173         type GRPH_PRESCALE_SCALE_G; \
 174         type GRPH_PRESCALE_BIAS_G; \
 175         type GRPH_PRESCALE_SCALE_B; \
 176         type GRPH_PRESCALE_BIAS_B; \
 177         type GRPH_INPUT_GAMMA_MODE; \
 178         type DCP_LUT_MEM_PWR_DIS; \
 179         type DC_LUT_WRITE_EN_MASK; \
 180         type DC_LUT_RW_MODE; \
 181         type DC_LUT_DATA_R_FORMAT; \
 182         type DC_LUT_DATA_G_FORMAT; \
 183         type DC_LUT_DATA_B_FORMAT; \
 184         type DC_LUT_RW_INDEX; \
 185         type DC_LUT_SEQ_COLOR; \
 186         type GRPH_DEGAMMA_MODE; \
 187         type CURSOR_DEGAMMA_MODE; \
 188         type CURSOR2_DEGAMMA_MODE
 189 
 190 struct dce_ipp_shift {
 191         IPP_REG_FIELD_LIST(uint8_t);
 192 };
 193 
 194 struct dce_ipp_mask {
 195         IPP_REG_FIELD_LIST(uint32_t);
 196 };
 197 
 198 struct dce_ipp_registers {
 199         uint32_t CUR_UPDATE;
 200         uint32_t CUR_CONTROL;
 201         uint32_t CUR_POSITION;
 202         uint32_t CUR_HOT_SPOT;
 203         uint32_t CUR_COLOR1;
 204         uint32_t CUR_COLOR2;
 205         uint32_t CUR_SIZE;
 206         uint32_t CUR_SURFACE_ADDRESS_HIGH;
 207         uint32_t CUR_SURFACE_ADDRESS;
 208         uint32_t PRESCALE_GRPH_CONTROL;
 209         uint32_t PRESCALE_VALUES_GRPH_R;
 210         uint32_t PRESCALE_VALUES_GRPH_G;
 211         uint32_t PRESCALE_VALUES_GRPH_B;
 212         uint32_t INPUT_GAMMA_CONTROL;
 213         uint32_t DCFE_MEM_PWR_CTRL;
 214         uint32_t DC_LUT_WRITE_EN_MASK;
 215         uint32_t DC_LUT_RW_MODE;
 216         uint32_t DC_LUT_CONTROL;
 217         uint32_t DC_LUT_RW_INDEX;
 218         uint32_t DC_LUT_SEQ_COLOR;
 219         uint32_t DEGAMMA_CONTROL;
 220 };
 221 
 222 struct dce_ipp {
 223         struct input_pixel_processor base;
 224         const struct dce_ipp_registers *regs;
 225         const struct dce_ipp_shift *ipp_shift;
 226         const struct dce_ipp_mask *ipp_mask;
 227 };
 228 
 229 void dce_ipp_construct(struct dce_ipp *ipp_dce,
 230         struct dc_context *ctx,
 231         int inst,
 232         const struct dce_ipp_registers *regs,
 233         const struct dce_ipp_shift *ipp_shift,
 234         const struct dce_ipp_mask *ipp_mask);
 235 
 236 void dce_ipp_destroy(struct input_pixel_processor **ipp);
 237 
 238 #endif /* _DCE_IPP_H_ */