drivers/gpu/drm/amd/display/dc/dce/dce_mem

/* [<][>][^][v][top][bottom][index][help] */
   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #ifndef __DCE_MEM_INPUT_H__
  26 #define __DCE_MEM_INPUT_H__
  27 
  28 #include "dc_hw_types.h"
  29 #include "mem_input.h"
  30 
  31 #define TO_DCE_MEM_INPUT(mem_input)\
  32         container_of(mem_input, struct dce_mem_input, base)
  33 
  34 #define MI_DCE_BASE_REG_LIST(id)\
  35         SRI(GRPH_ENABLE, DCP, id),\
  36         SRI(GRPH_CONTROL, DCP, id),\
  37         SRI(GRPH_X_START, DCP, id),\
  38         SRI(GRPH_Y_START, DCP, id),\
  39         SRI(GRPH_X_END, DCP, id),\
  40         SRI(GRPH_Y_END, DCP, id),\
  41         SRI(GRPH_PITCH, DCP, id),\
  42         SRI(HW_ROTATION, DCP, id),\
  43         SRI(GRPH_SWAP_CNTL, DCP, id),\
  44         SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
  45         SRI(GRPH_UPDATE, DCP, id),\
  46         SRI(GRPH_FLIP_CONTROL, DCP, id),\
  47         SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
  48         SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
  49         SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
  50         SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
  51         SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
  52         SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
  53         SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
  54         SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
  55         SRI(DMIF_BUFFER_CONTROL, PIPE, id)
  56 
  57 #define MI_DCE_PTE_REG_LIST(id)\
  58         SRI(DVMM_PTE_CONTROL, DCP, id),\
  59         SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
  60 
  61 #define MI_DCE8_REG_LIST(id)\
  62         MI_DCE_BASE_REG_LIST(id),\
  63         SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
  64 
  65 #define MI_DCE11_2_REG_LIST(id)\
  66         MI_DCE8_REG_LIST(id),\
  67         SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id)
  68 
  69 #define MI_DCE11_REG_LIST(id)\
  70         MI_DCE11_2_REG_LIST(id),\
  71         MI_DCE_PTE_REG_LIST(id)
  72 
  73 #define MI_DCE12_REG_LIST(id)\
  74         MI_DCE_BASE_REG_LIST(id),\
  75         MI_DCE_PTE_REG_LIST(id),\
  76         SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
  77         SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
  78         SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\
  79         SR(DCHUB_FB_LOCATION),\
  80         SR(DCHUB_AGP_BASE),\
  81         SR(DCHUB_AGP_BOT),\
  82         SR(DCHUB_AGP_TOP)
  83 
  84 struct dce_mem_input_registers {
  85         /* DCP */
  86         uint32_t GRPH_ENABLE;
  87         uint32_t GRPH_CONTROL;
  88         uint32_t GRPH_X_START;
  89         uint32_t GRPH_Y_START;
  90         uint32_t GRPH_X_END;
  91         uint32_t GRPH_Y_END;
  92         uint32_t GRPH_PITCH;
  93         uint32_t HW_ROTATION;
  94         uint32_t GRPH_SWAP_CNTL;
  95         uint32_t PRESCALE_GRPH_CONTROL;
  96         uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;
  97         uint32_t DVMM_PTE_CONTROL;
  98         uint32_t DVMM_PTE_ARB_CONTROL;
  99         uint32_t GRPH_UPDATE;
 100         uint32_t GRPH_FLIP_CONTROL;
 101         uint32_t GRPH_PRIMARY_SURFACE_ADDRESS;
 102         uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
 103         uint32_t GRPH_SECONDARY_SURFACE_ADDRESS;
 104         uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
 105         /* DMIF_PG */
 106         uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
 107         uint32_t DPG_WATERMARK_MASK_CONTROL;
 108         uint32_t DPG_PIPE_URGENCY_CONTROL;
 109         uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
 110         uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
 111         uint32_t DPG_PIPE_LOW_POWER_CONTROL;
 112         uint32_t DPG_PIPE_STUTTER_CONTROL;
 113         uint32_t DPG_PIPE_STUTTER_CONTROL2;
 114         /* DCI */
 115         uint32_t DMIF_BUFFER_CONTROL;
 116         /* MC_HUB */
 117         uint32_t MC_HUB_RDREQ_DMIF_LIMIT;
 118         /*DCHUB*/
 119         uint32_t DCHUB_FB_LOCATION;
 120         uint32_t DCHUB_AGP_BASE;
 121         uint32_t DCHUB_AGP_BOT;
 122         uint32_t DCHUB_AGP_TOP;
 123 };
 124 
 125 /* Set_Filed_for_Block */
 126 #define SFB(blk_name, reg_name, field_name, post_fix)\
 127         .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
 128 
 129 #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
 130         SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
 131         SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
 132         SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
 133         SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
 134         SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
 135         SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
 136         SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
 137         SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
 138         SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
 139 
 140 #define MI_DCP_MASK_SH_LIST(mask_sh, blk)\
 141         SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
 142         SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
 143         SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
 144         SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
 145         SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
 146         SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
 147         SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
 148         SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
 149         SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
 150         SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
 151         SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
 152         SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
 153         SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
 154         SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
 155         SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
 156         SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
 157         SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
 158         SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
 159         SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
 160         SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
 161         SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
 162         SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
 163         SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
 164 
 165 #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
 166         SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
 167 
 168 #define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
 169         SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\
 170         SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\
 171         SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
 172         SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
 173         SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
 174 
 175 #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
 176         SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
 177         SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
 178         SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
 179         SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
 180         SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
 181         SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
 182         SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
 183         SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
 184         SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
 185 
 186 #define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk)\
 187         SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
 188         SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
 189         SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
 190         SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
 191         SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
 192         SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
 193 
 194 #define MI_DCE8_MASK_SH_LIST(mask_sh)\
 195         MI_DCP_MASK_SH_LIST(mask_sh, ),\
 196         MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\
 197         MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\
 198         MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
 199 
 200 #define MI_DCE11_2_MASK_SH_LIST(mask_sh)\
 201         MI_DCE8_MASK_SH_LIST(mask_sh),\
 202         MI_DCP_DCE11_MASK_SH_LIST(mask_sh, )
 203 
 204 #define MI_DCE11_MASK_SH_LIST(mask_sh)\
 205         MI_DCE11_2_MASK_SH_LIST(mask_sh),\
 206         MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
 207 
 208 #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
 209         SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
 210         SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
 211         SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
 212         SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\
 213         SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
 214 
 215 #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
 216         SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
 217         SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\
 218         SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\
 219         SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\
 220         SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
 221         SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
 222         SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
 223         SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
 224         SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
 225         SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
 226         SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)
 227 
 228 #define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
 229         SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
 230         SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
 231         SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
 232         SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
 233         SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
 234 
 235 #define MI_DCE12_MASK_SH_LIST(mask_sh)\
 236         MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\
 237         SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
 238         MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\
 239         MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\
 240         MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
 241         MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
 242         MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\
 243         MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
 244 
 245 #define MI_REG_FIELD_LIST(type) \
 246         type GRPH_ENABLE; \
 247         type GRPH_X_START; \
 248         type GRPH_Y_START; \
 249         type GRPH_X_END; \
 250         type GRPH_Y_END; \
 251         type GRPH_PITCH; \
 252         type GRPH_ROTATION_ANGLE; \
 253         type GRPH_RED_CROSSBAR; \
 254         type GRPH_BLUE_CROSSBAR; \
 255         type GRPH_PRESCALE_SELECT; \
 256         type GRPH_PRESCALE_R_SIGN; \
 257         type GRPH_PRESCALE_G_SIGN; \
 258         type GRPH_PRESCALE_B_SIGN; \
 259         type GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; \
 260         type DVMM_PAGE_WIDTH; \
 261         type DVMM_PAGE_HEIGHT; \
 262         type DVMM_MIN_PTE_BEFORE_FLIP; \
 263         type DVMM_PTE_REQ_PER_CHUNK; \
 264         type DVMM_MAX_PTE_REQ_OUTSTANDING; \
 265         type GRPH_DEPTH; \
 266         type GRPH_FORMAT; \
 267         type GRPH_NUM_BANKS; \
 268         type GRPH_BANK_WIDTH;\
 269         type GRPH_BANK_HEIGHT;\
 270         type GRPH_MACRO_TILE_ASPECT;\
 271         type GRPH_TILE_SPLIT;\
 272         type GRPH_MICRO_TILE_MODE;\
 273         type GRPH_PIPE_CONFIG;\
 274         type GRPH_ARRAY_MODE;\
 275         type GRPH_COLOR_EXPANSION_MODE;\
 276         type GRPH_SW_MODE; \
 277         type GRPH_SE_ENABLE; \
 278         type GRPH_NUM_SHADER_ENGINES; \
 279         type GRPH_NUM_PIPES; \
 280         type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \
 281         type GRPH_SECONDARY_SURFACE_ADDRESS; \
 282         type GRPH_SECONDARY_DFQ_ENABLE; \
 283         type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \
 284         type GRPH_PRIMARY_SURFACE_ADDRESS; \
 285         type GRPH_SURFACE_UPDATE_PENDING; \
 286         type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \
 287         type GRPH_UPDATE_LOCK; \
 288         type PIXEL_DURATION; \
 289         type URGENCY_WATERMARK_MASK; \
 290         type PSTATE_CHANGE_WATERMARK_MASK; \
 291         type NB_PSTATE_CHANGE_WATERMARK_MASK; \
 292         type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \
 293         type URGENCY_LOW_WATERMARK; \
 294         type URGENCY_HIGH_WATERMARK; \
 295         type URGENT_LEVEL_LOW_WATERMARK;\
 296         type URGENT_LEVEL_HIGH_WATERMARK;\
 297         type NB_PSTATE_CHANGE_ENABLE; \
 298         type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \
 299         type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
 300         type NB_PSTATE_CHANGE_WATERMARK; \
 301         type PSTATE_CHANGE_ENABLE; \
 302         type PSTATE_CHANGE_URGENT_DURING_REQUEST; \
 303         type PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
 304         type PSTATE_CHANGE_WATERMARK; \
 305         type STUTTER_ENABLE; \
 306         type STUTTER_IGNORE_FBC; \
 307         type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \
 308         type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \
 309         type DMIF_BUFFERS_ALLOCATED; \
 310         type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
 311         type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
 312         type FB_BASE; \
 313         type FB_TOP; \
 314         type AGP_BASE; \
 315         type AGP_TOP; \
 316         type AGP_BOT; \
 317 
 318 struct dce_mem_input_shift {
 319         MI_REG_FIELD_LIST(uint8_t)
 320 };
 321 
 322 struct dce_mem_input_mask {
 323         MI_REG_FIELD_LIST(uint32_t)
 324 };
 325 
 326 struct dce_mem_input_wa {
 327         uint8_t single_head_rdreq_dmif_limit;
 328 };
 329 
 330 struct dce_mem_input {
 331         struct mem_input base;
 332 
 333         const struct dce_mem_input_registers *regs;
 334         const struct dce_mem_input_shift *shifts;
 335         const struct dce_mem_input_mask *masks;
 336 
 337         struct dce_mem_input_wa wa;
 338 };
 339 
 340 void dce_mem_input_construct(
 341         struct dce_mem_input *dce_mi,
 342         struct dc_context *ctx,
 343         int inst,
 344         const struct dce_mem_input_registers *regs,
 345         const struct dce_mem_input_shift *mi_shift,
 346         const struct dce_mem_input_mask *mi_mask);
 347 
 348 void dce112_mem_input_construct(
 349         struct dce_mem_input *dce_mi,
 350         struct dc_context *ctx,
 351         int inst,
 352         const struct dce_mem_input_registers *regs,
 353         const struct dce_mem_input_shift *mi_shift,
 354         const struct dce_mem_input_mask *mi_mask);
 355 
 356 void dce120_mem_input_construct(
 357         struct dce_mem_input *dce_mi,
 358         struct dc_context *ctx,
 359         int inst,
 360         const struct dce_mem_input_registers *regs,
 361         const struct dce_mem_input_shift *mi_shift,
 362         const struct dce_mem_input_mask *mi_mask);
 363 
 364 #endif /*__DCE_MEM_INPUT_H__*/
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

INCLUDED FROM
