drivers/gpu/drm/amd/display/dc/dce/dce_i2c

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   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 #ifndef __DCE_I2C_HW_H__
  27 #define __DCE_I2C_HW_H__
  28 
  29 enum dc_i2c_status {
  30         DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
  31         DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
  32         DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW,
  33         DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY = 2,
  34 };
  35 
  36 enum dc_i2c_arbitration {
  37         DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
  38         DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
  39 };
  40 
  41 enum i2c_channel_operation_result {
  42         I2C_CHANNEL_OPERATION_SUCCEEDED,
  43         I2C_CHANNEL_OPERATION_FAILED,
  44         I2C_CHANNEL_OPERATION_NOT_GRANTED,
  45         I2C_CHANNEL_OPERATION_IS_BUSY,
  46         I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED,
  47         I2C_CHANNEL_OPERATION_CHANNEL_IN_USE,
  48         I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED,
  49         I2C_CHANNEL_OPERATION_ENGINE_BUSY,
  50         I2C_CHANNEL_OPERATION_TIMEOUT,
  51         I2C_CHANNEL_OPERATION_NO_RESPONSE,
  52         I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS,
  53         I2C_CHANNEL_OPERATION_WRONG_PARAMETER,
  54         I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES,
  55         I2C_CHANNEL_OPERATION_NOT_STARTED
  56 };
  57 
  58 
  59 enum dce_i2c_transaction_action {
  60         DCE_I2C_TRANSACTION_ACTION_I2C_WRITE = 0x00,
  61         DCE_I2C_TRANSACTION_ACTION_I2C_READ = 0x10,
  62         DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
  63 
  64         DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
  65         DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
  66         DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
  67 
  68         DCE_I2C_TRANSACTION_ACTION_DP_WRITE = 0x80,
  69         DCE_I2C_TRANSACTION_ACTION_DP_READ = 0x90
  70 };
  71 
  72 enum {
  73         I2C_SETUP_TIME_LIMIT_DCE = 255,
  74         I2C_SETUP_TIME_LIMIT_DCN = 3,
  75         I2C_HW_BUFFER_SIZE_DCE100 = 538,
  76         I2C_HW_BUFFER_SIZE_DCE = 144,
  77         I2C_SEND_RESET_LENGTH_9 = 9,
  78         I2C_SEND_RESET_LENGTH_10 = 10,
  79         DEFAULT_I2C_HW_SPEED = 50,
  80         DEFAULT_I2C_HW_SPEED_100KHZ = 100,
  81         TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32,
  82 };
  83 
  84 #define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
  85         SRI(SETUP, DC_I2C_DDC, id),\
  86         SRI(SPEED, DC_I2C_DDC, id),\
  87         SRI(HW_STATUS, DC_I2C_DDC, id),\
  88         SR(DC_I2C_ARBITRATION),\
  89         SR(DC_I2C_CONTROL),\
  90         SR(DC_I2C_SW_STATUS),\
  91         SR(DC_I2C_TRANSACTION0),\
  92         SR(DC_I2C_TRANSACTION1),\
  93         SR(DC_I2C_TRANSACTION2),\
  94         SR(DC_I2C_TRANSACTION3),\
  95         SR(DC_I2C_DATA),\
  96         SR(MICROSECOND_TIME_BASE_DIV)
  97 
  98 #define I2C_SF(reg_name, field_name, post_fix)\
  99         .field_name = reg_name ## __ ## field_name ## post_fix
 100 
 101 #define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
 102         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
 103         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\
 104         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\
 105         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\
 106         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
 107         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
 108         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
 109         I2C_SF(DC_I2C_DDC1_HW_STATUS, DC_I2C_DDC1_HW_STATUS, mask_sh),\
 110         I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, mask_sh),\
 111         I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
 112         I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
 113         I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\
 114         I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
 115         I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
 116         I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
 117         I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
 118         I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
 119         I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
 120         I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\
 121         I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\
 122         I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\
 123         I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\
 124         I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\
 125         I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\
 126         I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\
 127         I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\
 128         I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\
 129         I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\
 130         I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\
 131         I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\
 132         I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\
 133         I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
 134         I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
 135         I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
 136         I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
 137         I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh)
 138 
 139 #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
 140         I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
 141         I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh)
 142 
 143 struct dce_i2c_shift {
 144         uint8_t DC_I2C_DDC1_ENABLE;
 145         uint8_t DC_I2C_DDC1_TIME_LIMIT;
 146         uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;
 147         uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;
 148         uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
 149         uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
 150         uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
 151         uint8_t DC_I2C_DDC1_HW_STATUS;
 152         uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
 153         uint8_t DC_I2C_SW_USE_I2C_REG_REQ;
 154         uint8_t DC_I2C_NO_QUEUED_SW_GO;
 155         uint8_t DC_I2C_SW_PRIORITY;
 156         uint8_t DC_I2C_SOFT_RESET;
 157         uint8_t DC_I2C_SW_STATUS_RESET;
 158         uint8_t DC_I2C_GO;
 159         uint8_t DC_I2C_SEND_RESET;
 160         uint8_t DC_I2C_TRANSACTION_COUNT;
 161         uint8_t DC_I2C_DDC_SELECT;
 162         uint8_t DC_I2C_DDC1_PRESCALE;
 163         uint8_t DC_I2C_DDC1_THRESHOLD;
 164         uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
 165         uint8_t DC_I2C_SW_STOPPED_ON_NACK;
 166         uint8_t DC_I2C_SW_TIMEOUT;
 167         uint8_t DC_I2C_SW_ABORTED;
 168         uint8_t DC_I2C_SW_DONE;
 169         uint8_t DC_I2C_SW_STATUS;
 170         uint8_t DC_I2C_STOP_ON_NACK0;
 171         uint8_t DC_I2C_START0;
 172         uint8_t DC_I2C_RW0;
 173         uint8_t DC_I2C_STOP0;
 174         uint8_t DC_I2C_COUNT0;
 175         uint8_t DC_I2C_DATA_RW;
 176         uint8_t DC_I2C_DATA;
 177         uint8_t DC_I2C_INDEX;
 178         uint8_t DC_I2C_INDEX_WRITE;
 179         uint8_t XTAL_REF_DIV;
 180 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 181         uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
 182 #endif
 183         uint8_t DC_I2C_REG_RW_CNTL_STATUS;
 184 };
 185 
 186 struct dce_i2c_mask {
 187         uint32_t DC_I2C_DDC1_ENABLE;
 188         uint32_t DC_I2C_DDC1_TIME_LIMIT;
 189         uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
 190         uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
 191         uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
 192         uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
 193         uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
 194         uint32_t DC_I2C_DDC1_HW_STATUS;
 195         uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
 196         uint32_t DC_I2C_SW_USE_I2C_REG_REQ;
 197         uint32_t DC_I2C_NO_QUEUED_SW_GO;
 198         uint32_t DC_I2C_SW_PRIORITY;
 199         uint32_t DC_I2C_SOFT_RESET;
 200         uint32_t DC_I2C_SW_STATUS_RESET;
 201         uint32_t DC_I2C_GO;
 202         uint32_t DC_I2C_SEND_RESET;
 203         uint32_t DC_I2C_TRANSACTION_COUNT;
 204         uint32_t DC_I2C_DDC_SELECT;
 205         uint32_t DC_I2C_DDC1_PRESCALE;
 206         uint32_t DC_I2C_DDC1_THRESHOLD;
 207         uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
 208         uint32_t DC_I2C_SW_STOPPED_ON_NACK;
 209         uint32_t DC_I2C_SW_TIMEOUT;
 210         uint32_t DC_I2C_SW_ABORTED;
 211         uint32_t DC_I2C_SW_DONE;
 212         uint32_t DC_I2C_SW_STATUS;
 213         uint32_t DC_I2C_STOP_ON_NACK0;
 214         uint32_t DC_I2C_START0;
 215         uint32_t DC_I2C_RW0;
 216         uint32_t DC_I2C_STOP0;
 217         uint32_t DC_I2C_COUNT0;
 218         uint32_t DC_I2C_DATA_RW;
 219         uint32_t DC_I2C_DATA;
 220         uint32_t DC_I2C_INDEX;
 221         uint32_t DC_I2C_INDEX_WRITE;
 222         uint32_t XTAL_REF_DIV;
 223 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 224         uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
 225 #endif
 226         uint32_t DC_I2C_REG_RW_CNTL_STATUS;
 227 };
 228 
 229 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 230 #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
 231         I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
 232         I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
 233 #endif
 234 
 235 struct dce_i2c_registers {
 236         uint32_t SETUP;
 237         uint32_t SPEED;
 238         uint32_t HW_STATUS;
 239         uint32_t DC_I2C_ARBITRATION;
 240         uint32_t DC_I2C_CONTROL;
 241         uint32_t DC_I2C_SW_STATUS;
 242         uint32_t DC_I2C_TRANSACTION0;
 243         uint32_t DC_I2C_TRANSACTION1;
 244         uint32_t DC_I2C_TRANSACTION2;
 245         uint32_t DC_I2C_TRANSACTION3;
 246         uint32_t DC_I2C_DATA;
 247         uint32_t MICROSECOND_TIME_BASE_DIV;
 248 };
 249 
 250 enum dce_i2c_transaction_address_space {
 251         DCE_I2C_TRANSACTION_ADDRESS_SPACE_I2C = 1,
 252         DCE_I2C_TRANSACTION_ADDRESS_SPACE_DPCD
 253 };
 254 
 255 struct i2c_request_transaction_data {
 256         enum dce_i2c_transaction_action action;
 257         enum i2c_channel_operation_result status;
 258         uint8_t address;
 259         uint32_t length;
 260         uint8_t *data;
 261 };
 262 
 263 struct dce_i2c_hw {
 264         struct ddc *ddc;
 265         uint32_t original_speed;
 266         uint32_t engine_keep_power_up_count;
 267         uint32_t transaction_count;
 268         uint32_t buffer_used_bytes;
 269         uint32_t buffer_used_write;
 270         uint32_t reference_frequency;
 271         uint32_t default_speed;
 272         uint32_t engine_id;
 273         uint32_t setup_limit;
 274         uint32_t send_reset_length;
 275         uint32_t buffer_size;
 276         struct dc_context *ctx;
 277 
 278         const struct dce_i2c_registers *regs;
 279         const struct dce_i2c_shift *shifts;
 280         const struct dce_i2c_mask *masks;
 281 };
 282 
 283 void dce_i2c_hw_construct(
 284         struct dce_i2c_hw *dce_i2c_hw,
 285         struct dc_context *ctx,
 286         uint32_t engine_id,
 287         const struct dce_i2c_registers *regs,
 288         const struct dce_i2c_shift *shifts,
 289         const struct dce_i2c_mask *masks);
 290 
 291 void dce100_i2c_hw_construct(
 292         struct dce_i2c_hw *dce_i2c_hw,
 293         struct dc_context *ctx,
 294         uint32_t engine_id,
 295         const struct dce_i2c_registers *regs,
 296         const struct dce_i2c_shift *shifts,
 297         const struct dce_i2c_mask *masks);
 298 
 299 void dce112_i2c_hw_construct(
 300         struct dce_i2c_hw *dce_i2c_hw,
 301         struct dc_context *ctx,
 302         uint32_t engine_id,
 303         const struct dce_i2c_registers *regs,
 304         const struct dce_i2c_shift *shifts,
 305         const struct dce_i2c_mask *masks);
 306 
 307 void dcn1_i2c_hw_construct(
 308         struct dce_i2c_hw *dce_i2c_hw,
 309         struct dc_context *ctx,
 310         uint32_t engine_id,
 311         const struct dce_i2c_registers *regs,
 312         const struct dce_i2c_shift *shifts,
 313         const struct dce_i2c_mask *masks);
 314 
 315 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 316 void dcn2_i2c_hw_construct(
 317         struct dce_i2c_hw *dce_i2c_hw,
 318         struct dc_context *ctx,
 319         uint32_t engine_id,
 320         const struct dce_i2c_registers *regs,
 321         const struct dce_i2c_shift *shifts,
 322         const struct dce_i2c_mask *masks);
 323 #endif
 324 
 325 bool dce_i2c_submit_command_hw(
 326         struct resource_pool *pool,
 327         struct ddc *ddc,
 328         struct i2c_command *cmd,
 329         struct dce_i2c_hw *dce_i2c_hw);
 330 
 331 struct dce_i2c_hw *acquire_i2c_hw_engine(
 332         struct resource_pool *pool,
 333         struct ddc *ddc);
 334 
 335 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

INCLUDED FROM
