drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu

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This source file includes following definitions.
dm_vblank_get_counter
dm_crtc_get_scanoutpos
dm_is_idle
dm_wait_for_idle
dm_check_soft_reset
dm_soft_reset
get_crtc_by_otg_inst
amdgpu_dm_vrr_active
dm_pflip_high_irq
dm_vupdate_high_irq
dm_crtc_high_irq
dm_set_clockgating_state
dm_set_powergating_state
amdgpu_dm_fbc_init
amdgpu_dm_audio_component_get_eld
amdgpu_dm_audio_component_bind
amdgpu_dm_audio_component_unbind
amdgpu_dm_audio_init
amdgpu_dm_audio_fini
amdgpu_dm_audio_eld_notify
amdgpu_dm_init
amdgpu_dm_fini
load_dmcu_fw
dm_sw_init
dm_sw_fini
detect_mst_link_for_all_connectors
dm_late_init
s3_handle_mst
dm_hw_init
dm_hw_fini
dm_suspend
amdgpu_dm_find_first_crtc_matching_connector
emulated_link_detect
dm_resume
amdgpu_dm_update_connector_after_detect
handle_hpd_irq
dm_handle_hpd_rx_irq
handle_hpd_rx_irq
register_hpd_handlers
dce110_register_irq_handlers
dcn10_register_irq_handlers
dm_atomic_get_state
dm_atomic_get_new_state
dm_atomic_get_old_state
dm_atomic_duplicate_state
dm_atomic_destroy_state
amdgpu_dm_mode_config_init
amdgpu_dm_update_backlight_caps
amdgpu_dm_backlight_update_status
amdgpu_dm_backlight_get_brightness
amdgpu_dm_register_backlight_device
initialize_plane
register_backlight_device
amdgpu_dm_initialize_drm_device
amdgpu_dm_destroy_drm_device
dm_bandwidth_update
s3_debug_store
dm_early_init
modeset_required
modereset_required
amdgpu_dm_encoder_destroy
fill_dc_scaling_info
get_fb_info
get_dcc_address
fill_plane_dcc_attributes
fill_plane_buffer_attributes
fill_blending_from_plane_state
fill_plane_color_attributes
fill_dc_plane_info_and_addr
fill_dc_plane_attributes
update_stream_scaling_settings
convert_color_depth_from_display_info
get_aspect_ratio
get_output_color_space
adjust_colour_depth_from_display_info
fill_stream_properties_from_drm_display_mode
fill_audio_info
copy_crtc_timing_for_drm_display_mode
decide_crtc_timing_for_drm_display_mode
create_fake_sink
set_multisync_trigger_params
set_master_stream
dm_enable_per_frame_crtc_master_sync
create_stream_for_sink
amdgpu_dm_crtc_destroy
dm_crtc_destroy_state
dm_crtc_reset_state
dm_crtc_duplicate_state
dm_set_vupdate_irq
dm_set_vblank
dm_enable_vblank
dm_disable_vblank
amdgpu_dm_connector_detect
amdgpu_dm_connector_atomic_set_property
amdgpu_dm_connector_atomic_get_property
amdgpu_dm_connector_unregister
amdgpu_dm_connector_destroy
amdgpu_dm_connector_funcs_reset
amdgpu_dm_connector_atomic_duplicate_state
get_modes
create_eml_sink
handle_edid_mgmt
amdgpu_dm_connector_mode_valid
fill_hdr_info_packet
is_hdr_metadata_different
amdgpu_dm_connector_atomic_check
dm_crtc_helper_disable
does_crtc_have_active_cursor
count_crtc_active_planes
dm_update_crtc_interrupt_state
dm_crtc_helper_atomic_check
dm_crtc_helper_mode_fixup
dm_encoder_helper_disable
dm_encoder_helper_atomic_check
dm_drm_plane_reset
dm_drm_plane_duplicate_state
dm_drm_plane_destroy_state
dm_plane_helper_prepare_fb
dm_plane_helper_cleanup_fb
dm_plane_atomic_check
dm_plane_atomic_async_check
dm_plane_atomic_async_update
get_plane_formats
amdgpu_dm_plane_init
amdgpu_dm_crtc_init
to_drm_connector_type
amdgpu_dm_connector_to_encoder
amdgpu_dm_get_native_mode
amdgpu_dm_create_common_mode
amdgpu_dm_connector_add_common_modes
amdgpu_dm_connector_ddc_get_modes
amdgpu_dm_connector_get_modes
amdgpu_dm_connector_init_helper
amdgpu_dm_i2c_xfer
amdgpu_dm_i2c_func
create_i2c
amdgpu_dm_connector_init
amdgpu_dm_get_encoder_crtc_mask
amdgpu_dm_encoder_init
manage_dm_interrupts
is_scaling_state_different
remove_stream
get_cursor_position
handle_cursor_update
prepare_flip_isr
update_freesync_state_on_stream
pre_update_freesync_state_on_stream
amdgpu_dm_handle_vrr_transition
amdgpu_dm_commit_cursors
amdgpu_dm_commit_planes
amdgpu_dm_commit_audio
amdgpu_dm_enable_crtc_interrupts
amdgpu_dm_crtc_copy_transient_flags
amdgpu_dm_atomic_commit
amdgpu_dm_atomic_commit_tail
dm_force_atomic_commit
dm_restore_drm_connector_state
do_aquire_global_lock
get_freesync_config_for_crtc
reset_freesync_config_for_crtc
dm_update_crtc_state
should_reset_plane
dm_update_plane_state
dm_determine_update_type_for_commit
amdgpu_dm_atomic_check
is_dp_capable_without_timing_msa
amdgpu_dm_update_freesync_caps
   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28 
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc/inc/core_types.h"
  32 #include "dal_asic_id.h"
  33 
  34 #include "vid.h"
  35 #include "amdgpu.h"
  36 #include "amdgpu_display.h"
  37 #include "amdgpu_ucode.h"
  38 #include "atom.h"
  39 #include "amdgpu_dm.h"
  40 #include "amdgpu_pm.h"
  41 
  42 #include "amd_shared.h"
  43 #include "amdgpu_dm_irq.h"
  44 #include "dm_helpers.h"
  45 #include "amdgpu_dm_mst_types.h"
  46 #if defined(CONFIG_DEBUG_FS)
  47 #include "amdgpu_dm_debugfs.h"
  48 #endif
  49 
  50 #include "ivsrcid/ivsrcid_vislands30.h"
  51 
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/version.h>
  55 #include <linux/types.h>
  56 #include <linux/pm_runtime.h>
  57 #include <linux/pci.h>
  58 #include <linux/firmware.h>
  59 #include <linux/component.h>
  60 
  61 #include <drm/drm_atomic.h>
  62 #include <drm/drm_atomic_uapi.h>
  63 #include <drm/drm_atomic_helper.h>
  64 #include <drm/drm_dp_mst_helper.h>
  65 #include <drm/drm_fb_helper.h>
  66 #include <drm/drm_fourcc.h>
  67 #include <drm/drm_edid.h>
  68 #include <drm/drm_vblank.h>
  69 #include <drm/drm_audio_component.h>
  70 
  71 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  72 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  73 
  74 #include "dcn/dcn_1_0_offset.h"
  75 #include "dcn/dcn_1_0_sh_mask.h"
  76 #include "soc15_hw_ip.h"
  77 #include "vega10_ip_offset.h"
  78 
  79 #include "soc15_common.h"
  80 #endif
  81 
  82 #include "modules/inc/mod_freesync.h"
  83 #include "modules/power/power_helpers.h"
  84 #include "modules/inc/mod_info_packet.h"
  85 
  86 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
  87 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
  88 
  89 /**
  90  * DOC: overview
  91  *
  92  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
  93  * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
  94  * requests into DC requests, and DC responses into DRM responses.
  95  *
  96  * The root control structure is &struct amdgpu_display_manager.
  97  */
  98 
  99 /* basic init/fini API */
 100 static int amdgpu_dm_init(struct amdgpu_device *adev);
 101 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 102 
 103 /*
 104  * initializes drm_device display related structures, based on the information
 105  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 106  * drm_encoder, drm_mode_config
 107  *
 108  * Returns 0 on success
 109  */
 110 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 111 /* removes and deallocates the drm structures, created by the above function */
 112 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 113 
 114 static void
 115 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
 116 
 117 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 118                                 struct drm_plane *plane,
 119                                 unsigned long possible_crtcs,
 120                                 const struct dc_plane_cap *plane_cap);
 121 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 122                                struct drm_plane *plane,
 123                                uint32_t link_index);
 124 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 125                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 126                                     uint32_t link_index,
 127                                     struct amdgpu_encoder *amdgpu_encoder);
 128 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 129                                   struct amdgpu_encoder *aencoder,
 130                                   uint32_t link_index);
 131 
 132 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 133 
 134 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 135                                    struct drm_atomic_state *state,
 136                                    bool nonblock);
 137 
 138 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 139 
 140 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 141                                   struct drm_atomic_state *state);
 142 
 143 static void handle_cursor_update(struct drm_plane *plane,
 144                                  struct drm_plane_state *old_plane_state);
 145 
 146 /*
 147  * dm_vblank_get_counter
 148  *
 149  * @brief
 150  * Get counter for number of vertical blanks
 151  *
 152  * @param
 153  * struct amdgpu_device *adev - [in] desired amdgpu device
 154  * int disp_idx - [in] which CRTC to get the counter from
 155  *
 156  * @return
 157  * Counter for vertical blanks
 158  */
 159 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 160 {
 161         if (crtc >= adev->mode_info.num_crtc)
 162                 return 0;
 163         else {
 164                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 165                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 166                                 acrtc->base.state);
 167 
 168 
 169                 if (acrtc_state->stream == NULL) {
 170                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 171                                   crtc);
 172                         return 0;
 173                 }
 174 
 175                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 176         }
 177 }
 178 
 179 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 180                                   u32 *vbl, u32 *position)
 181 {
 182         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 183 
 184         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 185                 return -EINVAL;
 186         else {
 187                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 188                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 189                                                 acrtc->base.state);
 190 
 191                 if (acrtc_state->stream ==  NULL) {
 192                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 193                                   crtc);
 194                         return 0;
 195                 }
 196 
 197                 /*
 198                  * TODO rework base driver to use values directly.
 199                  * for now parse it back into reg-format
 200                  */
 201                 dc_stream_get_scanoutpos(acrtc_state->stream,
 202                                          &v_blank_start,
 203                                          &v_blank_end,
 204                                          &h_position,
 205                                          &v_position);
 206 
 207                 *position = v_position | (h_position << 16);
 208                 *vbl = v_blank_start | (v_blank_end << 16);
 209         }
 210 
 211         return 0;
 212 }
 213 
 214 static bool dm_is_idle(void *handle)
 215 {
 216         /* XXX todo */
 217         return true;
 218 }
 219 
 220 static int dm_wait_for_idle(void *handle)
 221 {
 222         /* XXX todo */
 223         return 0;
 224 }
 225 
 226 static bool dm_check_soft_reset(void *handle)
 227 {
 228         return false;
 229 }
 230 
 231 static int dm_soft_reset(void *handle)
 232 {
 233         /* XXX todo */
 234         return 0;
 235 }
 236 
 237 static struct amdgpu_crtc *
 238 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 239                      int otg_inst)
 240 {
 241         struct drm_device *dev = adev->ddev;
 242         struct drm_crtc *crtc;
 243         struct amdgpu_crtc *amdgpu_crtc;
 244 
 245         if (otg_inst == -1) {
 246                 WARN_ON(1);
 247                 return adev->mode_info.crtcs[0];
 248         }
 249 
 250         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 251                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 252 
 253                 if (amdgpu_crtc->otg_inst == otg_inst)
 254                         return amdgpu_crtc;
 255         }
 256 
 257         return NULL;
 258 }
 259 
 260 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
 261 {
 262         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
 263                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 264 }
 265 
 266 static void dm_pflip_high_irq(void *interrupt_params)
 267 {
 268         struct amdgpu_crtc *amdgpu_crtc;
 269         struct common_irq_params *irq_params = interrupt_params;
 270         struct amdgpu_device *adev = irq_params->adev;
 271         unsigned long flags;
 272         struct drm_pending_vblank_event *e;
 273         struct dm_crtc_state *acrtc_state;
 274         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 275         bool vrr_active;
 276 
 277         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 278 
 279         /* IRQ could occur when in initial stage */
 280         /* TODO work and BO cleanup */
 281         if (amdgpu_crtc == NULL) {
 282                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 283                 return;
 284         }
 285 
 286         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 287 
 288         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 289                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 290                                                  amdgpu_crtc->pflip_status,
 291                                                  AMDGPU_FLIP_SUBMITTED,
 292                                                  amdgpu_crtc->crtc_id,
 293                                                  amdgpu_crtc);
 294                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 295                 return;
 296         }
 297 
 298         /* page flip completed. */
 299         e = amdgpu_crtc->event;
 300         amdgpu_crtc->event = NULL;
 301 
 302         if (!e)
 303                 WARN_ON(1);
 304 
 305         acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
 306         vrr_active = amdgpu_dm_vrr_active(acrtc_state);
 307 
 308         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 309         if (!vrr_active ||
 310             !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
 311                                       &v_blank_end, &hpos, &vpos) ||
 312             (vpos < v_blank_start)) {
 313                 /* Update to correct count and vblank timestamp if racing with
 314                  * vblank irq. This also updates to the correct vblank timestamp
 315                  * even in VRR mode, as scanout is past the front-porch atm.
 316                  */
 317                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 318 
 319                 /* Wake up userspace by sending the pageflip event with proper
 320                  * count and timestamp of vblank of flip completion.
 321                  */
 322                 if (e) {
 323                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 324 
 325                         /* Event sent, so done with vblank for this flip */
 326                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 327                 }
 328         } else if (e) {
 329                 /* VRR active and inside front-porch: vblank count and
 330                  * timestamp for pageflip event will only be up to date after
 331                  * drm_crtc_handle_vblank() has been executed from late vblank
 332                  * irq handler after start of back-porch (vline 0). We queue the
 333                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 334                  * updated timestamp and count, once it runs after us.
 335                  *
 336                  * We need to open-code this instead of using the helper
 337                  * drm_crtc_arm_vblank_event(), as that helper would
 338                  * call drm_crtc_accurate_vblank_count(), which we must
 339                  * not call in VRR mode while we are in front-porch!
 340                  */
 341 
 342                 /* sequence will be replaced by real count during send-out. */
 343                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 344                 e->pipe = amdgpu_crtc->crtc_id;
 345 
 346                 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
 347                 e = NULL;
 348         }
 349 
 350         /* Keep track of vblank of this flip for flip throttling. We use the
 351          * cooked hw counter, as that one incremented at start of this vblank
 352          * of pageflip completion, so last_flip_vblank is the forbidden count
 353          * for queueing new pageflips if vsync + VRR is enabled.
 354          */
 355         amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
 356                                                         amdgpu_crtc->crtc_id);
 357 
 358         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 359         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 360 
 361         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 362                          amdgpu_crtc->crtc_id, amdgpu_crtc,
 363                          vrr_active, (int) !e);
 364 }
 365 
 366 static void dm_vupdate_high_irq(void *interrupt_params)
 367 {
 368         struct common_irq_params *irq_params = interrupt_params;
 369         struct amdgpu_device *adev = irq_params->adev;
 370         struct amdgpu_crtc *acrtc;
 371         struct dm_crtc_state *acrtc_state;
 372         unsigned long flags;
 373 
 374         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 375 
 376         if (acrtc) {
 377                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 378 
 379                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 380                                  amdgpu_dm_vrr_active(acrtc_state));
 381 
 382                 /* Core vblank handling is done here after end of front-porch in
 383                  * vrr mode, as vblank timestamping will give valid results
 384                  * while now done after front-porch. This will also deliver
 385                  * page-flip completion events that have been queued to us
 386                  * if a pageflip happened inside front-porch.
 387                  */
 388                 if (amdgpu_dm_vrr_active(acrtc_state)) {
 389                         drm_crtc_handle_vblank(&acrtc->base);
 390 
 391                         /* BTR processing for pre-DCE12 ASICs */
 392                         if (acrtc_state->stream &&
 393                             adev->family < AMDGPU_FAMILY_AI) {
 394                                 spin_lock_irqsave(&adev->ddev->event_lock, flags);
 395                                 mod_freesync_handle_v_update(
 396                                     adev->dm.freesync_module,
 397                                     acrtc_state->stream,
 398                                     &acrtc_state->vrr_params);
 399 
 400                                 dc_stream_adjust_vmin_vmax(
 401                                     adev->dm.dc,
 402                                     acrtc_state->stream,
 403                                     &acrtc_state->vrr_params.adjust);
 404                                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 405                         }
 406                 }
 407         }
 408 }
 409 
 410 static void dm_crtc_high_irq(void *interrupt_params)
 411 {
 412         struct common_irq_params *irq_params = interrupt_params;
 413         struct amdgpu_device *adev = irq_params->adev;
 414         struct amdgpu_crtc *acrtc;
 415         struct dm_crtc_state *acrtc_state;
 416         unsigned long flags;
 417 
 418         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 419 
 420         if (acrtc) {
 421                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 422 
 423                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 424                                  amdgpu_dm_vrr_active(acrtc_state));
 425 
 426                 /* Core vblank handling at start of front-porch is only possible
 427                  * in non-vrr mode, as only there vblank timestamping will give
 428                  * valid results while done in front-porch. Otherwise defer it
 429                  * to dm_vupdate_high_irq after end of front-porch.
 430                  */
 431                 if (!amdgpu_dm_vrr_active(acrtc_state))
 432                         drm_crtc_handle_vblank(&acrtc->base);
 433 
 434                 /* Following stuff must happen at start of vblank, for crc
 435                  * computation and below-the-range btr support in vrr mode.
 436                  */
 437                 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 438 
 439                 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
 440                     acrtc_state->vrr_params.supported &&
 441                     acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
 442                         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 443                         mod_freesync_handle_v_update(
 444                                 adev->dm.freesync_module,
 445                                 acrtc_state->stream,
 446                                 &acrtc_state->vrr_params);
 447 
 448                         dc_stream_adjust_vmin_vmax(
 449                                 adev->dm.dc,
 450                                 acrtc_state->stream,
 451                                 &acrtc_state->vrr_params.adjust);
 452                         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 453                 }
 454         }
 455 }
 456 
 457 static int dm_set_clockgating_state(void *handle,
 458                   enum amd_clockgating_state state)
 459 {
 460         return 0;
 461 }
 462 
 463 static int dm_set_powergating_state(void *handle,
 464                   enum amd_powergating_state state)
 465 {
 466         return 0;
 467 }
 468 
 469 /* Prototypes of private functions */
 470 static int dm_early_init(void* handle);
 471 
 472 /* Allocate memory for FBC compressed data  */
 473 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 474 {
 475         struct drm_device *dev = connector->dev;
 476         struct amdgpu_device *adev = dev->dev_private;
 477         struct dm_comressor_info *compressor = &adev->dm.compressor;
 478         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 479         struct drm_display_mode *mode;
 480         unsigned long max_size = 0;
 481 
 482         if (adev->dm.dc->fbc_compressor == NULL)
 483                 return;
 484 
 485         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 486                 return;
 487 
 488         if (compressor->bo_ptr)
 489                 return;
 490 
 491 
 492         list_for_each_entry(mode, &connector->modes, head) {
 493                 if (max_size < mode->htotal * mode->vtotal)
 494                         max_size = mode->htotal * mode->vtotal;
 495         }
 496 
 497         if (max_size) {
 498                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 499                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 500                             &compressor->gpu_addr, &compressor->cpu_addr);
 501 
 502                 if (r)
 503                         DRM_ERROR("DM: Failed to initialize FBC\n");
 504                 else {
 505                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 506                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 507                 }
 508 
 509         }
 510 
 511 }
 512 
 513 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 514                                           int pipe, bool *enabled,
 515                                           unsigned char *buf, int max_bytes)
 516 {
 517         struct drm_device *dev = dev_get_drvdata(kdev);
 518         struct amdgpu_device *adev = dev->dev_private;
 519         struct drm_connector *connector;
 520         struct drm_connector_list_iter conn_iter;
 521         struct amdgpu_dm_connector *aconnector;
 522         int ret = 0;
 523 
 524         *enabled = false;
 525 
 526         mutex_lock(&adev->dm.audio_lock);
 527 
 528         drm_connector_list_iter_begin(dev, &conn_iter);
 529         drm_for_each_connector_iter(connector, &conn_iter) {
 530                 aconnector = to_amdgpu_dm_connector(connector);
 531                 if (aconnector->audio_inst != port)
 532                         continue;
 533 
 534                 *enabled = true;
 535                 ret = drm_eld_size(connector->eld);
 536                 memcpy(buf, connector->eld, min(max_bytes, ret));
 537 
 538                 break;
 539         }
 540         drm_connector_list_iter_end(&conn_iter);
 541 
 542         mutex_unlock(&adev->dm.audio_lock);
 543 
 544         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 545 
 546         return ret;
 547 }
 548 
 549 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 550         .get_eld = amdgpu_dm_audio_component_get_eld,
 551 };
 552 
 553 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 554                                        struct device *hda_kdev, void *data)
 555 {
 556         struct drm_device *dev = dev_get_drvdata(kdev);
 557         struct amdgpu_device *adev = dev->dev_private;
 558         struct drm_audio_component *acomp = data;
 559 
 560         acomp->ops = &amdgpu_dm_audio_component_ops;
 561         acomp->dev = kdev;
 562         adev->dm.audio_component = acomp;
 563 
 564         return 0;
 565 }
 566 
 567 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 568                                           struct device *hda_kdev, void *data)
 569 {
 570         struct drm_device *dev = dev_get_drvdata(kdev);
 571         struct amdgpu_device *adev = dev->dev_private;
 572         struct drm_audio_component *acomp = data;
 573 
 574         acomp->ops = NULL;
 575         acomp->dev = NULL;
 576         adev->dm.audio_component = NULL;
 577 }
 578 
 579 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 580         .bind   = amdgpu_dm_audio_component_bind,
 581         .unbind = amdgpu_dm_audio_component_unbind,
 582 };
 583 
 584 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 585 {
 586         int i, ret;
 587 
 588         if (!amdgpu_audio)
 589                 return 0;
 590 
 591         adev->mode_info.audio.enabled = true;
 592 
 593         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 594 
 595         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 596                 adev->mode_info.audio.pin[i].channels = -1;
 597                 adev->mode_info.audio.pin[i].rate = -1;
 598                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 599                 adev->mode_info.audio.pin[i].status_bits = 0;
 600                 adev->mode_info.audio.pin[i].category_code = 0;
 601                 adev->mode_info.audio.pin[i].connected = false;
 602                 adev->mode_info.audio.pin[i].id =
 603                         adev->dm.dc->res_pool->audios[i]->inst;
 604                 adev->mode_info.audio.pin[i].offset = 0;
 605         }
 606 
 607         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 608         if (ret < 0)
 609                 return ret;
 610 
 611         adev->dm.audio_registered = true;
 612 
 613         return 0;
 614 }
 615 
 616 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 617 {
 618         if (!amdgpu_audio)
 619                 return;
 620 
 621         if (!adev->mode_info.audio.enabled)
 622                 return;
 623 
 624         if (adev->dm.audio_registered) {
 625                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 626                 adev->dm.audio_registered = false;
 627         }
 628 
 629         /* TODO: Disable audio? */
 630 
 631         adev->mode_info.audio.enabled = false;
 632 }
 633 
 634 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 635 {
 636         struct drm_audio_component *acomp = adev->dm.audio_component;
 637 
 638         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
 639                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
 640 
 641                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 642                                                  pin, -1);
 643         }
 644 }
 645 
 646 static int amdgpu_dm_init(struct amdgpu_device *adev)
 647 {
 648         struct dc_init_data init_data;
 649         adev->dm.ddev = adev->ddev;
 650         adev->dm.adev = adev;
 651 
 652         /* Zero all the fields */
 653         memset(&init_data, 0, sizeof(init_data));
 654 
 655         mutex_init(&adev->dm.dc_lock);
 656         mutex_init(&adev->dm.audio_lock);
 657 
 658         if(amdgpu_dm_irq_init(adev)) {
 659                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 660                 goto error;
 661         }
 662 
 663         init_data.asic_id.chip_family = adev->family;
 664 
 665         init_data.asic_id.pci_revision_id = adev->rev_id;
 666         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 667 
 668         init_data.asic_id.vram_width = adev->gmc.vram_width;
 669         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 670         init_data.asic_id.atombios_base_address =
 671                 adev->mode_info.atom_context->bios;
 672 
 673         init_data.driver = adev;
 674 
 675         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 676 
 677         if (!adev->dm.cgs_device) {
 678                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 679                 goto error;
 680         }
 681 
 682         init_data.cgs_device = adev->dm.cgs_device;
 683 
 684         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 685 
 686         /*
 687          * TODO debug why this doesn't work on Raven
 688          */
 689         if (adev->flags & AMD_IS_APU &&
 690             adev->asic_type >= CHIP_CARRIZO &&
 691             adev->asic_type < CHIP_RAVEN)
 692                 init_data.flags.gpu_vm_support = true;
 693 
 694         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 695                 init_data.flags.fbc_support = true;
 696 
 697         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
 698                 init_data.flags.multi_mon_pp_mclk_switch = true;
 699 
 700         init_data.flags.power_down_display_on_boot = true;
 701 
 702 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 703         init_data.soc_bounding_box = adev->dm.soc_bounding_box;
 704 #endif
 705 
 706         /* Display Core create. */
 707         adev->dm.dc = dc_create(&init_data);
 708 
 709         if (adev->dm.dc) {
 710                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 711         } else {
 712                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 713                 goto error;
 714         }
 715 
 716         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 717         if (!adev->dm.freesync_module) {
 718                 DRM_ERROR(
 719                 "amdgpu: failed to initialize freesync_module.\n");
 720         } else
 721                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 722                                 adev->dm.freesync_module);
 723 
 724         amdgpu_dm_init_color_mod();
 725 
 726         if (amdgpu_dm_initialize_drm_device(adev)) {
 727                 DRM_ERROR(
 728                 "amdgpu: failed to initialize sw for display support.\n");
 729                 goto error;
 730         }
 731 
 732         /* Update the actual used number of crtc */
 733         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 734 
 735         /* TODO: Add_display_info? */
 736 
 737         /* TODO use dynamic cursor width */
 738         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 739         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 740 
 741         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 742                 DRM_ERROR(
 743                 "amdgpu: failed to initialize sw for display support.\n");
 744                 goto error;
 745         }
 746 
 747 #if defined(CONFIG_DEBUG_FS)
 748         if (dtn_debugfs_init(adev))
 749                 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
 750 #endif
 751 
 752         DRM_DEBUG_DRIVER("KMS initialized.\n");
 753 
 754         return 0;
 755 error:
 756         amdgpu_dm_fini(adev);
 757 
 758         return -EINVAL;
 759 }
 760 
 761 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 762 {
 763         amdgpu_dm_audio_fini(adev);
 764 
 765         amdgpu_dm_destroy_drm_device(&adev->dm);
 766 
 767         /* DC Destroy TODO: Replace destroy DAL */
 768         if (adev->dm.dc)
 769                 dc_destroy(&adev->dm.dc);
 770         /*
 771          * TODO: pageflip, vlank interrupt
 772          *
 773          * amdgpu_dm_irq_fini(adev);
 774          */
 775 
 776         if (adev->dm.cgs_device) {
 777                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 778                 adev->dm.cgs_device = NULL;
 779         }
 780         if (adev->dm.freesync_module) {
 781                 mod_freesync_destroy(adev->dm.freesync_module);
 782                 adev->dm.freesync_module = NULL;
 783         }
 784 
 785         mutex_destroy(&adev->dm.audio_lock);
 786         mutex_destroy(&adev->dm.dc_lock);
 787 
 788         return;
 789 }
 790 
 791 static int load_dmcu_fw(struct amdgpu_device *adev)
 792 {
 793         const char *fw_name_dmcu = NULL;
 794         int r;
 795         const struct dmcu_firmware_header_v1_0 *hdr;
 796 
 797         switch(adev->asic_type) {
 798         case CHIP_BONAIRE:
 799         case CHIP_HAWAII:
 800         case CHIP_KAVERI:
 801         case CHIP_KABINI:
 802         case CHIP_MULLINS:
 803         case CHIP_TONGA:
 804         case CHIP_FIJI:
 805         case CHIP_CARRIZO:
 806         case CHIP_STONEY:
 807         case CHIP_POLARIS11:
 808         case CHIP_POLARIS10:
 809         case CHIP_POLARIS12:
 810         case CHIP_VEGAM:
 811         case CHIP_VEGA10:
 812         case CHIP_VEGA12:
 813         case CHIP_VEGA20:
 814         case CHIP_NAVI10:
 815         case CHIP_NAVI14:
 816         case CHIP_NAVI12:
 817         case CHIP_RENOIR:
 818                 return 0;
 819         case CHIP_RAVEN:
 820                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
 821                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 822                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
 823                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 824                 else
 825                         return 0;
 826                 break;
 827         default:
 828                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 829                 return -EINVAL;
 830         }
 831 
 832         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 833                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
 834                 return 0;
 835         }
 836 
 837         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
 838         if (r == -ENOENT) {
 839                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
 840                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
 841                 adev->dm.fw_dmcu = NULL;
 842                 return 0;
 843         }
 844         if (r) {
 845                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
 846                         fw_name_dmcu);
 847                 return r;
 848         }
 849 
 850         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
 851         if (r) {
 852                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
 853                         fw_name_dmcu);
 854                 release_firmware(adev->dm.fw_dmcu);
 855                 adev->dm.fw_dmcu = NULL;
 856                 return r;
 857         }
 858 
 859         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
 860         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
 861         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
 862         adev->firmware.fw_size +=
 863                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 864 
 865         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
 866         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
 867         adev->firmware.fw_size +=
 868                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 869 
 870         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
 871 
 872         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
 873 
 874         return 0;
 875 }
 876 
 877 static int dm_sw_init(void *handle)
 878 {
 879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 880 
 881         return load_dmcu_fw(adev);
 882 }
 883 
 884 static int dm_sw_fini(void *handle)
 885 {
 886         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 887 
 888         if(adev->dm.fw_dmcu) {
 889                 release_firmware(adev->dm.fw_dmcu);
 890                 adev->dm.fw_dmcu = NULL;
 891         }
 892 
 893         return 0;
 894 }
 895 
 896 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 897 {
 898         struct amdgpu_dm_connector *aconnector;
 899         struct drm_connector *connector;
 900         int ret = 0;
 901 
 902         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 903 
 904         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 905                 aconnector = to_amdgpu_dm_connector(connector);
 906                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 907                     aconnector->mst_mgr.aux) {
 908                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 909                                         aconnector, aconnector->base.base.id);
 910 
 911                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 912                         if (ret < 0) {
 913                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 914                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 915                                 return ret;
 916                                 }
 917                         }
 918         }
 919 
 920         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 921         return ret;
 922 }
 923 
 924 static int dm_late_init(void *handle)
 925 {
 926         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 927 
 928         struct dmcu_iram_parameters params;
 929         unsigned int linear_lut[16];
 930         int i;
 931         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
 932         bool ret = false;
 933 
 934         for (i = 0; i < 16; i++)
 935                 linear_lut[i] = 0xFFFF * i / 15;
 936 
 937         params.set = 0;
 938         params.backlight_ramping_start = 0xCCCC;
 939         params.backlight_ramping_reduction = 0xCCCCCCCC;
 940         params.backlight_lut_array_size = 16;
 941         params.backlight_lut_array = linear_lut;
 942 
 943         /* Min backlight level after ABM reduction,  Don't allow below 1%
 944          * 0xFFFF x 0.01 = 0x28F
 945          */
 946         params.min_abm_backlight = 0x28F;
 947 
 948         /* todo will enable for navi10 */
 949         if (adev->asic_type <= CHIP_RAVEN) {
 950                 ret = dmcu_load_iram(dmcu, params);
 951 
 952                 if (!ret)
 953                         return -EINVAL;
 954         }
 955 
 956         return detect_mst_link_for_all_connectors(adev->ddev);
 957 }
 958 
 959 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 960 {
 961         struct amdgpu_dm_connector *aconnector;
 962         struct drm_connector *connector;
 963         struct drm_dp_mst_topology_mgr *mgr;
 964         int ret;
 965         bool need_hotplug = false;
 966 
 967         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 968 
 969         list_for_each_entry(connector, &dev->mode_config.connector_list,
 970                             head) {
 971                 aconnector = to_amdgpu_dm_connector(connector);
 972                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
 973                     aconnector->mst_port)
 974                         continue;
 975 
 976                 mgr = &aconnector->mst_mgr;
 977 
 978                 if (suspend) {
 979                         drm_dp_mst_topology_mgr_suspend(mgr);
 980                 } else {
 981                         ret = drm_dp_mst_topology_mgr_resume(mgr);
 982                         if (ret < 0) {
 983                                 drm_dp_mst_topology_mgr_set_mst(mgr, false);
 984                                 need_hotplug = true;
 985                         }
 986                 }
 987         }
 988 
 989         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 990 
 991         if (need_hotplug)
 992                 drm_kms_helper_hotplug_event(dev);
 993 }
 994 
 995 /**
 996  * dm_hw_init() - Initialize DC device
 997  * @handle: The base driver device containing the amdpgu_dm device.
 998  *
 999  * Initialize the &struct amdgpu_display_manager device. This involves calling
1000  * the initializers of each DM component, then populating the struct with them.
1001  *
1002  * Although the function implies hardware initialization, both hardware and
1003  * software are initialized here. Splitting them out to their relevant init
1004  * hooks is a future TODO item.
1005  *
1006  * Some notable things that are initialized here:
1007  *
1008  * - Display Core, both software and hardware
1009  * - DC modules that we need (freesync and color management)
1010  * - DRM software states
1011  * - Interrupt sources and handlers
1012  * - Vblank support
1013  * - Debug FS entries, if enabled
1014  */
1015 static int dm_hw_init(void *handle)
1016 {
1017         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018         /* Create DAL display manager */
1019         amdgpu_dm_init(adev);
1020         amdgpu_dm_hpd_init(adev);
1021 
1022         return 0;
1023 }
1024 
1025 /**
1026  * dm_hw_fini() - Teardown DC device
1027  * @handle: The base driver device containing the amdpgu_dm device.
1028  *
1029  * Teardown components within &struct amdgpu_display_manager that require
1030  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1031  * were loaded. Also flush IRQ workqueues and disable them.
1032  */
1033 static int dm_hw_fini(void *handle)
1034 {
1035         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036 
1037         amdgpu_dm_hpd_fini(adev);
1038 
1039         amdgpu_dm_irq_fini(adev);
1040         amdgpu_dm_fini(adev);
1041         return 0;
1042 }
1043 
1044 static int dm_suspend(void *handle)
1045 {
1046         struct amdgpu_device *adev = handle;
1047         struct amdgpu_display_manager *dm = &adev->dm;
1048         int ret = 0;
1049 
1050         WARN_ON(adev->dm.cached_state);
1051         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1052 
1053         s3_handle_mst(adev->ddev, true);
1054 
1055         amdgpu_dm_irq_suspend(adev);
1056 
1057 
1058         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1059 
1060         return ret;
1061 }
1062 
1063 static struct amdgpu_dm_connector *
1064 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1065                                              struct drm_crtc *crtc)
1066 {
1067         uint32_t i;
1068         struct drm_connector_state *new_con_state;
1069         struct drm_connector *connector;
1070         struct drm_crtc *crtc_from_state;
1071 
1072         for_each_new_connector_in_state(state, connector, new_con_state, i) {
1073                 crtc_from_state = new_con_state->crtc;
1074 
1075                 if (crtc_from_state == crtc)
1076                         return to_amdgpu_dm_connector(connector);
1077         }
1078 
1079         return NULL;
1080 }
1081 
1082 static void emulated_link_detect(struct dc_link *link)
1083 {
1084         struct dc_sink_init_data sink_init_data = { 0 };
1085         struct display_sink_capability sink_caps = { 0 };
1086         enum dc_edid_status edid_status;
1087         struct dc_context *dc_ctx = link->ctx;
1088         struct dc_sink *sink = NULL;
1089         struct dc_sink *prev_sink = NULL;
1090 
1091         link->type = dc_connection_none;
1092         prev_sink = link->local_sink;
1093 
1094         if (prev_sink != NULL)
1095                 dc_sink_retain(prev_sink);
1096 
1097         switch (link->connector_signal) {
1098         case SIGNAL_TYPE_HDMI_TYPE_A: {
1099                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1100                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1101                 break;
1102         }
1103 
1104         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1105                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1106                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1107                 break;
1108         }
1109 
1110         case SIGNAL_TYPE_DVI_DUAL_LINK: {
1111                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1112                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1113                 break;
1114         }
1115 
1116         case SIGNAL_TYPE_LVDS: {
1117                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1118                 sink_caps.signal = SIGNAL_TYPE_LVDS;
1119                 break;
1120         }
1121 
1122         case SIGNAL_TYPE_EDP: {
1123                 sink_caps.transaction_type =
1124                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1125                 sink_caps.signal = SIGNAL_TYPE_EDP;
1126                 break;
1127         }
1128 
1129         case SIGNAL_TYPE_DISPLAY_PORT: {
1130                 sink_caps.transaction_type =
1131                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1132                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1133                 break;
1134         }
1135 
1136         default:
1137                 DC_ERROR("Invalid connector type! signal:%d\n",
1138                         link->connector_signal);
1139                 return;
1140         }
1141 
1142         sink_init_data.link = link;
1143         sink_init_data.sink_signal = sink_caps.signal;
1144 
1145         sink = dc_sink_create(&sink_init_data);
1146         if (!sink) {
1147                 DC_ERROR("Failed to create sink!\n");
1148                 return;
1149         }
1150 
1151         /* dc_sink_create returns a new reference */
1152         link->local_sink = sink;
1153 
1154         edid_status = dm_helpers_read_local_edid(
1155                         link->ctx,
1156                         link,
1157                         sink);
1158 
1159         if (edid_status != EDID_OK)
1160                 DC_ERROR("Failed to read EDID");
1161 
1162 }
1163 
1164 static int dm_resume(void *handle)
1165 {
1166         struct amdgpu_device *adev = handle;
1167         struct drm_device *ddev = adev->ddev;
1168         struct amdgpu_display_manager *dm = &adev->dm;
1169         struct amdgpu_dm_connector *aconnector;
1170         struct drm_connector *connector;
1171         struct drm_crtc *crtc;
1172         struct drm_crtc_state *new_crtc_state;
1173         struct dm_crtc_state *dm_new_crtc_state;
1174         struct drm_plane *plane;
1175         struct drm_plane_state *new_plane_state;
1176         struct dm_plane_state *dm_new_plane_state;
1177         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1178         enum dc_connection_type new_connection_type = dc_connection_none;
1179         int i;
1180 
1181         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1182         dc_release_state(dm_state->context);
1183         dm_state->context = dc_create_state(dm->dc);
1184         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1185         dc_resource_state_construct(dm->dc, dm_state->context);
1186 
1187         /* power on hardware */
1188         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1189 
1190         /* program HPD filter */
1191         dc_resume(dm->dc);
1192 
1193         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
1194         s3_handle_mst(ddev, false);
1195 
1196         /*
1197          * early enable HPD Rx IRQ, should be done before set mode as short
1198          * pulse interrupts are used for MST
1199          */
1200         amdgpu_dm_irq_resume_early(adev);
1201 
1202         /* Do detection*/
1203         list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
1204                 aconnector = to_amdgpu_dm_connector(connector);
1205 
1206                 /*
1207                  * this is the case when traversing through already created
1208                  * MST connectors, should be skipped
1209                  */
1210                 if (aconnector->mst_port)
1211                         continue;
1212 
1213                 mutex_lock(&aconnector->hpd_lock);
1214                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1215                         DRM_ERROR("KMS: Failed to detect connector\n");
1216 
1217                 if (aconnector->base.force && new_connection_type == dc_connection_none)
1218                         emulated_link_detect(aconnector->dc_link);
1219                 else
1220                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1221 
1222                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1223                         aconnector->fake_enable = false;
1224 
1225                 if (aconnector->dc_sink)
1226                         dc_sink_release(aconnector->dc_sink);
1227                 aconnector->dc_sink = NULL;
1228                 amdgpu_dm_update_connector_after_detect(aconnector);
1229                 mutex_unlock(&aconnector->hpd_lock);
1230         }
1231 
1232         /* Force mode set in atomic commit */
1233         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1234                 new_crtc_state->active_changed = true;
1235 
1236         /*
1237          * atomic_check is expected to create the dc states. We need to release
1238          * them here, since they were duplicated as part of the suspend
1239          * procedure.
1240          */
1241         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1242                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1243                 if (dm_new_crtc_state->stream) {
1244                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1245                         dc_stream_release(dm_new_crtc_state->stream);
1246                         dm_new_crtc_state->stream = NULL;
1247                 }
1248         }
1249 
1250         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1251                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1252                 if (dm_new_plane_state->dc_state) {
1253                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1254                         dc_plane_state_release(dm_new_plane_state->dc_state);
1255                         dm_new_plane_state->dc_state = NULL;
1256                 }
1257         }
1258 
1259         drm_atomic_helper_resume(ddev, dm->cached_state);
1260 
1261         dm->cached_state = NULL;
1262 
1263         amdgpu_dm_irq_resume_late(adev);
1264 
1265         return 0;
1266 }
1267 
1268 /**
1269  * DOC: DM Lifecycle
1270  *
1271  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1272  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1273  * the base driver's device list to be initialized and torn down accordingly.
1274  *
1275  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1276  */
1277 
1278 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1279         .name = "dm",
1280         .early_init = dm_early_init,
1281         .late_init = dm_late_init,
1282         .sw_init = dm_sw_init,
1283         .sw_fini = dm_sw_fini,
1284         .hw_init = dm_hw_init,
1285         .hw_fini = dm_hw_fini,
1286         .suspend = dm_suspend,
1287         .resume = dm_resume,
1288         .is_idle = dm_is_idle,
1289         .wait_for_idle = dm_wait_for_idle,
1290         .check_soft_reset = dm_check_soft_reset,
1291         .soft_reset = dm_soft_reset,
1292         .set_clockgating_state = dm_set_clockgating_state,
1293         .set_powergating_state = dm_set_powergating_state,
1294 };
1295 
1296 const struct amdgpu_ip_block_version dm_ip_block =
1297 {
1298         .type = AMD_IP_BLOCK_TYPE_DCE,
1299         .major = 1,
1300         .minor = 0,
1301         .rev = 0,
1302         .funcs = &amdgpu_dm_funcs,
1303 };
1304 
1305 
1306 /**
1307  * DOC: atomic
1308  *
1309  * *WIP*
1310  */
1311 
1312 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1313         .fb_create = amdgpu_display_user_framebuffer_create,
1314         .output_poll_changed = drm_fb_helper_output_poll_changed,
1315         .atomic_check = amdgpu_dm_atomic_check,
1316         .atomic_commit = amdgpu_dm_atomic_commit,
1317 };
1318 
1319 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1320         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1321 };
1322 
1323 static void
1324 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1325 {
1326         struct drm_connector *connector = &aconnector->base;
1327         struct drm_device *dev = connector->dev;
1328         struct dc_sink *sink;
1329 
1330         /* MST handled by drm_mst framework */
1331         if (aconnector->mst_mgr.mst_state == true)
1332                 return;
1333 
1334 
1335         sink = aconnector->dc_link->local_sink;
1336         if (sink)
1337                 dc_sink_retain(sink);
1338 
1339         /*
1340          * Edid mgmt connector gets first update only in mode_valid hook and then
1341          * the connector sink is set to either fake or physical sink depends on link status.
1342          * Skip if already done during boot.
1343          */
1344         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1345                         && aconnector->dc_em_sink) {
1346 
1347                 /*
1348                  * For S3 resume with headless use eml_sink to fake stream
1349                  * because on resume connector->sink is set to NULL
1350                  */
1351                 mutex_lock(&dev->mode_config.mutex);
1352 
1353                 if (sink) {
1354                         if (aconnector->dc_sink) {
1355                                 amdgpu_dm_update_freesync_caps(connector, NULL);
1356                                 /*
1357                                  * retain and release below are used to
1358                                  * bump up refcount for sink because the link doesn't point
1359                                  * to it anymore after disconnect, so on next crtc to connector
1360                                  * reshuffle by UMD we will get into unwanted dc_sink release
1361                                  */
1362                                 dc_sink_release(aconnector->dc_sink);
1363                         }
1364                         aconnector->dc_sink = sink;
1365                         dc_sink_retain(aconnector->dc_sink);
1366                         amdgpu_dm_update_freesync_caps(connector,
1367                                         aconnector->edid);
1368                 } else {
1369                         amdgpu_dm_update_freesync_caps(connector, NULL);
1370                         if (!aconnector->dc_sink) {
1371                                 aconnector->dc_sink = aconnector->dc_em_sink;
1372                                 dc_sink_retain(aconnector->dc_sink);
1373                         }
1374                 }
1375 
1376                 mutex_unlock(&dev->mode_config.mutex);
1377 
1378                 if (sink)
1379                         dc_sink_release(sink);
1380                 return;
1381         }
1382 
1383         /*
1384          * TODO: temporary guard to look for proper fix
1385          * if this sink is MST sink, we should not do anything
1386          */
1387         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1388                 dc_sink_release(sink);
1389                 return;
1390         }
1391 
1392         if (aconnector->dc_sink == sink) {
1393                 /*
1394                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
1395                  * Do nothing!!
1396                  */
1397                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1398                                 aconnector->connector_id);
1399                 if (sink)
1400                         dc_sink_release(sink);
1401                 return;
1402         }
1403 
1404         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1405                 aconnector->connector_id, aconnector->dc_sink, sink);
1406 
1407         mutex_lock(&dev->mode_config.mutex);
1408 
1409         /*
1410          * 1. Update status of the drm connector
1411          * 2. Send an event and let userspace tell us what to do
1412          */
1413         if (sink) {
1414                 /*
1415                  * TODO: check if we still need the S3 mode update workaround.
1416                  * If yes, put it here.
1417                  */
1418                 if (aconnector->dc_sink)
1419                         amdgpu_dm_update_freesync_caps(connector, NULL);
1420 
1421                 aconnector->dc_sink = sink;
1422                 dc_sink_retain(aconnector->dc_sink);
1423                 if (sink->dc_edid.length == 0) {
1424                         aconnector->edid = NULL;
1425                         if (aconnector->dc_link->aux_mode) {
1426                                 drm_dp_cec_unset_edid(
1427                                         &aconnector->dm_dp_aux.aux);
1428                         }
1429                 } else {
1430                         aconnector->edid =
1431                                 (struct edid *)sink->dc_edid.raw_edid;
1432 
1433                         drm_connector_update_edid_property(connector,
1434                                                            aconnector->edid);
1435 
1436                         if (aconnector->dc_link->aux_mode)
1437                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1438                                                     aconnector->edid);
1439                 }
1440 
1441                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1442 
1443         } else {
1444                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1445                 amdgpu_dm_update_freesync_caps(connector, NULL);
1446                 drm_connector_update_edid_property(connector, NULL);
1447                 aconnector->num_modes = 0;
1448                 dc_sink_release(aconnector->dc_sink);
1449                 aconnector->dc_sink = NULL;
1450                 aconnector->edid = NULL;
1451         }
1452 
1453         mutex_unlock(&dev->mode_config.mutex);
1454 
1455         if (sink)
1456                 dc_sink_release(sink);
1457 }
1458 
1459 static void handle_hpd_irq(void *param)
1460 {
1461         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1462         struct drm_connector *connector = &aconnector->base;
1463         struct drm_device *dev = connector->dev;
1464         enum dc_connection_type new_connection_type = dc_connection_none;
1465 
1466         /*
1467          * In case of failure or MST no need to update connector status or notify the OS
1468          * since (for MST case) MST does this in its own context.
1469          */
1470         mutex_lock(&aconnector->hpd_lock);
1471 
1472         if (aconnector->fake_enable)
1473                 aconnector->fake_enable = false;
1474 
1475         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1476                 DRM_ERROR("KMS: Failed to detect connector\n");
1477 
1478         if (aconnector->base.force && new_connection_type == dc_connection_none) {
1479                 emulated_link_detect(aconnector->dc_link);
1480 
1481 
1482                 drm_modeset_lock_all(dev);
1483                 dm_restore_drm_connector_state(dev, connector);
1484                 drm_modeset_unlock_all(dev);
1485 
1486                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1487                         drm_kms_helper_hotplug_event(dev);
1488 
1489         } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1490                 amdgpu_dm_update_connector_after_detect(aconnector);
1491 
1492 
1493                 drm_modeset_lock_all(dev);
1494                 dm_restore_drm_connector_state(dev, connector);
1495                 drm_modeset_unlock_all(dev);
1496 
1497                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1498                         drm_kms_helper_hotplug_event(dev);
1499         }
1500         mutex_unlock(&aconnector->hpd_lock);
1501 
1502 }
1503 
1504 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1505 {
1506         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1507         uint8_t dret;
1508         bool new_irq_handled = false;
1509         int dpcd_addr;
1510         int dpcd_bytes_to_read;
1511 
1512         const int max_process_count = 30;
1513         int process_count = 0;
1514 
1515         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1516 
1517         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1518                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1519                 /* DPCD 0x200 - 0x201 for downstream IRQ */
1520                 dpcd_addr = DP_SINK_COUNT;
1521         } else {
1522                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1523                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1524                 dpcd_addr = DP_SINK_COUNT_ESI;
1525         }
1526 
1527         dret = drm_dp_dpcd_read(
1528                 &aconnector->dm_dp_aux.aux,
1529                 dpcd_addr,
1530                 esi,
1531                 dpcd_bytes_to_read);
1532 
1533         while (dret == dpcd_bytes_to_read &&
1534                 process_count < max_process_count) {
1535                 uint8_t retry;
1536                 dret = 0;
1537 
1538                 process_count++;
1539 
1540                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1541                 /* handle HPD short pulse irq */
1542                 if (aconnector->mst_mgr.mst_state)
1543                         drm_dp_mst_hpd_irq(
1544                                 &aconnector->mst_mgr,
1545                                 esi,
1546                                 &new_irq_handled);
1547 
1548                 if (new_irq_handled) {
1549                         /* ACK at DPCD to notify down stream */
1550                         const int ack_dpcd_bytes_to_write =
1551                                 dpcd_bytes_to_read - 1;
1552 
1553                         for (retry = 0; retry < 3; retry++) {
1554                                 uint8_t wret;
1555 
1556                                 wret = drm_dp_dpcd_write(
1557                                         &aconnector->dm_dp_aux.aux,
1558                                         dpcd_addr + 1,
1559                                         &esi[1],
1560                                         ack_dpcd_bytes_to_write);
1561                                 if (wret == ack_dpcd_bytes_to_write)
1562                                         break;
1563                         }
1564 
1565                         /* check if there is new irq to be handled */
1566                         dret = drm_dp_dpcd_read(
1567                                 &aconnector->dm_dp_aux.aux,
1568                                 dpcd_addr,
1569                                 esi,
1570                                 dpcd_bytes_to_read);
1571 
1572                         new_irq_handled = false;
1573                 } else {
1574                         break;
1575                 }
1576         }
1577 
1578         if (process_count == max_process_count)
1579                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1580 }
1581 
1582 static void handle_hpd_rx_irq(void *param)
1583 {
1584         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1585         struct drm_connector *connector = &aconnector->base;
1586         struct drm_device *dev = connector->dev;
1587         struct dc_link *dc_link = aconnector->dc_link;
1588         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1589         enum dc_connection_type new_connection_type = dc_connection_none;
1590 
1591         /*
1592          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1593          * conflict, after implement i2c helper, this mutex should be
1594          * retired.
1595          */
1596         if (dc_link->type != dc_connection_mst_branch)
1597                 mutex_lock(&aconnector->hpd_lock);
1598 
1599         if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1600                         !is_mst_root_connector) {
1601                 /* Downstream Port status changed. */
1602                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1603                         DRM_ERROR("KMS: Failed to detect connector\n");
1604 
1605                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1606                         emulated_link_detect(dc_link);
1607 
1608                         if (aconnector->fake_enable)
1609                                 aconnector->fake_enable = false;
1610 
1611                         amdgpu_dm_update_connector_after_detect(aconnector);
1612 
1613 
1614                         drm_modeset_lock_all(dev);
1615                         dm_restore_drm_connector_state(dev, connector);
1616                         drm_modeset_unlock_all(dev);
1617 
1618                         drm_kms_helper_hotplug_event(dev);
1619                 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1620 
1621                         if (aconnector->fake_enable)
1622                                 aconnector->fake_enable = false;
1623 
1624                         amdgpu_dm_update_connector_after_detect(aconnector);
1625 
1626 
1627                         drm_modeset_lock_all(dev);
1628                         dm_restore_drm_connector_state(dev, connector);
1629                         drm_modeset_unlock_all(dev);
1630 
1631                         drm_kms_helper_hotplug_event(dev);
1632                 }
1633         }
1634         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1635             (dc_link->type == dc_connection_mst_branch))
1636                 dm_handle_hpd_rx_irq(aconnector);
1637 
1638         if (dc_link->type != dc_connection_mst_branch) {
1639                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1640                 mutex_unlock(&aconnector->hpd_lock);
1641         }
1642 }
1643 
1644 static void register_hpd_handlers(struct amdgpu_device *adev)
1645 {
1646         struct drm_device *dev = adev->ddev;
1647         struct drm_connector *connector;
1648         struct amdgpu_dm_connector *aconnector;
1649         const struct dc_link *dc_link;
1650         struct dc_interrupt_params int_params = {0};
1651 
1652         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1653         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1654 
1655         list_for_each_entry(connector,
1656                         &dev->mode_config.connector_list, head) {
1657 
1658                 aconnector = to_amdgpu_dm_connector(connector);
1659                 dc_link = aconnector->dc_link;
1660 
1661                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1662                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1663                         int_params.irq_source = dc_link->irq_source_hpd;
1664 
1665                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1666                                         handle_hpd_irq,
1667                                         (void *) aconnector);
1668                 }
1669 
1670                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1671 
1672                         /* Also register for DP short pulse (hpd_rx). */
1673                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1674                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1675 
1676                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1677                                         handle_hpd_rx_irq,
1678                                         (void *) aconnector);
1679                 }
1680         }
1681 }
1682 
1683 /* Register IRQ sources and initialize IRQ callbacks */
1684 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1685 {
1686         struct dc *dc = adev->dm.dc;
1687         struct common_irq_params *c_irq_params;
1688         struct dc_interrupt_params int_params = {0};
1689         int r;
1690         int i;
1691         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1692 
1693         if (adev->asic_type >= CHIP_VEGA10)
1694                 client_id = SOC15_IH_CLIENTID_DCE;
1695 
1696         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1697         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1698 
1699         /*
1700          * Actions of amdgpu_irq_add_id():
1701          * 1. Register a set() function with base driver.
1702          *    Base driver will call set() function to enable/disable an
1703          *    interrupt in DC hardware.
1704          * 2. Register amdgpu_dm_irq_handler().
1705          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1706          *    coming from DC hardware.
1707          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1708          *    for acknowledging and handling. */
1709 
1710         /* Use VBLANK interrupt */
1711         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1712                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1713                 if (r) {
1714                         DRM_ERROR("Failed to add crtc irq id!\n");
1715                         return r;
1716                 }
1717 
1718                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1719                 int_params.irq_source =
1720                         dc_interrupt_to_irq_source(dc, i, 0);
1721 
1722                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1723 
1724                 c_irq_params->adev = adev;
1725                 c_irq_params->irq_src = int_params.irq_source;
1726 
1727                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1728                                 dm_crtc_high_irq, c_irq_params);
1729         }
1730 
1731         /* Use VUPDATE interrupt */
1732         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1733                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1734                 if (r) {
1735                         DRM_ERROR("Failed to add vupdate irq id!\n");
1736                         return r;
1737                 }
1738 
1739                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1740                 int_params.irq_source =
1741                         dc_interrupt_to_irq_source(dc, i, 0);
1742 
1743                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1744 
1745                 c_irq_params->adev = adev;
1746                 c_irq_params->irq_src = int_params.irq_source;
1747 
1748                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1749                                 dm_vupdate_high_irq, c_irq_params);
1750         }
1751 
1752         /* Use GRPH_PFLIP interrupt */
1753         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1754                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1755                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1756                 if (r) {
1757                         DRM_ERROR("Failed to add page flip irq id!\n");
1758                         return r;
1759                 }
1760 
1761                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1762                 int_params.irq_source =
1763                         dc_interrupt_to_irq_source(dc, i, 0);
1764 
1765                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1766 
1767                 c_irq_params->adev = adev;
1768                 c_irq_params->irq_src = int_params.irq_source;
1769 
1770                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1771                                 dm_pflip_high_irq, c_irq_params);
1772 
1773         }
1774 
1775         /* HPD */
1776         r = amdgpu_irq_add_id(adev, client_id,
1777                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1778         if (r) {
1779                 DRM_ERROR("Failed to add hpd irq id!\n");
1780                 return r;
1781         }
1782 
1783         register_hpd_handlers(adev);
1784 
1785         return 0;
1786 }
1787 
1788 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1789 /* Register IRQ sources and initialize IRQ callbacks */
1790 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1791 {
1792         struct dc *dc = adev->dm.dc;
1793         struct common_irq_params *c_irq_params;
1794         struct dc_interrupt_params int_params = {0};
1795         int r;
1796         int i;
1797 
1798         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1799         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1800 
1801         /*
1802          * Actions of amdgpu_irq_add_id():
1803          * 1. Register a set() function with base driver.
1804          *    Base driver will call set() function to enable/disable an
1805          *    interrupt in DC hardware.
1806          * 2. Register amdgpu_dm_irq_handler().
1807          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1808          *    coming from DC hardware.
1809          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1810          *    for acknowledging and handling.
1811          */
1812 
1813         /* Use VSTARTUP interrupt */
1814         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1815                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1816                         i++) {
1817                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1818 
1819                 if (r) {
1820                         DRM_ERROR("Failed to add crtc irq id!\n");
1821                         return r;
1822                 }
1823 
1824                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1825                 int_params.irq_source =
1826                         dc_interrupt_to_irq_source(dc, i, 0);
1827 
1828                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1829 
1830                 c_irq_params->adev = adev;
1831                 c_irq_params->irq_src = int_params.irq_source;
1832 
1833                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1834                                 dm_crtc_high_irq, c_irq_params);
1835         }
1836 
1837         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1838          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1839          * to trigger at end of each vblank, regardless of state of the lock,
1840          * matching DCE behaviour.
1841          */
1842         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1843              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1844              i++) {
1845                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1846 
1847                 if (r) {
1848                         DRM_ERROR("Failed to add vupdate irq id!\n");
1849                         return r;
1850                 }
1851 
1852                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1853                 int_params.irq_source =
1854                         dc_interrupt_to_irq_source(dc, i, 0);
1855 
1856                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1857 
1858                 c_irq_params->adev = adev;
1859                 c_irq_params->irq_src = int_params.irq_source;
1860 
1861                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1862                                 dm_vupdate_high_irq, c_irq_params);
1863         }
1864 
1865         /* Use GRPH_PFLIP interrupt */
1866         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1867                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1868                         i++) {
1869                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1870                 if (r) {
1871                         DRM_ERROR("Failed to add page flip irq id!\n");
1872                         return r;
1873                 }
1874 
1875                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1876                 int_params.irq_source =
1877                         dc_interrupt_to_irq_source(dc, i, 0);
1878 
1879                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1880 
1881                 c_irq_params->adev = adev;
1882                 c_irq_params->irq_src = int_params.irq_source;
1883 
1884                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1885                                 dm_pflip_high_irq, c_irq_params);
1886 
1887         }
1888 
1889         /* HPD */
1890         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1891                         &adev->hpd_irq);
1892         if (r) {
1893                 DRM_ERROR("Failed to add hpd irq id!\n");
1894                 return r;
1895         }
1896 
1897         register_hpd_handlers(adev);
1898 
1899         return 0;
1900 }
1901 #endif
1902 
1903 /*
1904  * Acquires the lock for the atomic state object and returns
1905  * the new atomic state.
1906  *
1907  * This should only be called during atomic check.
1908  */
1909 static int dm_atomic_get_state(struct drm_atomic_state *state,
1910                                struct dm_atomic_state **dm_state)
1911 {
1912         struct drm_device *dev = state->dev;
1913         struct amdgpu_device *adev = dev->dev_private;
1914         struct amdgpu_display_manager *dm = &adev->dm;
1915         struct drm_private_state *priv_state;
1916 
1917         if (*dm_state)
1918                 return 0;
1919 
1920         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1921         if (IS_ERR(priv_state))
1922                 return PTR_ERR(priv_state);
1923 
1924         *dm_state = to_dm_atomic_state(priv_state);
1925 
1926         return 0;
1927 }
1928 
1929 struct dm_atomic_state *
1930 dm_atomic_get_new_state(struct drm_atomic_state *state)
1931 {
1932         struct drm_device *dev = state->dev;
1933         struct amdgpu_device *adev = dev->dev_private;
1934         struct amdgpu_display_manager *dm = &adev->dm;
1935         struct drm_private_obj *obj;
1936         struct drm_private_state *new_obj_state;
1937         int i;
1938 
1939         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1940                 if (obj->funcs == dm->atomic_obj.funcs)
1941                         return to_dm_atomic_state(new_obj_state);
1942         }
1943 
1944         return NULL;
1945 }
1946 
1947 struct dm_atomic_state *
1948 dm_atomic_get_old_state(struct drm_atomic_state *state)
1949 {
1950         struct drm_device *dev = state->dev;
1951         struct amdgpu_device *adev = dev->dev_private;
1952         struct amdgpu_display_manager *dm = &adev->dm;
1953         struct drm_private_obj *obj;
1954         struct drm_private_state *old_obj_state;
1955         int i;
1956 
1957         for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1958                 if (obj->funcs == dm->atomic_obj.funcs)
1959                         return to_dm_atomic_state(old_obj_state);
1960         }
1961 
1962         return NULL;
1963 }
1964 
1965 static struct drm_private_state *
1966 dm_atomic_duplicate_state(struct drm_private_obj *obj)
1967 {
1968         struct dm_atomic_state *old_state, *new_state;
1969 
1970         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1971         if (!new_state)
1972                 return NULL;
1973 
1974         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1975 
1976         old_state = to_dm_atomic_state(obj->state);
1977 
1978         if (old_state && old_state->context)
1979                 new_state->context = dc_copy_state(old_state->context);
1980 
1981         if (!new_state->context) {
1982                 kfree(new_state);
1983                 return NULL;
1984         }
1985 
1986         return &new_state->base;
1987 }
1988 
1989 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1990                                     struct drm_private_state *state)
1991 {
1992         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1993 
1994         if (dm_state && dm_state->context)
1995                 dc_release_state(dm_state->context);
1996 
1997         kfree(dm_state);
1998 }
1999 
2000 static struct drm_private_state_funcs dm_atomic_state_funcs = {
2001         .atomic_duplicate_state = dm_atomic_duplicate_state,
2002         .atomic_destroy_state = dm_atomic_destroy_state,
2003 };
2004 
2005 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2006 {
2007         struct dm_atomic_state *state;
2008         int r;
2009 
2010         adev->mode_info.mode_config_initialized = true;
2011 
2012         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
2013         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
2014 
2015         adev->ddev->mode_config.max_width = 16384;
2016         adev->ddev->mode_config.max_height = 16384;
2017 
2018         adev->ddev->mode_config.preferred_depth = 24;
2019         adev->ddev->mode_config.prefer_shadow = 1;
2020         /* indicates support for immediate flip */
2021         adev->ddev->mode_config.async_page_flip = true;
2022 
2023         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2024 
2025         state = kzalloc(sizeof(*state), GFP_KERNEL);
2026         if (!state)
2027                 return -ENOMEM;
2028 
2029         state->context = dc_create_state(adev->dm.dc);
2030         if (!state->context) {
2031                 kfree(state);
2032                 return -ENOMEM;
2033         }
2034 
2035         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2036 
2037         drm_atomic_private_obj_init(adev->ddev,
2038                                     &adev->dm.atomic_obj,
2039                                     &state->base,
2040                                     &dm_atomic_state_funcs);
2041 
2042         r = amdgpu_display_modeset_create_props(adev);
2043         if (r)
2044                 return r;
2045 
2046         r = amdgpu_dm_audio_init(adev);
2047         if (r)
2048                 return r;
2049 
2050         return 0;
2051 }
2052 
2053 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2054 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2055 
2056 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2057         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2058 
2059 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2060 {
2061 #if defined(CONFIG_ACPI)
2062         struct amdgpu_dm_backlight_caps caps;
2063 
2064         if (dm->backlight_caps.caps_valid)
2065                 return;
2066 
2067         amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2068         if (caps.caps_valid) {
2069                 dm->backlight_caps.min_input_signal = caps.min_input_signal;
2070                 dm->backlight_caps.max_input_signal = caps.max_input_signal;
2071                 dm->backlight_caps.caps_valid = true;
2072         } else {
2073                 dm->backlight_caps.min_input_signal =
2074                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2075                 dm->backlight_caps.max_input_signal =
2076                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2077         }
2078 #else
2079         dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2080         dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2081 #endif
2082 }
2083 
2084 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2085 {
2086         struct amdgpu_display_manager *dm = bl_get_data(bd);
2087         struct amdgpu_dm_backlight_caps caps;
2088         uint32_t brightness = bd->props.brightness;
2089 
2090         amdgpu_dm_update_backlight_caps(dm);
2091         caps = dm->backlight_caps;
2092         /*
2093          * The brightness input is in the range 0-255
2094          * It needs to be rescaled to be between the
2095          * requested min and max input signal
2096          *
2097          * It also needs to be scaled up by 0x101 to
2098          * match the DC interface which has a range of
2099          * 0 to 0xffff
2100          */
2101         brightness =
2102                 brightness
2103                 * 0x101
2104                 * (caps.max_input_signal - caps.min_input_signal)
2105                 / AMDGPU_MAX_BL_LEVEL
2106                 + caps.min_input_signal * 0x101;
2107 
2108         if (dc_link_set_backlight_level(dm->backlight_link,
2109                         brightness, 0))
2110                 return 0;
2111         else
2112                 return 1;
2113 }
2114 
2115 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2116 {
2117         struct amdgpu_display_manager *dm = bl_get_data(bd);
2118         int ret = dc_link_get_backlight_level(dm->backlight_link);
2119 
2120         if (ret == DC_ERROR_UNEXPECTED)
2121                 return bd->props.brightness;
2122         return ret;
2123 }
2124 
2125 static const struct backlight_ops amdgpu_dm_backlight_ops = {
2126         .options = BL_CORE_SUSPENDRESUME,
2127         .get_brightness = amdgpu_dm_backlight_get_brightness,
2128         .update_status  = amdgpu_dm_backlight_update_status,
2129 };
2130 
2131 static void
2132 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
2133 {
2134         char bl_name[16];
2135         struct backlight_properties props = { 0 };
2136 
2137         amdgpu_dm_update_backlight_caps(dm);
2138 
2139         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
2140         props.brightness = AMDGPU_MAX_BL_LEVEL;
2141         props.type = BACKLIGHT_RAW;
2142 
2143         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2144                         dm->adev->ddev->primary->index);
2145 
2146         dm->backlight_dev = backlight_device_register(bl_name,
2147                         dm->adev->ddev->dev,
2148                         dm,
2149                         &amdgpu_dm_backlight_ops,
2150                         &props);
2151 
2152         if (IS_ERR(dm->backlight_dev))
2153                 DRM_ERROR("DM: Backlight registration failed!\n");
2154         else
2155                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
2156 }
2157 
2158 #endif
2159 
2160 static int initialize_plane(struct amdgpu_display_manager *dm,
2161                             struct amdgpu_mode_info *mode_info, int plane_id,
2162                             enum drm_plane_type plane_type,
2163                             const struct dc_plane_cap *plane_cap)
2164 {
2165         struct drm_plane *plane;
2166         unsigned long possible_crtcs;
2167         int ret = 0;
2168 
2169         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
2170         if (!plane) {
2171                 DRM_ERROR("KMS: Failed to allocate plane\n");
2172                 return -ENOMEM;
2173         }
2174         plane->type = plane_type;
2175 
2176         /*
2177          * HACK: IGT tests expect that the primary plane for a CRTC
2178          * can only have one possible CRTC. Only expose support for
2179          * any CRTC if they're not going to be used as a primary plane
2180          * for a CRTC - like overlay or underlay planes.
2181          */
2182         possible_crtcs = 1 << plane_id;
2183         if (plane_id >= dm->dc->caps.max_streams)
2184                 possible_crtcs = 0xff;
2185 
2186         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2187 
2188         if (ret) {
2189                 DRM_ERROR("KMS: Failed to initialize plane\n");
2190                 kfree(plane);
2191                 return ret;
2192         }
2193 
2194         if (mode_info)
2195                 mode_info->planes[plane_id] = plane;
2196 
2197         return ret;
2198 }
2199 
2200 
2201 static void register_backlight_device(struct amdgpu_display_manager *dm,
2202                                       struct dc_link *link)
2203 {
2204 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2205         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2206 
2207         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2208             link->type != dc_connection_none) {
2209                 /*
2210                  * Event if registration failed, we should continue with
2211                  * DM initialization because not having a backlight control
2212                  * is better then a black screen.
2213                  */
2214                 amdgpu_dm_register_backlight_device(dm);
2215 
2216                 if (dm->backlight_dev)
2217                         dm->backlight_link = link;
2218         }
2219 #endif
2220 }
2221 
2222 
2223 /*
2224  * In this architecture, the association
2225  * connector -> encoder -> crtc
2226  * id not really requried. The crtc and connector will hold the
2227  * display_index as an abstraction to use with DAL component
2228  *
2229  * Returns 0 on success
2230  */
2231 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2232 {
2233         struct amdgpu_display_manager *dm = &adev->dm;
2234         int32_t i;
2235         struct amdgpu_dm_connector *aconnector = NULL;
2236         struct amdgpu_encoder *aencoder = NULL;
2237         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2238         uint32_t link_cnt;
2239         int32_t primary_planes;
2240         enum dc_connection_type new_connection_type = dc_connection_none;
2241         const struct dc_plane_cap *plane;
2242 
2243         link_cnt = dm->dc->caps.max_links;
2244         if (amdgpu_dm_mode_config_init(dm->adev)) {
2245                 DRM_ERROR("DM: Failed to initialize mode config\n");
2246                 return -EINVAL;
2247         }
2248 
2249         /* There is one primary plane per CRTC */
2250         primary_planes = dm->dc->caps.max_streams;
2251         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2252 
2253         /*
2254          * Initialize primary planes, implicit planes for legacy IOCTLS.
2255          * Order is reversed to match iteration order in atomic check.
2256          */
2257         for (i = (primary_planes - 1); i >= 0; i--) {
2258                 plane = &dm->dc->caps.planes[i];
2259 
2260                 if (initialize_plane(dm, mode_info, i,
2261                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
2262                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
2263                         goto fail;
2264                 }
2265         }
2266 
2267         /*
2268          * Initialize overlay planes, index starting after primary planes.
2269          * These planes have a higher DRM index than the primary planes since
2270          * they should be considered as having a higher z-order.
2271          * Order is reversed to match iteration order in atomic check.
2272          *
2273          * Only support DCN for now, and only expose one so we don't encourage
2274          * userspace to use up all the pipes.
2275          */
2276         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2277                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2278 
2279                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2280                         continue;
2281 
2282                 if (!plane->blends_with_above || !plane->blends_with_below)
2283                         continue;
2284 
2285                 if (!plane->pixel_format_support.argb8888)
2286                         continue;
2287 
2288                 if (initialize_plane(dm, NULL, primary_planes + i,
2289                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
2290                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2291                         goto fail;
2292                 }
2293 
2294                 /* Only create one overlay plane. */
2295                 break;
2296         }
2297 
2298         for (i = 0; i < dm->dc->caps.max_streams; i++)
2299                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2300                         DRM_ERROR("KMS: Failed to initialize crtc\n");
2301                         goto fail;
2302                 }
2303 
2304         dm->display_indexes_num = dm->dc->caps.max_streams;
2305 
2306         /* loops over all connectors on the board */
2307         for (i = 0; i < link_cnt; i++) {
2308                 struct dc_link *link = NULL;
2309 
2310                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2311                         DRM_ERROR(
2312                                 "KMS: Cannot support more than %d display indexes\n",
2313                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
2314                         continue;
2315                 }
2316 
2317                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2318                 if (!aconnector)
2319                         goto fail;
2320 
2321                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2322                 if (!aencoder)
2323                         goto fail;
2324 
2325                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2326                         DRM_ERROR("KMS: Failed to initialize encoder\n");
2327                         goto fail;
2328                 }
2329 
2330                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2331                         DRM_ERROR("KMS: Failed to initialize connector\n");
2332                         goto fail;
2333                 }
2334 
2335                 link = dc_get_link_at_index(dm->dc, i);
2336 
2337                 if (!dc_link_detect_sink(link, &new_connection_type))
2338                         DRM_ERROR("KMS: Failed to detect connector\n");
2339 
2340                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2341                         emulated_link_detect(link);
2342                         amdgpu_dm_update_connector_after_detect(aconnector);
2343 
2344                 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2345                         amdgpu_dm_update_connector_after_detect(aconnector);
2346                         register_backlight_device(dm, link);
2347                 }
2348 
2349 
2350         }
2351 
2352         /* Software is initialized. Now we can register interrupt handlers. */
2353         switch (adev->asic_type) {
2354         case CHIP_BONAIRE:
2355         case CHIP_HAWAII:
2356         case CHIP_KAVERI:
2357         case CHIP_KABINI:
2358         case CHIP_MULLINS:
2359         case CHIP_TONGA:
2360         case CHIP_FIJI:
2361         case CHIP_CARRIZO:
2362         case CHIP_STONEY:
2363         case CHIP_POLARIS11:
2364         case CHIP_POLARIS10:
2365         case CHIP_POLARIS12:
2366         case CHIP_VEGAM:
2367         case CHIP_VEGA10:
2368         case CHIP_VEGA12:
2369         case CHIP_VEGA20:
2370                 if (dce110_register_irq_handlers(dm->adev)) {
2371                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2372                         goto fail;
2373                 }
2374                 break;
2375 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2376         case CHIP_RAVEN:
2377 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2378         case CHIP_NAVI12:
2379         case CHIP_NAVI10:
2380         case CHIP_NAVI14:
2381 #endif
2382 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2383         case CHIP_RENOIR:
2384 #endif
2385                 if (dcn10_register_irq_handlers(dm->adev)) {
2386                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2387                         goto fail;
2388                 }
2389                 break;
2390 #endif
2391         default:
2392                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2393                 goto fail;
2394         }
2395 
2396         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2397                 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2398 
2399         return 0;
2400 fail:
2401         kfree(aencoder);
2402         kfree(aconnector);
2403 
2404         return -EINVAL;
2405 }
2406 
2407 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2408 {
2409         drm_mode_config_cleanup(dm->ddev);
2410         drm_atomic_private_obj_fini(&dm->atomic_obj);
2411         return;
2412 }
2413 
2414 /******************************************************************************
2415  * amdgpu_display_funcs functions
2416  *****************************************************************************/
2417 
2418 /*
2419  * dm_bandwidth_update - program display watermarks
2420  *
2421  * @adev: amdgpu_device pointer
2422  *
2423  * Calculate and program the display watermarks and line buffer allocation.
2424  */
2425 static void dm_bandwidth_update(struct amdgpu_device *adev)
2426 {
2427         /* TODO: implement later */
2428 }
2429 
2430 static const struct amdgpu_display_funcs dm_display_funcs = {
2431         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2432         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2433         .backlight_set_level = NULL, /* never called for DC */
2434         .backlight_get_level = NULL, /* never called for DC */
2435         .hpd_sense = NULL,/* called unconditionally */
2436         .hpd_set_polarity = NULL, /* called unconditionally */
2437         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2438         .page_flip_get_scanoutpos =
2439                 dm_crtc_get_scanoutpos,/* called unconditionally */
2440         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2441         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2442 };
2443 
2444 #if defined(CONFIG_DEBUG_KERNEL_DC)
2445 
2446 static ssize_t s3_debug_store(struct device *device,
2447                               struct device_attribute *attr,
2448                               const char *buf,
2449                               size_t count)
2450 {
2451         int ret;
2452         int s3_state;
2453         struct drm_device *drm_dev = dev_get_drvdata(device);
2454         struct amdgpu_device *adev = drm_dev->dev_private;
2455 
2456         ret = kstrtoint(buf, 0, &s3_state);
2457 
2458         if (ret == 0) {
2459                 if (s3_state) {
2460                         dm_resume(adev);
2461                         drm_kms_helper_hotplug_event(adev->ddev);
2462                 } else
2463                         dm_suspend(adev);
2464         }
2465 
2466         return ret == 0 ? count : 0;
2467 }
2468 
2469 DEVICE_ATTR_WO(s3_debug);
2470 
2471 #endif
2472 
2473 static int dm_early_init(void *handle)
2474 {
2475         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2476 
2477         switch (adev->asic_type) {
2478         case CHIP_BONAIRE:
2479         case CHIP_HAWAII:
2480                 adev->mode_info.num_crtc = 6;
2481                 adev->mode_info.num_hpd = 6;
2482                 adev->mode_info.num_dig = 6;
2483                 break;
2484         case CHIP_KAVERI:
2485                 adev->mode_info.num_crtc = 4;
2486                 adev->mode_info.num_hpd = 6;
2487                 adev->mode_info.num_dig = 7;
2488                 break;
2489         case CHIP_KABINI:
2490         case CHIP_MULLINS:
2491                 adev->mode_info.num_crtc = 2;
2492                 adev->mode_info.num_hpd = 6;
2493                 adev->mode_info.num_dig = 6;
2494                 break;
2495         case CHIP_FIJI:
2496         case CHIP_TONGA:
2497                 adev->mode_info.num_crtc = 6;
2498                 adev->mode_info.num_hpd = 6;
2499                 adev->mode_info.num_dig = 7;
2500                 break;
2501         case CHIP_CARRIZO:
2502                 adev->mode_info.num_crtc = 3;
2503                 adev->mode_info.num_hpd = 6;
2504                 adev->mode_info.num_dig = 9;
2505                 break;
2506         case CHIP_STONEY:
2507                 adev->mode_info.num_crtc = 2;
2508                 adev->mode_info.num_hpd = 6;
2509                 adev->mode_info.num_dig = 9;
2510                 break;
2511         case CHIP_POLARIS11:
2512         case CHIP_POLARIS12:
2513                 adev->mode_info.num_crtc = 5;
2514                 adev->mode_info.num_hpd = 5;
2515                 adev->mode_info.num_dig = 5;
2516                 break;
2517         case CHIP_POLARIS10:
2518         case CHIP_VEGAM:
2519                 adev->mode_info.num_crtc = 6;
2520                 adev->mode_info.num_hpd = 6;
2521                 adev->mode_info.num_dig = 6;
2522                 break;
2523         case CHIP_VEGA10:
2524         case CHIP_VEGA12:
2525         case CHIP_VEGA20:
2526                 adev->mode_info.num_crtc = 6;
2527                 adev->mode_info.num_hpd = 6;
2528                 adev->mode_info.num_dig = 6;
2529                 break;
2530 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2531         case CHIP_RAVEN:
2532                 adev->mode_info.num_crtc = 4;
2533                 adev->mode_info.num_hpd = 4;
2534                 adev->mode_info.num_dig = 4;
2535                 break;
2536 #endif
2537 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2538         case CHIP_NAVI10:
2539         case CHIP_NAVI12:
2540                 adev->mode_info.num_crtc = 6;
2541                 adev->mode_info.num_hpd = 6;
2542                 adev->mode_info.num_dig = 6;
2543                 break;
2544         case CHIP_NAVI14:
2545                 adev->mode_info.num_crtc = 5;
2546                 adev->mode_info.num_hpd = 5;
2547                 adev->mode_info.num_dig = 5;
2548                 break;
2549 #endif
2550 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2551         case CHIP_RENOIR:
2552                 adev->mode_info.num_crtc = 4;
2553                 adev->mode_info.num_hpd = 4;
2554                 adev->mode_info.num_dig = 4;
2555                 break;
2556 #endif
2557         default:
2558                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2559                 return -EINVAL;
2560         }
2561 
2562         amdgpu_dm_set_irq_funcs(adev);
2563 
2564         if (adev->mode_info.funcs == NULL)
2565                 adev->mode_info.funcs = &dm_display_funcs;
2566 
2567         /*
2568          * Note: Do NOT change adev->audio_endpt_rreg and
2569          * adev->audio_endpt_wreg because they are initialised in
2570          * amdgpu_device_init()
2571          */
2572 #if defined(CONFIG_DEBUG_KERNEL_DC)
2573         device_create_file(
2574                 adev->ddev->dev,
2575                 &dev_attr_s3_debug);
2576 #endif
2577 
2578         return 0;
2579 }
2580 
2581 static bool modeset_required(struct drm_crtc_state *crtc_state,
2582                              struct dc_stream_state *new_stream,
2583                              struct dc_stream_state *old_stream)
2584 {
2585         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2586                 return false;
2587 
2588         if (!crtc_state->enable)
2589                 return false;
2590 
2591         return crtc_state->active;
2592 }
2593 
2594 static bool modereset_required(struct drm_crtc_state *crtc_state)
2595 {
2596         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2597                 return false;
2598 
2599         return !crtc_state->enable || !crtc_state->active;
2600 }
2601 
2602 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2603 {
2604         drm_encoder_cleanup(encoder);
2605         kfree(encoder);
2606 }
2607 
2608 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2609         .destroy = amdgpu_dm_encoder_destroy,
2610 };
2611 
2612 
2613 static int fill_dc_scaling_info(const struct drm_plane_state *state,
2614                                 struct dc_scaling_info *scaling_info)
2615 {
2616         int scale_w, scale_h;
2617 
2618         memset(scaling_info, 0, sizeof(*scaling_info));
2619 
2620         /* Source is fixed 16.16 but we ignore mantissa for now... */
2621         scaling_info->src_rect.x = state->src_x >> 16;
2622         scaling_info->src_rect.y = state->src_y >> 16;
2623 
2624         scaling_info->src_rect.width = state->src_w >> 16;
2625         if (scaling_info->src_rect.width == 0)
2626                 return -EINVAL;
2627 
2628         scaling_info->src_rect.height = state->src_h >> 16;
2629         if (scaling_info->src_rect.height == 0)
2630                 return -EINVAL;
2631 
2632         scaling_info->dst_rect.x = state->crtc_x;
2633         scaling_info->dst_rect.y = state->crtc_y;
2634 
2635         if (state->crtc_w == 0)
2636                 return -EINVAL;
2637 
2638         scaling_info->dst_rect.width = state->crtc_w;
2639 
2640         if (state->crtc_h == 0)
2641                 return -EINVAL;
2642 
2643         scaling_info->dst_rect.height = state->crtc_h;
2644 
2645         /* DRM doesn't specify clipping on destination output. */
2646         scaling_info->clip_rect = scaling_info->dst_rect;
2647 
2648         /* TODO: Validate scaling per-format with DC plane caps */
2649         scale_w = scaling_info->dst_rect.width * 1000 /
2650                   scaling_info->src_rect.width;
2651 
2652         if (scale_w < 250 || scale_w > 16000)
2653                 return -EINVAL;
2654 
2655         scale_h = scaling_info->dst_rect.height * 1000 /
2656                   scaling_info->src_rect.height;
2657 
2658         if (scale_h < 250 || scale_h > 16000)
2659                 return -EINVAL;
2660 
2661         /*
2662          * The "scaling_quality" can be ignored for now, quality = 0 has DC
2663          * assume reasonable defaults based on the format.
2664          */
2665 
2666         return 0;
2667 }
2668 
2669 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2670                        uint64_t *tiling_flags)
2671 {
2672         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2673         int r = amdgpu_bo_reserve(rbo, false);
2674 
2675         if (unlikely(r)) {
2676                 /* Don't show error message when returning -ERESTARTSYS */
2677                 if (r != -ERESTARTSYS)
2678                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
2679                 return r;
2680         }
2681 
2682         if (tiling_flags)
2683                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2684 
2685         amdgpu_bo_unreserve(rbo);
2686 
2687         return r;
2688 }
2689 
2690 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2691 {
2692         uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2693 
2694         return offset ? (address + offset * 256) : 0;
2695 }
2696 
2697 static int
2698 fill_plane_dcc_attributes(struct amdgpu_device *adev,
2699                           const struct amdgpu_framebuffer *afb,
2700                           const enum surface_pixel_format format,
2701                           const enum dc_rotation_angle rotation,
2702                           const struct plane_size *plane_size,
2703                           const union dc_tiling_info *tiling_info,
2704                           const uint64_t info,
2705                           struct dc_plane_dcc_param *dcc,
2706                           struct dc_plane_address *address,
2707                           bool force_disable_dcc)
2708 {
2709         struct dc *dc = adev->dm.dc;
2710         struct dc_dcc_surface_param input;
2711         struct dc_surface_dcc_cap output;
2712         uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2713         uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2714         uint64_t dcc_address;
2715 
2716         memset(&input, 0, sizeof(input));
2717         memset(&output, 0, sizeof(output));
2718 
2719         if (force_disable_dcc)
2720                 return 0;
2721 
2722         if (!offset)
2723                 return 0;
2724 
2725         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2726                 return 0;
2727 
2728         if (!dc->cap_funcs.get_dcc_compression_cap)
2729                 return -EINVAL;
2730 
2731         input.format = format;
2732         input.surface_size.width = plane_size->surface_size.width;
2733         input.surface_size.height = plane_size->surface_size.height;
2734         input.swizzle_mode = tiling_info->gfx9.swizzle;
2735 
2736         if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
2737                 input.scan = SCAN_DIRECTION_HORIZONTAL;
2738         else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
2739                 input.scan = SCAN_DIRECTION_VERTICAL;
2740 
2741         if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2742                 return -EINVAL;
2743 
2744         if (!output.capable)
2745                 return -EINVAL;
2746 
2747         if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2748                 return -EINVAL;
2749 
2750         dcc->enable = 1;
2751         dcc->meta_pitch =
2752                 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2753         dcc->independent_64b_blks = i64b;
2754 
2755         dcc_address = get_dcc_address(afb->address, info);
2756         address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2757         address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
2758 
2759         return 0;
2760 }
2761 
2762 static int
2763 fill_plane_buffer_attributes(struct amdgpu_device *adev,
2764                              const struct amdgpu_framebuffer *afb,
2765                              const enum surface_pixel_format format,
2766                              const enum dc_rotation_angle rotation,
2767                              const uint64_t tiling_flags,
2768                              union dc_tiling_info *tiling_info,
2769                              struct plane_size *plane_size,
2770                              struct dc_plane_dcc_param *dcc,
2771                              struct dc_plane_address *address,
2772                              bool force_disable_dcc)
2773 {
2774         const struct drm_framebuffer *fb = &afb->base;
2775         int ret;
2776 
2777         memset(tiling_info, 0, sizeof(*tiling_info));
2778         memset(plane_size, 0, sizeof(*plane_size));
2779         memset(dcc, 0, sizeof(*dcc));
2780         memset(address, 0, sizeof(*address));
2781 
2782         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2783                 plane_size->surface_size.x = 0;
2784                 plane_size->surface_size.y = 0;
2785                 plane_size->surface_size.width = fb->width;
2786                 plane_size->surface_size.height = fb->height;
2787                 plane_size->surface_pitch =
2788                         fb->pitches[0] / fb->format->cpp[0];
2789 
2790                 address->type = PLN_ADDR_TYPE_GRAPHICS;
2791                 address->grph.addr.low_part = lower_32_bits(afb->address);
2792                 address->grph.addr.high_part = upper_32_bits(afb->address);
2793         } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
2794                 uint64_t chroma_addr = afb->address + fb->offsets[1];
2795 
2796                 plane_size->surface_size.x = 0;
2797                 plane_size->surface_size.y = 0;
2798                 plane_size->surface_size.width = fb->width;
2799                 plane_size->surface_size.height = fb->height;
2800                 plane_size->surface_pitch =
2801                         fb->pitches[0] / fb->format->cpp[0];
2802 
2803                 plane_size->chroma_size.x = 0;
2804                 plane_size->chroma_size.y = 0;
2805                 /* TODO: set these based on surface format */
2806                 plane_size->chroma_size.width = fb->width / 2;
2807                 plane_size->chroma_size.height = fb->height / 2;
2808 
2809                 plane_size->chroma_pitch =
2810                         fb->pitches[1] / fb->format->cpp[1];
2811 
2812                 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2813                 address->video_progressive.luma_addr.low_part =
2814                         lower_32_bits(afb->address);
2815                 address->video_progressive.luma_addr.high_part =
2816                         upper_32_bits(afb->address);
2817                 address->video_progressive.chroma_addr.low_part =
2818                         lower_32_bits(chroma_addr);
2819                 address->video_progressive.chroma_addr.high_part =
2820                         upper_32_bits(chroma_addr);
2821         }
2822 
2823         /* Fill GFX8 params */
2824         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2825                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2826 
2827                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2828                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2829                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2830                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2831                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2832 
2833                 /* XXX fix me for VI */
2834                 tiling_info->gfx8.num_banks = num_banks;
2835                 tiling_info->gfx8.array_mode =
2836                                 DC_ARRAY_2D_TILED_THIN1;
2837                 tiling_info->gfx8.tile_split = tile_split;
2838                 tiling_info->gfx8.bank_width = bankw;
2839                 tiling_info->gfx8.bank_height = bankh;
2840                 tiling_info->gfx8.tile_aspect = mtaspect;
2841                 tiling_info->gfx8.tile_mode =
2842                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2843         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2844                         == DC_ARRAY_1D_TILED_THIN1) {
2845                 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2846         }
2847 
2848         tiling_info->gfx8.pipe_config =
2849                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2850 
2851         if (adev->asic_type == CHIP_VEGA10 ||
2852             adev->asic_type == CHIP_VEGA12 ||
2853             adev->asic_type == CHIP_VEGA20 ||
2854 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2855             adev->asic_type == CHIP_NAVI10 ||
2856             adev->asic_type == CHIP_NAVI14 ||
2857             adev->asic_type == CHIP_NAVI12 ||
2858 #endif
2859 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2860             adev->asic_type == CHIP_RENOIR ||
2861 #endif
2862             adev->asic_type == CHIP_RAVEN) {
2863                 /* Fill GFX9 params */
2864                 tiling_info->gfx9.num_pipes =
2865                         adev->gfx.config.gb_addr_config_fields.num_pipes;
2866                 tiling_info->gfx9.num_banks =
2867                         adev->gfx.config.gb_addr_config_fields.num_banks;
2868                 tiling_info->gfx9.pipe_interleave =
2869                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2870                 tiling_info->gfx9.num_shader_engines =
2871                         adev->gfx.config.gb_addr_config_fields.num_se;
2872                 tiling_info->gfx9.max_compressed_frags =
2873                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2874                 tiling_info->gfx9.num_rb_per_se =
2875                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2876                 tiling_info->gfx9.swizzle =
2877                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2878                 tiling_info->gfx9.shaderEnable = 1;
2879 
2880                 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2881                                                 plane_size, tiling_info,
2882                                                 tiling_flags, dcc, address,
2883                                                 force_disable_dcc);
2884                 if (ret)
2885                         return ret;
2886         }
2887 
2888         return 0;
2889 }
2890 
2891 static void
2892 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
2893                                bool *per_pixel_alpha, bool *global_alpha,
2894                                int *global_alpha_value)
2895 {
2896         *per_pixel_alpha = false;
2897         *global_alpha = false;
2898         *global_alpha_value = 0xff;
2899 
2900         if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2901                 return;
2902 
2903         if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2904                 static const uint32_t alpha_formats[] = {
2905                         DRM_FORMAT_ARGB8888,
2906                         DRM_FORMAT_RGBA8888,
2907                         DRM_FORMAT_ABGR8888,
2908                 };
2909                 uint32_t format = plane_state->fb->format->format;
2910                 unsigned int i;
2911 
2912                 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2913                         if (format == alpha_formats[i]) {
2914                                 *per_pixel_alpha = true;
2915                                 break;
2916                         }
2917                 }
2918         }
2919 
2920         if (plane_state->alpha < 0xffff) {
2921                 *global_alpha = true;
2922                 *global_alpha_value = plane_state->alpha >> 8;
2923         }
2924 }
2925 
2926 static int
2927 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
2928                             const enum surface_pixel_format format,
2929                             enum dc_color_space *color_space)
2930 {
2931         bool full_range;
2932 
2933         *color_space = COLOR_SPACE_SRGB;
2934 
2935         /* DRM color properties only affect non-RGB formats. */
2936         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2937                 return 0;
2938 
2939         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2940 
2941         switch (plane_state->color_encoding) {
2942         case DRM_COLOR_YCBCR_BT601:
2943                 if (full_range)
2944                         *color_space = COLOR_SPACE_YCBCR601;
2945                 else
2946                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2947                 break;
2948 
2949         case DRM_COLOR_YCBCR_BT709:
2950                 if (full_range)
2951                         *color_space = COLOR_SPACE_YCBCR709;
2952                 else
2953                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2954                 break;
2955 
2956         case DRM_COLOR_YCBCR_BT2020:
2957                 if (full_range)
2958                         *color_space = COLOR_SPACE_2020_YCBCR;
2959                 else
2960                         return -EINVAL;
2961                 break;
2962 
2963         default:
2964                 return -EINVAL;
2965         }
2966 
2967         return 0;
2968 }
2969 
2970 static int
2971 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
2972                             const struct drm_plane_state *plane_state,
2973                             const uint64_t tiling_flags,
2974                             struct dc_plane_info *plane_info,
2975                             struct dc_plane_address *address,
2976                             bool force_disable_dcc)
2977 {
2978         const struct drm_framebuffer *fb = plane_state->fb;
2979         const struct amdgpu_framebuffer *afb =
2980                 to_amdgpu_framebuffer(plane_state->fb);
2981         struct drm_format_name_buf format_name;
2982         int ret;
2983 
2984         memset(plane_info, 0, sizeof(*plane_info));
2985 
2986         switch (fb->format->format) {
2987         case DRM_FORMAT_C8:
2988                 plane_info->format =
2989                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2990                 break;
2991         case DRM_FORMAT_RGB565:
2992                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2993                 break;
2994         case DRM_FORMAT_XRGB8888:
2995         case DRM_FORMAT_ARGB8888:
2996                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2997                 break;
2998         case DRM_FORMAT_XRGB2101010:
2999         case DRM_FORMAT_ARGB2101010:
3000                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
3001                 break;
3002         case DRM_FORMAT_XBGR2101010:
3003         case DRM_FORMAT_ABGR2101010:
3004                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
3005                 break;
3006         case DRM_FORMAT_XBGR8888:
3007         case DRM_FORMAT_ABGR8888:
3008                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
3009                 break;
3010         case DRM_FORMAT_NV21:
3011                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
3012                 break;
3013         case DRM_FORMAT_NV12:
3014                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
3015                 break;
3016         default:
3017                 DRM_ERROR(
3018                         "Unsupported screen format %s\n",
3019                         drm_get_format_name(fb->format->format, &format_name));
3020                 return -EINVAL;
3021         }
3022 
3023         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3024         case DRM_MODE_ROTATE_0:
3025                 plane_info->rotation = ROTATION_ANGLE_0;
3026                 break;
3027         case DRM_MODE_ROTATE_90:
3028                 plane_info->rotation = ROTATION_ANGLE_90;
3029                 break;
3030         case DRM_MODE_ROTATE_180:
3031                 plane_info->rotation = ROTATION_ANGLE_180;
3032                 break;
3033         case DRM_MODE_ROTATE_270:
3034                 plane_info->rotation = ROTATION_ANGLE_270;
3035                 break;
3036         default:
3037                 plane_info->rotation = ROTATION_ANGLE_0;
3038                 break;
3039         }
3040 
3041         plane_info->visible = true;
3042         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3043 
3044         plane_info->layer_index = 0;
3045 
3046         ret = fill_plane_color_attributes(plane_state, plane_info->format,
3047                                           &plane_info->color_space);
3048         if (ret)
3049                 return ret;
3050 
3051         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3052                                            plane_info->rotation, tiling_flags,
3053                                            &plane_info->tiling_info,
3054                                            &plane_info->plane_size,
3055                                            &plane_info->dcc, address,
3056                                            force_disable_dcc);
3057         if (ret)
3058                 return ret;
3059 
3060         fill_blending_from_plane_state(
3061                 plane_state, &plane_info->per_pixel_alpha,
3062                 &plane_info->global_alpha, &plane_info->global_alpha_value);
3063 
3064         return 0;
3065 }
3066 
3067 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3068                                     struct dc_plane_state *dc_plane_state,
3069                                     struct drm_plane_state *plane_state,
3070                                     struct drm_crtc_state *crtc_state)
3071 {
3072         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
3073         const struct amdgpu_framebuffer *amdgpu_fb =
3074                 to_amdgpu_framebuffer(plane_state->fb);
3075         struct dc_scaling_info scaling_info;
3076         struct dc_plane_info plane_info;
3077         uint64_t tiling_flags;
3078         int ret;
3079         bool force_disable_dcc = false;
3080 
3081         ret = fill_dc_scaling_info(plane_state, &scaling_info);
3082         if (ret)
3083                 return ret;
3084 
3085         dc_plane_state->src_rect = scaling_info.src_rect;
3086         dc_plane_state->dst_rect = scaling_info.dst_rect;
3087         dc_plane_state->clip_rect = scaling_info.clip_rect;
3088         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
3089 
3090         ret = get_fb_info(amdgpu_fb, &tiling_flags);
3091         if (ret)
3092                 return ret;
3093 
3094         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
3095         ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3096                                           &plane_info,
3097                                           &dc_plane_state->address,
3098                                           force_disable_dcc);
3099         if (ret)
3100                 return ret;
3101 
3102         dc_plane_state->format = plane_info.format;
3103         dc_plane_state->color_space = plane_info.color_space;
3104         dc_plane_state->format = plane_info.format;
3105         dc_plane_state->plane_size = plane_info.plane_size;
3106         dc_plane_state->rotation = plane_info.rotation;
3107         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3108         dc_plane_state->stereo_format = plane_info.stereo_format;
3109         dc_plane_state->tiling_info = plane_info.tiling_info;
3110         dc_plane_state->visible = plane_info.visible;
3111         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3112         dc_plane_state->global_alpha = plane_info.global_alpha;
3113         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3114         dc_plane_state->dcc = plane_info.dcc;
3115         dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
3116 
3117         /*
3118          * Always set input transfer function, since plane state is refreshed
3119          * every time.
3120          */
3121         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3122         if (ret)
3123                 return ret;
3124 
3125         return 0;
3126 }
3127 
3128 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3129                                            const struct dm_connector_state *dm_state,
3130                                            struct dc_stream_state *stream)
3131 {
3132         enum amdgpu_rmx_type rmx_type;
3133 
3134         struct rect src = { 0 }; /* viewport in composition space*/
3135         struct rect dst = { 0 }; /* stream addressable area */
3136 
3137         /* no mode. nothing to be done */
3138         if (!mode)
3139                 return;
3140 
3141         /* Full screen scaling by default */
3142         src.width = mode->hdisplay;
3143         src.height = mode->vdisplay;
3144         dst.width = stream->timing.h_addressable;
3145         dst.height = stream->timing.v_addressable;
3146 
3147         if (dm_state) {
3148                 rmx_type = dm_state->scaling;
3149                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3150                         if (src.width * dst.height <
3151                                         src.height * dst.width) {
3152                                 /* height needs less upscaling/more downscaling */
3153                                 dst.width = src.width *
3154                                                 dst.height / src.height;
3155                         } else {
3156                                 /* width needs less upscaling/more downscaling */
3157                                 dst.height = src.height *
3158                                                 dst.width / src.width;
3159                         }
3160                 } else if (rmx_type == RMX_CENTER) {
3161                         dst = src;
3162                 }
3163 
3164                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3165                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
3166 
3167                 if (dm_state->underscan_enable) {
3168                         dst.x += dm_state->underscan_hborder / 2;
3169                         dst.y += dm_state->underscan_vborder / 2;
3170                         dst.width -= dm_state->underscan_hborder;
3171                         dst.height -= dm_state->underscan_vborder;
3172                 }
3173         }
3174 
3175         stream->src = src;
3176         stream->dst = dst;
3177 
3178         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
3179                         dst.x, dst.y, dst.width, dst.height);
3180 
3181 }
3182 
3183 static enum dc_color_depth
3184 convert_color_depth_from_display_info(const struct drm_connector *connector,
3185                                       const struct drm_connector_state *state)
3186 {
3187         uint8_t bpc = (uint8_t)connector->display_info.bpc;
3188 
3189         /* Assume 8 bpc by default if no bpc is specified. */
3190         bpc = bpc ? bpc : 8;
3191 
3192         if (!state)
3193                 state = connector->state;
3194 
3195         if (state) {
3196                 /*
3197                  * Cap display bpc based on the user requested value.
3198                  *
3199                  * The value for state->max_bpc may not correctly updated
3200                  * depending on when the connector gets added to the state
3201                  * or if this was called outside of atomic check, so it
3202                  * can't be used directly.
3203                  */
3204                 bpc = min(bpc, state->max_requested_bpc);
3205 
3206                 /* Round down to the nearest even number. */
3207                 bpc = bpc - (bpc & 1);
3208         }
3209 
3210         switch (bpc) {
3211         case 0:
3212                 /*
3213                  * Temporary Work around, DRM doesn't parse color depth for
3214                  * EDID revision before 1.4
3215                  * TODO: Fix edid parsing
3216                  */
3217                 return COLOR_DEPTH_888;
3218         case 6:
3219                 return COLOR_DEPTH_666;
3220         case 8:
3221                 return COLOR_DEPTH_888;
3222         case 10:
3223                 return COLOR_DEPTH_101010;
3224         case 12:
3225                 return COLOR_DEPTH_121212;
3226         case 14:
3227                 return COLOR_DEPTH_141414;
3228         case 16:
3229                 return COLOR_DEPTH_161616;
3230         default:
3231                 return COLOR_DEPTH_UNDEFINED;
3232         }
3233 }
3234 
3235 static enum dc_aspect_ratio
3236 get_aspect_ratio(const struct drm_display_mode *mode_in)
3237 {
3238         /* 1-1 mapping, since both enums follow the HDMI spec. */
3239         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3240 }
3241 
3242 static enum dc_color_space
3243 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3244 {
3245         enum dc_color_space color_space = COLOR_SPACE_SRGB;
3246 
3247         switch (dc_crtc_timing->pixel_encoding) {
3248         case PIXEL_ENCODING_YCBCR422:
3249         case PIXEL_ENCODING_YCBCR444:
3250         case PIXEL_ENCODING_YCBCR420:
3251         {
3252                 /*
3253                  * 27030khz is the separation point between HDTV and SDTV
3254                  * according to HDMI spec, we use YCbCr709 and YCbCr601
3255                  * respectively
3256                  */
3257                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
3258                         if (dc_crtc_timing->flags.Y_ONLY)
3259                                 color_space =
3260                                         COLOR_SPACE_YCBCR709_LIMITED;
3261                         else
3262                                 color_space = COLOR_SPACE_YCBCR709;
3263                 } else {
3264                         if (dc_crtc_timing->flags.Y_ONLY)
3265                                 color_space =
3266                                         COLOR_SPACE_YCBCR601_LIMITED;
3267                         else
3268                                 color_space = COLOR_SPACE_YCBCR601;
3269                 }
3270 
3271         }
3272         break;
3273         case PIXEL_ENCODING_RGB:
3274                 color_space = COLOR_SPACE_SRGB;
3275                 break;
3276 
3277         default:
3278                 WARN_ON(1);
3279                 break;
3280         }
3281 
3282         return color_space;
3283 }
3284 
3285 static bool adjust_colour_depth_from_display_info(
3286         struct dc_crtc_timing *timing_out,
3287         const struct drm_display_info *info)
3288 {
3289         enum dc_color_depth depth = timing_out->display_color_depth;
3290         int normalized_clk;
3291         do {
3292                 normalized_clk = timing_out->pix_clk_100hz / 10;
3293                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3294                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3295                         normalized_clk /= 2;
3296                 /* Adjusting pix clock following on HDMI spec based on colour depth */
3297                 switch (depth) {
3298                 case COLOR_DEPTH_888:
3299                         break;
3300                 case COLOR_DEPTH_101010:
3301                         normalized_clk = (normalized_clk * 30) / 24;
3302                         break;
3303                 case COLOR_DEPTH_121212:
3304                         normalized_clk = (normalized_clk * 36) / 24;
3305                         break;
3306                 case COLOR_DEPTH_161616:
3307                         normalized_clk = (normalized_clk * 48) / 24;
3308                         break;
3309                 default:
3310                         /* The above depths are the only ones valid for HDMI. */
3311                         return false;
3312                 }
3313                 if (normalized_clk <= info->max_tmds_clock) {
3314                         timing_out->display_color_depth = depth;
3315                         return true;
3316                 }
3317         } while (--depth > COLOR_DEPTH_666);
3318         return false;
3319 }
3320 
3321 static void fill_stream_properties_from_drm_display_mode(
3322         struct dc_stream_state *stream,
3323         const struct drm_display_mode *mode_in,
3324         const struct drm_connector *connector,
3325         const struct drm_connector_state *connector_state,
3326         const struct dc_stream_state *old_stream)
3327 {
3328         struct dc_crtc_timing *timing_out = &stream->timing;
3329         const struct drm_display_info *info = &connector->display_info;
3330 
3331         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3332 
3333         timing_out->h_border_left = 0;
3334         timing_out->h_border_right = 0;
3335         timing_out->v_border_top = 0;
3336         timing_out->v_border_bottom = 0;
3337         /* TODO: un-hardcode */
3338         if (drm_mode_is_420_only(info, mode_in)
3339                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3340                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3341         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3342                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3343                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3344         else
3345                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3346 
3347         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3348         timing_out->display_color_depth = convert_color_depth_from_display_info(
3349                 connector, connector_state);
3350         timing_out->scan_type = SCANNING_TYPE_NODATA;
3351         timing_out->hdmi_vic = 0;
3352 
3353         if(old_stream) {
3354                 timing_out->vic = old_stream->timing.vic;
3355                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3356                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3357         } else {
3358                 timing_out->vic = drm_match_cea_mode(mode_in);
3359                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3360                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3361                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3362                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3363         }
3364 
3365         timing_out->h_addressable = mode_in->crtc_hdisplay;
3366         timing_out->h_total = mode_in->crtc_htotal;
3367         timing_out->h_sync_width =
3368                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3369         timing_out->h_front_porch =
3370                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3371         timing_out->v_total = mode_in->crtc_vtotal;
3372         timing_out->v_addressable = mode_in->crtc_vdisplay;
3373         timing_out->v_front_porch =
3374                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3375         timing_out->v_sync_width =
3376                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3377         timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3378         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3379 
3380         stream->output_color_space = get_output_color_space(timing_out);
3381 
3382         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3383         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3384         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3385                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
3386                     drm_mode_is_420_also(info, mode_in) &&
3387                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
3388                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3389                         adjust_colour_depth_from_display_info(timing_out, info);
3390                 }
3391         }
3392 }
3393 
3394 static void fill_audio_info(struct audio_info *audio_info,
3395                             const struct drm_connector *drm_connector,
3396                             const struct dc_sink *dc_sink)
3397 {
3398         int i = 0;
3399         int cea_revision = 0;
3400         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3401 
3402         audio_info->manufacture_id = edid_caps->manufacturer_id;
3403         audio_info->product_id = edid_caps->product_id;
3404 
3405         cea_revision = drm_connector->display_info.cea_rev;
3406 
3407         strscpy(audio_info->display_name,
3408                 edid_caps->display_name,
3409                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3410 
3411         if (cea_revision >= 3) {
3412                 audio_info->mode_count = edid_caps->audio_mode_count;
3413 
3414                 for (i = 0; i < audio_info->mode_count; ++i) {
3415                         audio_info->modes[i].format_code =
3416                                         (enum audio_format_code)
3417                                         (edid_caps->audio_modes[i].format_code);
3418                         audio_info->modes[i].channel_count =
3419                                         edid_caps->audio_modes[i].channel_count;
3420                         audio_info->modes[i].sample_rates.all =
3421                                         edid_caps->audio_modes[i].sample_rate;
3422                         audio_info->modes[i].sample_size =
3423                                         edid_caps->audio_modes[i].sample_size;
3424                 }
3425         }
3426 
3427         audio_info->flags.all = edid_caps->speaker_flags;
3428 
3429         /* TODO: We only check for the progressive mode, check for interlace mode too */
3430         if (drm_connector->latency_present[0]) {
3431                 audio_info->video_latency = drm_connector->video_latency[0];
3432                 audio_info->audio_latency = drm_connector->audio_latency[0];
3433         }
3434 
3435         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3436 
3437 }
3438 
3439 static void
3440 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3441                                       struct drm_display_mode *dst_mode)
3442 {
3443         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3444         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3445         dst_mode->crtc_clock = src_mode->crtc_clock;
3446         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3447         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3448         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
3449         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3450         dst_mode->crtc_htotal = src_mode->crtc_htotal;
3451         dst_mode->crtc_hskew = src_mode->crtc_hskew;
3452         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3453         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3454         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3455         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3456         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3457 }
3458 
3459 static void
3460 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3461                                         const struct drm_display_mode *native_mode,
3462                                         bool scale_enabled)
3463 {
3464         if (scale_enabled) {
3465                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3466         } else if (native_mode->clock == drm_mode->clock &&
3467                         native_mode->htotal == drm_mode->htotal &&
3468                         native_mode->vtotal == drm_mode->vtotal) {
3469                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3470         } else {
3471                 /* no scaling nor amdgpu inserted, no need to patch */
3472         }
3473 }
3474 
3475 static struct dc_sink *
3476 create_fake_sink(struct amdgpu_dm_connector *aconnector)
3477 {
3478         struct dc_sink_init_data sink_init_data = { 0 };
3479         struct dc_sink *sink = NULL;
3480         sink_init_data.link = aconnector->dc_link;
3481         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3482 
3483         sink = dc_sink_create(&sink_init_data);
3484         if (!sink) {
3485                 DRM_ERROR("Failed to create sink!\n");
3486                 return NULL;
3487         }
3488         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3489 
3490         return sink;
3491 }
3492 
3493 static void set_multisync_trigger_params(
3494                 struct dc_stream_state *stream)
3495 {
3496         if (stream->triggered_crtc_reset.enabled) {
3497                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3498                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3499         }
3500 }
3501 
3502 static void set_master_stream(struct dc_stream_state *stream_set[],
3503                               int stream_count)
3504 {
3505         int j, highest_rfr = 0, master_stream = 0;
3506 
3507         for (j = 0;  j < stream_count; j++) {
3508                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3509                         int refresh_rate = 0;
3510 
3511                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3512                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3513                         if (refresh_rate > highest_rfr) {
3514                                 highest_rfr = refresh_rate;
3515                                 master_stream = j;
3516                         }
3517                 }
3518         }
3519         for (j = 0;  j < stream_count; j++) {
3520                 if (stream_set[j])
3521                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3522         }
3523 }
3524 
3525 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3526 {
3527         int i = 0;
3528 
3529         if (context->stream_count < 2)
3530                 return;
3531         for (i = 0; i < context->stream_count ; i++) {
3532                 if (!context->streams[i])
3533                         continue;
3534                 /*
3535                  * TODO: add a function to read AMD VSDB bits and set
3536                  * crtc_sync_master.multi_sync_enabled flag
3537                  * For now it's set to false
3538                  */
3539                 set_multisync_trigger_params(context->streams[i]);
3540         }
3541         set_master_stream(context->streams, context->stream_count);
3542 }
3543 
3544 static struct dc_stream_state *
3545 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3546                        const struct drm_display_mode *drm_mode,
3547                        const struct dm_connector_state *dm_state,
3548                        const struct dc_stream_state *old_stream)
3549 {
3550         struct drm_display_mode *preferred_mode = NULL;
3551         struct drm_connector *drm_connector;
3552         const struct drm_connector_state *con_state =
3553                 dm_state ? &dm_state->base : NULL;
3554         struct dc_stream_state *stream = NULL;
3555         struct drm_display_mode mode = *drm_mode;
3556         bool native_mode_found = false;
3557         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3558         int mode_refresh;
3559         int preferred_refresh = 0;
3560 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3561         struct dsc_dec_dpcd_caps dsc_caps;
3562         uint32_t link_bandwidth_kbps;
3563 #endif
3564 
3565         struct dc_sink *sink = NULL;
3566         if (aconnector == NULL) {
3567                 DRM_ERROR("aconnector is NULL!\n");
3568                 return stream;
3569         }
3570 
3571         drm_connector = &aconnector->base;
3572 
3573         if (!aconnector->dc_sink) {
3574                 sink = create_fake_sink(aconnector);
3575                 if (!sink)
3576                         return stream;
3577         } else {
3578                 sink = aconnector->dc_sink;
3579                 dc_sink_retain(sink);
3580         }
3581 
3582         stream = dc_create_stream_for_sink(sink);
3583 
3584         if (stream == NULL) {
3585                 DRM_ERROR("Failed to create stream for sink!\n");
3586                 goto finish;
3587         }
3588 
3589         stream->dm_stream_context = aconnector;
3590 
3591         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3592                 /* Search for preferred mode */
3593                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3594                         native_mode_found = true;
3595                         break;
3596                 }
3597         }
3598         if (!native_mode_found)
3599                 preferred_mode = list_first_entry_or_null(
3600                                 &aconnector->base.modes,
3601                                 struct drm_display_mode,
3602                                 head);
3603 
3604         mode_refresh = drm_mode_vrefresh(&mode);
3605 
3606         if (preferred_mode == NULL) {
3607                 /*
3608                  * This may not be an error, the use case is when we have no
3609                  * usermode calls to reset and set mode upon hotplug. In this
3610                  * case, we call set mode ourselves to restore the previous mode
3611                  * and the modelist may not be filled in in time.
3612                  */
3613                 DRM_DEBUG_DRIVER("No preferred mode found\n");
3614         } else {
3615                 decide_crtc_timing_for_drm_display_mode(
3616                                 &mode, preferred_mode,
3617                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
3618                 preferred_refresh = drm_mode_vrefresh(preferred_mode);
3619         }
3620 
3621         if (!dm_state)
3622                 drm_mode_set_crtcinfo(&mode, 0);
3623 
3624         /*
3625         * If scaling is enabled and refresh rate didn't change
3626         * we copy the vic and polarities of the old timings
3627         */
3628         if (!scale || mode_refresh != preferred_refresh)
3629                 fill_stream_properties_from_drm_display_mode(stream,
3630                         &mode, &aconnector->base, con_state, NULL);
3631         else
3632                 fill_stream_properties_from_drm_display_mode(stream,
3633                         &mode, &aconnector->base, con_state, old_stream);
3634 
3635 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3636         stream->timing.flags.DSC = 0;
3637 
3638         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3639                 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3640                                       aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3641                                       &dsc_caps);
3642                 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
3643                                                              dc_link_get_link_cap(aconnector->dc_link));
3644 
3645                 if (dsc_caps.is_dsc_supported)
3646                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
3647                                                   &dsc_caps,
3648                                                   link_bandwidth_kbps,
3649                                                   &stream->timing,
3650                                                   &stream->timing.dsc_cfg))
3651                                 stream->timing.flags.DSC = 1;
3652         }
3653 #endif
3654 
3655         update_stream_scaling_settings(&mode, dm_state, stream);
3656 
3657         fill_audio_info(
3658                 &stream->audio_info,
3659                 drm_connector,
3660                 sink);
3661 
3662         update_stream_signal(stream, sink);
3663 
3664 finish:
3665         dc_sink_release(sink);
3666 
3667         return stream;
3668 }
3669 
3670 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3671 {
3672         drm_crtc_cleanup(crtc);
3673         kfree(crtc);
3674 }
3675 
3676 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3677                                   struct drm_crtc_state *state)
3678 {
3679         struct dm_crtc_state *cur = to_dm_crtc_state(state);
3680 
3681         /* TODO Destroy dc_stream objects are stream object is flattened */
3682         if (cur->stream)
3683                 dc_stream_release(cur->stream);
3684 
3685 
3686         __drm_atomic_helper_crtc_destroy_state(state);
3687 
3688 
3689         kfree(state);
3690 }
3691 
3692 static void dm_crtc_reset_state(struct drm_crtc *crtc)
3693 {
3694         struct dm_crtc_state *state;
3695 
3696         if (crtc->state)
3697                 dm_crtc_destroy_state(crtc, crtc->state);
3698 
3699         state = kzalloc(sizeof(*state), GFP_KERNEL);
3700         if (WARN_ON(!state))
3701                 return;
3702 
3703         crtc->state = &state->base;
3704         crtc->state->crtc = crtc;
3705 
3706 }
3707 
3708 static struct drm_crtc_state *
3709 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3710 {
3711         struct dm_crtc_state *state, *cur;
3712 
3713         cur = to_dm_crtc_state(crtc->state);
3714 
3715         if (WARN_ON(!crtc->state))
3716                 return NULL;
3717 
3718         state = kzalloc(sizeof(*state), GFP_KERNEL);
3719         if (!state)
3720                 return NULL;
3721 
3722         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3723 
3724         if (cur->stream) {
3725                 state->stream = cur->stream;
3726                 dc_stream_retain(state->stream);
3727         }
3728 
3729         state->active_planes = cur->active_planes;
3730         state->interrupts_enabled = cur->interrupts_enabled;
3731         state->vrr_params = cur->vrr_params;
3732         state->vrr_infopacket = cur->vrr_infopacket;
3733         state->abm_level = cur->abm_level;
3734         state->vrr_supported = cur->vrr_supported;
3735         state->freesync_config = cur->freesync_config;
3736         state->crc_src = cur->crc_src;
3737         state->cm_has_degamma = cur->cm_has_degamma;
3738         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
3739 
3740         /* TODO Duplicate dc_stream after objects are stream object is flattened */
3741 
3742         return &state->base;
3743 }
3744 
3745 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3746 {
3747         enum dc_irq_source irq_source;
3748         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3749         struct amdgpu_device *adev = crtc->dev->dev_private;
3750         int rc;
3751 
3752         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3753 
3754         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3755 
3756         DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3757                          acrtc->crtc_id, enable ? "en" : "dis", rc);
3758         return rc;
3759 }
3760 
3761 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3762 {
3763         enum dc_irq_source irq_source;
3764         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3765         struct amdgpu_device *adev = crtc->dev->dev_private;
3766         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3767         int rc = 0;
3768 
3769         if (enable) {
3770                 /* vblank irq on -> Only need vupdate irq in vrr mode */
3771                 if (amdgpu_dm_vrr_active(acrtc_state))
3772                         rc = dm_set_vupdate_irq(crtc, true);
3773         } else {
3774                 /* vblank irq off -> vupdate irq off */
3775                 rc = dm_set_vupdate_irq(crtc, false);
3776         }
3777 
3778         if (rc)
3779                 return rc;
3780 
3781         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3782         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3783 }
3784 
3785 static int dm_enable_vblank(struct drm_crtc *crtc)
3786 {
3787         return dm_set_vblank(crtc, true);
3788 }
3789 
3790 static void dm_disable_vblank(struct drm_crtc *crtc)
3791 {
3792         dm_set_vblank(crtc, false);
3793 }
3794 
3795 /* Implemented only the options currently availible for the driver */
3796 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3797         .reset = dm_crtc_reset_state,
3798         .destroy = amdgpu_dm_crtc_destroy,
3799         .gamma_set = drm_atomic_helper_legacy_gamma_set,
3800         .set_config = drm_atomic_helper_set_config,
3801         .page_flip = drm_atomic_helper_page_flip,
3802         .atomic_duplicate_state = dm_crtc_duplicate_state,
3803         .atomic_destroy_state = dm_crtc_destroy_state,
3804         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3805         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3806         .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
3807         .enable_vblank = dm_enable_vblank,
3808         .disable_vblank = dm_disable_vblank,
3809 };
3810 
3811 static enum drm_connector_status
3812 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3813 {
3814         bool connected;
3815         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3816 
3817         /*
3818          * Notes:
3819          * 1. This interface is NOT called in context of HPD irq.
3820          * 2. This interface *is called* in context of user-mode ioctl. Which
3821          * makes it a bad place for *any* MST-related activity.
3822          */
3823 
3824         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3825             !aconnector->fake_enable)
3826                 connected = (aconnector->dc_sink != NULL);
3827         else
3828                 connected = (aconnector->base.force == DRM_FORCE_ON);
3829 
3830         return (connected ? connector_status_connected :
3831                         connector_status_disconnected);
3832 }
3833 
3834 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3835                                             struct drm_connector_state *connector_state,
3836                                             struct drm_property *property,
3837                                             uint64_t val)
3838 {
3839         struct drm_device *dev = connector->dev;
3840         struct amdgpu_device *adev = dev->dev_private;
3841         struct dm_connector_state *dm_old_state =
3842                 to_dm_connector_state(connector->state);
3843         struct dm_connector_state *dm_new_state =
3844                 to_dm_connector_state(connector_state);
3845 
3846         int ret = -EINVAL;
3847 
3848         if (property == dev->mode_config.scaling_mode_property) {
3849                 enum amdgpu_rmx_type rmx_type;
3850 
3851                 switch (val) {
3852                 case DRM_MODE_SCALE_CENTER:
3853                         rmx_type = RMX_CENTER;
3854                         break;
3855                 case DRM_MODE_SCALE_ASPECT:
3856                         rmx_type = RMX_ASPECT;
3857                         break;
3858                 case DRM_MODE_SCALE_FULLSCREEN:
3859                         rmx_type = RMX_FULL;
3860                         break;
3861                 case DRM_MODE_SCALE_NONE:
3862                 default:
3863                         rmx_type = RMX_OFF;
3864                         break;
3865                 }
3866 
3867                 if (dm_old_state->scaling == rmx_type)
3868                         return 0;
3869 
3870                 dm_new_state->scaling = rmx_type;
3871                 ret = 0;
3872         } else if (property == adev->mode_info.underscan_hborder_property) {
3873                 dm_new_state->underscan_hborder = val;
3874                 ret = 0;
3875         } else if (property == adev->mode_info.underscan_vborder_property) {
3876                 dm_new_state->underscan_vborder = val;
3877                 ret = 0;
3878         } else if (property == adev->mode_info.underscan_property) {
3879                 dm_new_state->underscan_enable = val;
3880                 ret = 0;
3881         } else if (property == adev->mode_info.abm_level_property) {
3882                 dm_new_state->abm_level = val;
3883                 ret = 0;
3884         }
3885 
3886         return ret;
3887 }
3888 
3889 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3890                                             const struct drm_connector_state *state,
3891                                             struct drm_property *property,
3892                                             uint64_t *val)
3893 {
3894         struct drm_device *dev = connector->dev;
3895         struct amdgpu_device *adev = dev->dev_private;
3896         struct dm_connector_state *dm_state =
3897                 to_dm_connector_state(state);
3898         int ret = -EINVAL;
3899 
3900         if (property == dev->mode_config.scaling_mode_property) {
3901                 switch (dm_state->scaling) {
3902                 case RMX_CENTER:
3903                         *val = DRM_MODE_SCALE_CENTER;
3904                         break;
3905                 case RMX_ASPECT:
3906                         *val = DRM_MODE_SCALE_ASPECT;
3907                         break;
3908                 case RMX_FULL:
3909                         *val = DRM_MODE_SCALE_FULLSCREEN;
3910                         break;
3911                 case RMX_OFF:
3912                 default:
3913                         *val = DRM_MODE_SCALE_NONE;
3914                         break;
3915                 }
3916                 ret = 0;
3917         } else if (property == adev->mode_info.underscan_hborder_property) {
3918                 *val = dm_state->underscan_hborder;
3919                 ret = 0;
3920         } else if (property == adev->mode_info.underscan_vborder_property) {
3921                 *val = dm_state->underscan_vborder;
3922                 ret = 0;
3923         } else if (property == adev->mode_info.underscan_property) {
3924                 *val = dm_state->underscan_enable;
3925                 ret = 0;
3926         } else if (property == adev->mode_info.abm_level_property) {
3927                 *val = dm_state->abm_level;
3928                 ret = 0;
3929         }
3930 
3931         return ret;
3932 }
3933 
3934 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
3935 {
3936         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
3937 
3938         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
3939 }
3940 
3941 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3942 {
3943         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3944         const struct dc_link *link = aconnector->dc_link;
3945         struct amdgpu_device *adev = connector->dev->dev_private;
3946         struct amdgpu_display_manager *dm = &adev->dm;
3947 
3948 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3949         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3950 
3951         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3952             link->type != dc_connection_none &&
3953             dm->backlight_dev) {
3954                 backlight_device_unregister(dm->backlight_dev);
3955                 dm->backlight_dev = NULL;
3956         }
3957 #endif
3958 
3959         if (aconnector->dc_em_sink)
3960                 dc_sink_release(aconnector->dc_em_sink);
3961         aconnector->dc_em_sink = NULL;
3962         if (aconnector->dc_sink)
3963                 dc_sink_release(aconnector->dc_sink);
3964         aconnector->dc_sink = NULL;
3965 
3966         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3967         drm_connector_unregister(connector);
3968         drm_connector_cleanup(connector);
3969         if (aconnector->i2c) {
3970                 i2c_del_adapter(&aconnector->i2c->base);
3971                 kfree(aconnector->i2c);
3972         }
3973 
3974         kfree(connector);
3975 }
3976 
3977 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3978 {
3979         struct dm_connector_state *state =
3980                 to_dm_connector_state(connector->state);
3981 
3982         if (connector->state)
3983                 __drm_atomic_helper_connector_destroy_state(connector->state);
3984 
3985         kfree(state);
3986 
3987         state = kzalloc(sizeof(*state), GFP_KERNEL);
3988 
3989         if (state) {
3990                 state->scaling = RMX_OFF;
3991                 state->underscan_enable = false;
3992                 state->underscan_hborder = 0;
3993                 state->underscan_vborder = 0;
3994                 state->base.max_requested_bpc = 8;
3995 
3996                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3997                         state->abm_level = amdgpu_dm_abm_level;
3998 
3999                 __drm_atomic_helper_connector_reset(connector, &state->base);
4000         }
4001 }
4002 
4003 struct drm_connector_state *
4004 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
4005 {
4006         struct dm_connector_state *state =
4007                 to_dm_connector_state(connector->state);
4008 
4009         struct dm_connector_state *new_state =
4010                         kmemdup(state, sizeof(*state), GFP_KERNEL);
4011 
4012         if (!new_state)
4013                 return NULL;
4014 
4015         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
4016 
4017         new_state->freesync_capable = state->freesync_capable;
4018         new_state->abm_level = state->abm_level;
4019         new_state->scaling = state->scaling;
4020         new_state->underscan_enable = state->underscan_enable;
4021         new_state->underscan_hborder = state->underscan_hborder;
4022         new_state->underscan_vborder = state->underscan_vborder;
4023 
4024         return &new_state->base;
4025 }
4026 
4027 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4028         .reset = amdgpu_dm_connector_funcs_reset,
4029         .detect = amdgpu_dm_connector_detect,
4030         .fill_modes = drm_helper_probe_single_connector_modes,
4031         .destroy = amdgpu_dm_connector_destroy,
4032         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4033         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4034         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
4035         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4036         .early_unregister = amdgpu_dm_connector_unregister
4037 };
4038 
4039 static int get_modes(struct drm_connector *connector)
4040 {
4041         return amdgpu_dm_connector_get_modes(connector);
4042 }
4043 
4044 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
4045 {
4046         struct dc_sink_init_data init_params = {
4047                         .link = aconnector->dc_link,
4048                         .sink_signal = SIGNAL_TYPE_VIRTUAL
4049         };
4050         struct edid *edid;
4051 
4052         if (!aconnector->base.edid_blob_ptr) {
4053                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4054                                 aconnector->base.name);
4055 
4056                 aconnector->base.force = DRM_FORCE_OFF;
4057                 aconnector->base.override_edid = false;
4058                 return;
4059         }
4060 
4061         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4062 
4063         aconnector->edid = edid;
4064 
4065         aconnector->dc_em_sink = dc_link_add_remote_sink(
4066                 aconnector->dc_link,
4067                 (uint8_t *)edid,
4068                 (edid->extensions + 1) * EDID_LENGTH,
4069                 &init_params);
4070 
4071         if (aconnector->base.force == DRM_FORCE_ON) {
4072                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
4073                 aconnector->dc_link->local_sink :
4074                 aconnector->dc_em_sink;
4075                 dc_sink_retain(aconnector->dc_sink);
4076         }
4077 }
4078 
4079 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
4080 {
4081         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4082 
4083         /*
4084          * In case of headless boot with force on for DP managed connector
4085          * Those settings have to be != 0 to get initial modeset
4086          */
4087         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4088                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4089                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4090         }
4091 
4092 
4093         aconnector->base.override_edid = true;
4094         create_eml_sink(aconnector);
4095 }
4096 
4097 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
4098                                    struct drm_display_mode *mode)
4099 {
4100         int result = MODE_ERROR;
4101         struct dc_sink *dc_sink;
4102         struct amdgpu_device *adev = connector->dev->dev_private;
4103         /* TODO: Unhardcode stream count */
4104         struct dc_stream_state *stream;
4105         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4106         enum dc_status dc_result = DC_OK;
4107 
4108         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4109                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4110                 return result;
4111 
4112         /*
4113          * Only run this the first time mode_valid is called to initilialize
4114          * EDID mgmt
4115          */
4116         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4117                 !aconnector->dc_em_sink)
4118                 handle_edid_mgmt(aconnector);
4119 
4120         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
4121 
4122         if (dc_sink == NULL) {
4123                 DRM_ERROR("dc_sink is NULL!\n");
4124                 goto fail;
4125         }
4126 
4127         stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
4128         if (stream == NULL) {
4129                 DRM_ERROR("Failed to create stream for sink!\n");
4130                 goto fail;
4131         }
4132 
4133         dc_result = dc_validate_stream(adev->dm.dc, stream);
4134 
4135         if (dc_result == DC_OK)
4136                 result = MODE_OK;
4137         else
4138                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
4139                               mode->vdisplay,
4140                               mode->hdisplay,
4141                               mode->clock,
4142                               dc_result);
4143 
4144         dc_stream_release(stream);
4145 
4146 fail:
4147         /* TODO: error handling*/
4148         return result;
4149 }
4150 
4151 static int fill_hdr_info_packet(const struct drm_connector_state *state,
4152                                 struct dc_info_packet *out)
4153 {
4154         struct hdmi_drm_infoframe frame;
4155         unsigned char buf[30]; /* 26 + 4 */
4156         ssize_t len;
4157         int ret, i;
4158 
4159         memset(out, 0, sizeof(*out));
4160 
4161         if (!state->hdr_output_metadata)
4162                 return 0;
4163 
4164         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4165         if (ret)
4166                 return ret;
4167 
4168         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4169         if (len < 0)
4170                 return (int)len;
4171 
4172         /* Static metadata is a fixed 26 bytes + 4 byte header. */
4173         if (len != 30)
4174                 return -EINVAL;
4175 
4176         /* Prepare the infopacket for DC. */
4177         switch (state->connector->connector_type) {
4178         case DRM_MODE_CONNECTOR_HDMIA:
4179                 out->hb0 = 0x87; /* type */
4180                 out->hb1 = 0x01; /* version */
4181                 out->hb2 = 0x1A; /* length */
4182                 out->sb[0] = buf[3]; /* checksum */
4183                 i = 1;
4184                 break;
4185 
4186         case DRM_MODE_CONNECTOR_DisplayPort:
4187         case DRM_MODE_CONNECTOR_eDP:
4188                 out->hb0 = 0x00; /* sdp id, zero */
4189                 out->hb1 = 0x87; /* type */
4190                 out->hb2 = 0x1D; /* payload len - 1 */
4191                 out->hb3 = (0x13 << 2); /* sdp version */
4192                 out->sb[0] = 0x01; /* version */
4193                 out->sb[1] = 0x1A; /* length */
4194                 i = 2;
4195                 break;
4196 
4197         default:
4198                 return -EINVAL;
4199         }
4200 
4201         memcpy(&out->sb[i], &buf[4], 26);
4202         out->valid = true;
4203 
4204         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4205                        sizeof(out->sb), false);
4206 
4207         return 0;
4208 }
4209 
4210 static bool
4211 is_hdr_metadata_different(const struct drm_connector_state *old_state,
4212                           const struct drm_connector_state *new_state)
4213 {
4214         struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4215         struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4216 
4217         if (old_blob != new_blob) {
4218                 if (old_blob && new_blob &&
4219                     old_blob->length == new_blob->length)
4220                         return memcmp(old_blob->data, new_blob->data,
4221                                       old_blob->length);
4222 
4223                 return true;
4224         }
4225 
4226         return false;
4227 }
4228 
4229 static int
4230 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
4231                                  struct drm_atomic_state *state)
4232 {
4233         struct drm_connector_state *new_con_state =
4234                 drm_atomic_get_new_connector_state(state, conn);
4235         struct drm_connector_state *old_con_state =
4236                 drm_atomic_get_old_connector_state(state, conn);
4237         struct drm_crtc *crtc = new_con_state->crtc;
4238         struct drm_crtc_state *new_crtc_state;
4239         int ret;
4240 
4241         if (!crtc)
4242                 return 0;
4243 
4244         if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4245                 struct dc_info_packet hdr_infopacket;
4246 
4247                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4248                 if (ret)
4249                         return ret;
4250 
4251                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4252                 if (IS_ERR(new_crtc_state))
4253                         return PTR_ERR(new_crtc_state);
4254 
4255                 /*
4256                  * DC considers the stream backends changed if the
4257                  * static metadata changes. Forcing the modeset also
4258                  * gives a simple way for userspace to switch from
4259                  * 8bpc to 10bpc when setting the metadata to enter
4260                  * or exit HDR.
4261                  *
4262                  * Changing the static metadata after it's been
4263                  * set is permissible, however. So only force a
4264                  * modeset if we're entering or exiting HDR.
4265                  */
4266                 new_crtc_state->mode_changed =
4267                         !old_con_state->hdr_output_metadata ||
4268                         !new_con_state->hdr_output_metadata;
4269         }
4270 
4271         return 0;
4272 }
4273 
4274 static const struct drm_connector_helper_funcs
4275 amdgpu_dm_connector_helper_funcs = {
4276         /*
4277          * If hotplugging a second bigger display in FB Con mode, bigger resolution
4278          * modes will be filtered by drm_mode_validate_size(), and those modes
4279          * are missing after user start lightdm. So we need to renew modes list.
4280          * in get_modes call back, not just return the modes count
4281          */
4282         .get_modes = get_modes,
4283         .mode_valid = amdgpu_dm_connector_mode_valid,
4284         .atomic_check = amdgpu_dm_connector_atomic_check,
4285 };
4286 
4287 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4288 {
4289 }
4290 
4291 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4292 {
4293         struct drm_device *dev = new_crtc_state->crtc->dev;
4294         struct drm_plane *plane;
4295 
4296         drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4297                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4298                         return true;
4299         }
4300 
4301         return false;
4302 }
4303 
4304 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
4305 {
4306         struct drm_atomic_state *state = new_crtc_state->state;
4307         struct drm_plane *plane;
4308         int num_active = 0;
4309 
4310         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4311                 struct drm_plane_state *new_plane_state;
4312 
4313                 /* Cursor planes are "fake". */
4314                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4315                         continue;
4316 
4317                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4318 
4319                 if (!new_plane_state) {
4320                         /*
4321                          * The plane is enable on the CRTC and hasn't changed
4322                          * state. This means that it previously passed
4323                          * validation and is therefore enabled.
4324                          */
4325                         num_active += 1;
4326                         continue;
4327                 }
4328 
4329                 /* We need a framebuffer to be considered enabled. */
4330                 num_active += (new_plane_state->fb != NULL);
4331         }
4332 
4333         return num_active;
4334 }
4335 
4336 /*
4337  * Sets whether interrupts should be enabled on a specific CRTC.
4338  * We require that the stream be enabled and that there exist active
4339  * DC planes on the stream.
4340  */
4341 static void
4342 dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4343                                struct drm_crtc_state *new_crtc_state)
4344 {
4345         struct dm_crtc_state *dm_new_crtc_state =
4346                 to_dm_crtc_state(new_crtc_state);
4347 
4348         dm_new_crtc_state->active_planes = 0;
4349         dm_new_crtc_state->interrupts_enabled = false;
4350 
4351         if (!dm_new_crtc_state->stream)
4352                 return;
4353 
4354         dm_new_crtc_state->active_planes =
4355                 count_crtc_active_planes(new_crtc_state);
4356 
4357         dm_new_crtc_state->interrupts_enabled =
4358                 dm_new_crtc_state->active_planes > 0;
4359 }
4360 
4361 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4362                                        struct drm_crtc_state *state)
4363 {
4364         struct amdgpu_device *adev = crtc->dev->dev_private;
4365         struct dc *dc = adev->dm.dc;
4366         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4367         int ret = -EINVAL;
4368 
4369         /*
4370          * Update interrupt state for the CRTC. This needs to happen whenever
4371          * the CRTC has changed or whenever any of its planes have changed.
4372          * Atomic check satisfies both of these requirements since the CRTC
4373          * is added to the state by DRM during drm_atomic_helper_check_planes.
4374          */
4375         dm_update_crtc_interrupt_state(crtc, state);
4376 
4377         if (unlikely(!dm_crtc_state->stream &&
4378                      modeset_required(state, NULL, dm_crtc_state->stream))) {
4379                 WARN_ON(1);
4380                 return ret;
4381         }
4382 
4383         /* In some use cases, like reset, no stream is attached */
4384         if (!dm_crtc_state->stream)
4385                 return 0;
4386 
4387         /*
4388          * We want at least one hardware plane enabled to use
4389          * the stream with a cursor enabled.
4390          */
4391         if (state->enable && state->active &&
4392             does_crtc_have_active_cursor(state) &&
4393             dm_crtc_state->active_planes == 0)
4394                 return -EINVAL;
4395 
4396         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
4397                 return 0;
4398 
4399         return ret;
4400 }
4401 
4402 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4403                                       const struct drm_display_mode *mode,
4404                                       struct drm_display_mode *adjusted_mode)
4405 {
4406         return true;
4407 }
4408 
4409 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4410         .disable = dm_crtc_helper_disable,
4411         .atomic_check = dm_crtc_helper_atomic_check,
4412         .mode_fixup = dm_crtc_helper_mode_fixup
4413 };
4414 
4415 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4416 {
4417 
4418 }
4419 
4420 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4421                                           struct drm_crtc_state *crtc_state,
4422                                           struct drm_connector_state *conn_state)
4423 {
4424         return 0;
4425 }
4426 
4427 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4428         .disable = dm_encoder_helper_disable,
4429         .atomic_check = dm_encoder_helper_atomic_check
4430 };
4431 
4432 static void dm_drm_plane_reset(struct drm_plane *plane)
4433 {
4434         struct dm_plane_state *amdgpu_state = NULL;
4435 
4436         if (plane->state)
4437                 plane->funcs->atomic_destroy_state(plane, plane->state);
4438 
4439         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
4440         WARN_ON(amdgpu_state == NULL);
4441 
4442         if (amdgpu_state)
4443                 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
4444 }
4445 
4446 static struct drm_plane_state *
4447 dm_drm_plane_duplicate_state(struct drm_plane *plane)
4448 {
4449         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4450 
4451         old_dm_plane_state = to_dm_plane_state(plane->state);
4452         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4453         if (!dm_plane_state)
4454                 return NULL;
4455 
4456         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4457 
4458         if (old_dm_plane_state->dc_state) {
4459                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4460                 dc_plane_state_retain(dm_plane_state->dc_state);
4461         }
4462 
4463         return &dm_plane_state->base;
4464 }
4465 
4466 void dm_drm_plane_destroy_state(struct drm_plane *plane,
4467                                 struct drm_plane_state *state)
4468 {
4469         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4470 
4471         if (dm_plane_state->dc_state)
4472                 dc_plane_state_release(dm_plane_state->dc_state);
4473 
4474         drm_atomic_helper_plane_destroy_state(plane, state);
4475 }
4476 
4477 static const struct drm_plane_funcs dm_plane_funcs = {
4478         .update_plane   = drm_atomic_helper_update_plane,
4479         .disable_plane  = drm_atomic_helper_disable_plane,
4480         .destroy        = drm_primary_helper_destroy,
4481         .reset = dm_drm_plane_reset,
4482         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4483         .atomic_destroy_state = dm_drm_plane_destroy_state,
4484 };
4485 
4486 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4487                                       struct drm_plane_state *new_state)
4488 {
4489         struct amdgpu_framebuffer *afb;
4490         struct drm_gem_object *obj;
4491         struct amdgpu_device *adev;
4492         struct amdgpu_bo *rbo;
4493         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
4494         struct list_head list;
4495         struct ttm_validate_buffer tv;
4496         struct ww_acquire_ctx ticket;
4497         uint64_t tiling_flags;
4498         uint32_t domain;
4499         int r;
4500         bool force_disable_dcc = false;
4501 
4502         dm_plane_state_old = to_dm_plane_state(plane->state);
4503         dm_plane_state_new = to_dm_plane_state(new_state);
4504 
4505         if (!new_state->fb) {
4506                 DRM_DEBUG_DRIVER("No FB bound\n");
4507                 return 0;
4508         }
4509 
4510         afb = to_amdgpu_framebuffer(new_state->fb);
4511         obj = new_state->fb->obj[0];
4512         rbo = gem_to_amdgpu_bo(obj);
4513         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
4514         INIT_LIST_HEAD(&list);
4515 
4516         tv.bo = &rbo->tbo;
4517         tv.num_shared = 1;
4518         list_add(&tv.head, &list);
4519 
4520         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true);
4521         if (r) {
4522                 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
4523                 return r;
4524         }
4525 
4526         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4527                 domain = amdgpu_display_supported_domains(adev, rbo->flags);
4528         else
4529                 domain = AMDGPU_GEM_DOMAIN_VRAM;
4530 
4531         r = amdgpu_bo_pin(rbo, domain);
4532         if (unlikely(r != 0)) {
4533                 if (r != -ERESTARTSYS)
4534                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
4535                 ttm_eu_backoff_reservation(&ticket, &list);
4536                 return r;
4537         }
4538 
4539         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4540         if (unlikely(r != 0)) {
4541                 amdgpu_bo_unpin(rbo);
4542                 ttm_eu_backoff_reservation(&ticket, &list);
4543                 DRM_ERROR("%p bind failed\n", rbo);
4544                 return r;
4545         }
4546 
4547         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4548 
4549         ttm_eu_backoff_reservation(&ticket, &list);
4550 
4551         afb->address = amdgpu_bo_gpu_offset(rbo);
4552 
4553         amdgpu_bo_ref(rbo);
4554 
4555         if (dm_plane_state_new->dc_state &&
4556                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4557                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
4558 
4559                 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4560                 fill_plane_buffer_attributes(
4561                         adev, afb, plane_state->format, plane_state->rotation,
4562                         tiling_flags, &plane_state->tiling_info,
4563                         &plane_state->plane_size, &plane_state->dcc,
4564                         &plane_state->address,
4565                         force_disable_dcc);
4566         }
4567 
4568         return 0;
4569 }
4570 
4571 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4572                                        struct drm_plane_state *old_state)
4573 {
4574         struct amdgpu_bo *rbo;
4575         int r;
4576 
4577         if (!old_state->fb)
4578                 return;
4579 
4580         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
4581         r = amdgpu_bo_reserve(rbo, false);
4582         if (unlikely(r)) {
4583                 DRM_ERROR("failed to reserve rbo before unpin\n");
4584                 return;
4585         }
4586 
4587         amdgpu_bo_unpin(rbo);
4588         amdgpu_bo_unreserve(rbo);
4589         amdgpu_bo_unref(&rbo);
4590 }
4591 
4592 static int dm_plane_atomic_check(struct drm_plane *plane,
4593                                  struct drm_plane_state *state)
4594 {
4595         struct amdgpu_device *adev = plane->dev->dev_private;
4596         struct dc *dc = adev->dm.dc;
4597         struct dm_plane_state *dm_plane_state;
4598         struct dc_scaling_info scaling_info;
4599         int ret;
4600 
4601         dm_plane_state = to_dm_plane_state(state);
4602 
4603         if (!dm_plane_state->dc_state)
4604                 return 0;
4605 
4606         ret = fill_dc_scaling_info(state, &scaling_info);
4607         if (ret)
4608                 return ret;
4609 
4610         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
4611                 return 0;
4612 
4613         return -EINVAL;
4614 }
4615 
4616 static int dm_plane_atomic_async_check(struct drm_plane *plane,
4617                                        struct drm_plane_state *new_plane_state)
4618 {
4619         /* Only support async updates on cursor planes. */
4620         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4621                 return -EINVAL;
4622 
4623         return 0;
4624 }
4625 
4626 static void dm_plane_atomic_async_update(struct drm_plane *plane,
4627                                          struct drm_plane_state *new_state)
4628 {
4629         struct drm_plane_state *old_state =
4630                 drm_atomic_get_old_plane_state(new_state->state, plane);
4631 
4632         swap(plane->state->fb, new_state->fb);
4633 
4634         plane->state->src_x = new_state->src_x;
4635         plane->state->src_y = new_state->src_y;
4636         plane->state->src_w = new_state->src_w;
4637         plane->state->src_h = new_state->src_h;
4638         plane->state->crtc_x = new_state->crtc_x;
4639         plane->state->crtc_y = new_state->crtc_y;
4640         plane->state->crtc_w = new_state->crtc_w;
4641         plane->state->crtc_h = new_state->crtc_h;
4642 
4643         handle_cursor_update(plane, old_state);
4644 }
4645 
4646 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4647         .prepare_fb = dm_plane_helper_prepare_fb,
4648         .cleanup_fb = dm_plane_helper_cleanup_fb,
4649         .atomic_check = dm_plane_atomic_check,
4650         .atomic_async_check = dm_plane_atomic_async_check,
4651         .atomic_async_update = dm_plane_atomic_async_update
4652 };
4653 
4654 /*
4655  * TODO: these are currently initialized to rgb formats only.
4656  * For future use cases we should either initialize them dynamically based on
4657  * plane capabilities, or initialize this array to all formats, so internal drm
4658  * check will succeed, and let DC implement proper check
4659  */
4660 static const uint32_t rgb_formats[] = {
4661         DRM_FORMAT_XRGB8888,
4662         DRM_FORMAT_ARGB8888,
4663         DRM_FORMAT_RGBA8888,
4664         DRM_FORMAT_XRGB2101010,
4665         DRM_FORMAT_XBGR2101010,
4666         DRM_FORMAT_ARGB2101010,
4667         DRM_FORMAT_ABGR2101010,
4668         DRM_FORMAT_XBGR8888,
4669         DRM_FORMAT_ABGR8888,
4670         DRM_FORMAT_RGB565,
4671 };
4672 
4673 static const uint32_t overlay_formats[] = {
4674         DRM_FORMAT_XRGB8888,
4675         DRM_FORMAT_ARGB8888,
4676         DRM_FORMAT_RGBA8888,
4677         DRM_FORMAT_XBGR8888,
4678         DRM_FORMAT_ABGR8888,
4679         DRM_FORMAT_RGB565
4680 };
4681 
4682 static const u32 cursor_formats[] = {
4683         DRM_FORMAT_ARGB8888
4684 };
4685 
4686 static int get_plane_formats(const struct drm_plane *plane,
4687                              const struct dc_plane_cap *plane_cap,
4688                              uint32_t *formats, int max_formats)
4689 {
4690         int i, num_formats = 0;
4691 
4692         /*
4693          * TODO: Query support for each group of formats directly from
4694          * DC plane caps. This will require adding more formats to the
4695          * caps list.
4696          */
4697 
4698         switch (plane->type) {
4699         case DRM_PLANE_TYPE_PRIMARY:
4700                 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4701                         if (num_formats >= max_formats)
4702                                 break;
4703 
4704                         formats[num_formats++] = rgb_formats[i];
4705                 }
4706 
4707                 if (plane_cap && plane_cap->pixel_format_support.nv12)
4708                         formats[num_formats++] = DRM_FORMAT_NV12;
4709                 break;
4710 
4711         case DRM_PLANE_TYPE_OVERLAY:
4712                 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4713                         if (num_formats >= max_formats)
4714                                 break;
4715 
4716                         formats[num_formats++] = overlay_formats[i];
4717                 }
4718                 break;
4719 
4720         case DRM_PLANE_TYPE_CURSOR:
4721                 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4722                         if (num_formats >= max_formats)
4723                                 break;
4724 
4725                         formats[num_formats++] = cursor_formats[i];
4726                 }
4727                 break;
4728         }
4729 
4730         return num_formats;
4731 }
4732 
4733 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4734                                 struct drm_plane *plane,
4735                                 unsigned long possible_crtcs,
4736                                 const struct dc_plane_cap *plane_cap)
4737 {
4738         uint32_t formats[32];
4739         int num_formats;
4740         int res = -EPERM;
4741 
4742         num_formats = get_plane_formats(plane, plane_cap, formats,
4743                                         ARRAY_SIZE(formats));
4744 
4745         res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4746                                        &dm_plane_funcs, formats, num_formats,
4747                                        NULL, plane->type, NULL);
4748         if (res)
4749                 return res;
4750 
4751         if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4752             plane_cap && plane_cap->per_pixel_alpha) {
4753                 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4754                                           BIT(DRM_MODE_BLEND_PREMULTI);
4755 
4756                 drm_plane_create_alpha_property(plane);
4757                 drm_plane_create_blend_mode_property(plane, blend_caps);
4758         }
4759 
4760         if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
4761             plane_cap && plane_cap->pixel_format_support.nv12) {
4762                 /* This only affects YUV formats. */
4763                 drm_plane_create_color_properties(
4764                         plane,
4765                         BIT(DRM_COLOR_YCBCR_BT601) |
4766                         BIT(DRM_COLOR_YCBCR_BT709),
4767                         BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4768                         BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4769                         DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4770         }
4771 
4772         drm_plane_helper_add(plane, &dm_plane_helper_funcs);
4773 
4774         /* Create (reset) the plane state */
4775         if (plane->funcs->reset)
4776                 plane->funcs->reset(plane);
4777 
4778         return 0;
4779 }
4780 
4781 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4782                                struct drm_plane *plane,
4783                                uint32_t crtc_index)
4784 {
4785         struct amdgpu_crtc *acrtc = NULL;
4786         struct drm_plane *cursor_plane;
4787 
4788         int res = -ENOMEM;
4789 
4790         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4791         if (!cursor_plane)
4792                 goto fail;
4793 
4794         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
4795         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
4796 
4797         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4798         if (!acrtc)
4799                 goto fail;
4800 
4801         res = drm_crtc_init_with_planes(
4802                         dm->ddev,
4803                         &acrtc->base,
4804                         plane,
4805                         cursor_plane,
4806                         &amdgpu_dm_crtc_funcs, NULL);
4807 
4808         if (res)
4809                 goto fail;
4810 
4811         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4812 
4813         /* Create (reset) the plane state */
4814         if (acrtc->base.funcs->reset)
4815                 acrtc->base.funcs->reset(&acrtc->base);
4816 
4817         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4818         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4819 
4820         acrtc->crtc_id = crtc_index;
4821         acrtc->base.enabled = false;
4822         acrtc->otg_inst = -1;
4823 
4824         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
4825         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4826                                    true, MAX_COLOR_LUT_ENTRIES);
4827         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
4828 
4829         return 0;
4830 
4831 fail:
4832         kfree(acrtc);
4833         kfree(cursor_plane);
4834         return res;
4835 }
4836 
4837 
4838 static int to_drm_connector_type(enum signal_type st)
4839 {
4840         switch (st) {
4841         case SIGNAL_TYPE_HDMI_TYPE_A:
4842                 return DRM_MODE_CONNECTOR_HDMIA;
4843         case SIGNAL_TYPE_EDP:
4844                 return DRM_MODE_CONNECTOR_eDP;
4845         case SIGNAL_TYPE_LVDS:
4846                 return DRM_MODE_CONNECTOR_LVDS;
4847         case SIGNAL_TYPE_RGB:
4848                 return DRM_MODE_CONNECTOR_VGA;
4849         case SIGNAL_TYPE_DISPLAY_PORT:
4850         case SIGNAL_TYPE_DISPLAY_PORT_MST:
4851                 return DRM_MODE_CONNECTOR_DisplayPort;
4852         case SIGNAL_TYPE_DVI_DUAL_LINK:
4853         case SIGNAL_TYPE_DVI_SINGLE_LINK:
4854                 return DRM_MODE_CONNECTOR_DVID;
4855         case SIGNAL_TYPE_VIRTUAL:
4856                 return DRM_MODE_CONNECTOR_VIRTUAL;
4857 
4858         default:
4859                 return DRM_MODE_CONNECTOR_Unknown;
4860         }
4861 }
4862 
4863 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4864 {
4865         return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4866 }
4867 
4868 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4869 {
4870         struct drm_encoder *encoder;
4871         struct amdgpu_encoder *amdgpu_encoder;
4872 
4873         encoder = amdgpu_dm_connector_to_encoder(connector);
4874 
4875         if (encoder == NULL)
4876                 return;
4877 
4878         amdgpu_encoder = to_amdgpu_encoder(encoder);
4879 
4880         amdgpu_encoder->native_mode.clock = 0;
4881 
4882         if (!list_empty(&connector->probed_modes)) {
4883                 struct drm_display_mode *preferred_mode = NULL;
4884 
4885                 list_for_each_entry(preferred_mode,
4886                                     &connector->probed_modes,
4887                                     head) {
4888                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4889                                 amdgpu_encoder->native_mode = *preferred_mode;
4890 
4891                         break;
4892                 }
4893 
4894         }
4895 }
4896 
4897 static struct drm_display_mode *
4898 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4899                              char *name,
4900                              int hdisplay, int vdisplay)
4901 {
4902         struct drm_device *dev = encoder->dev;
4903         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4904         struct drm_display_mode *mode = NULL;
4905         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4906 
4907         mode = drm_mode_duplicate(dev, native_mode);
4908 
4909         if (mode == NULL)
4910                 return NULL;
4911 
4912         mode->hdisplay = hdisplay;
4913         mode->vdisplay = vdisplay;
4914         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
4915         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
4916 
4917         return mode;
4918 
4919 }
4920 
4921 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
4922                                                  struct drm_connector *connector)
4923 {
4924         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4925         struct drm_display_mode *mode = NULL;
4926         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4927         struct amdgpu_dm_connector *amdgpu_dm_connector =
4928                                 to_amdgpu_dm_connector(connector);
4929         int i;
4930         int n;
4931         struct mode_size {
4932                 char name[DRM_DISPLAY_MODE_LEN];
4933                 int w;
4934                 int h;
4935         } common_modes[] = {
4936                 {  "640x480",  640,  480},
4937                 {  "800x600",  800,  600},
4938                 { "1024x768", 1024,  768},
4939                 { "1280x720", 1280,  720},
4940                 { "1280x800", 1280,  800},
4941                 {"1280x1024", 1280, 1024},
4942                 { "1440x900", 1440,  900},
4943                 {"1680x1050", 1680, 1050},
4944                 {"1600x1200", 1600, 1200},
4945                 {"1920x1080", 1920, 1080},
4946                 {"1920x1200", 1920, 1200}
4947         };
4948 
4949         n = ARRAY_SIZE(common_modes);
4950 
4951         for (i = 0; i < n; i++) {
4952                 struct drm_display_mode *curmode = NULL;
4953                 bool mode_existed = false;
4954 
4955                 if (common_modes[i].w > native_mode->hdisplay ||
4956                     common_modes[i].h > native_mode->vdisplay ||
4957                    (common_modes[i].w == native_mode->hdisplay &&
4958                     common_modes[i].h == native_mode->vdisplay))
4959                         continue;
4960 
4961                 list_for_each_entry(curmode, &connector->probed_modes, head) {
4962                         if (common_modes[i].w == curmode->hdisplay &&
4963                             common_modes[i].h == curmode->vdisplay) {
4964                                 mode_existed = true;
4965                                 break;
4966                         }
4967                 }
4968 
4969                 if (mode_existed)
4970                         continue;
4971 
4972                 mode = amdgpu_dm_create_common_mode(encoder,
4973                                 common_modes[i].name, common_modes[i].w,
4974                                 common_modes[i].h);
4975                 drm_mode_probed_add(connector, mode);
4976                 amdgpu_dm_connector->num_modes++;
4977         }
4978 }
4979 
4980 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4981                                               struct edid *edid)
4982 {
4983         struct amdgpu_dm_connector *amdgpu_dm_connector =
4984                         to_amdgpu_dm_connector(connector);
4985 
4986         if (edid) {
4987                 /* empty probed_modes */
4988                 INIT_LIST_HEAD(&connector->probed_modes);
4989                 amdgpu_dm_connector->num_modes =
4990                                 drm_add_edid_modes(connector, edid);
4991 
4992                 /* sorting the probed modes before calling function
4993                  * amdgpu_dm_get_native_mode() since EDID can have
4994                  * more than one preferred mode. The modes that are
4995                  * later in the probed mode list could be of higher
4996                  * and preferred resolution. For example, 3840x2160
4997                  * resolution in base EDID preferred timing and 4096x2160
4998                  * preferred resolution in DID extension block later.
4999                  */
5000                 drm_mode_sort(&connector->probed_modes);
5001                 amdgpu_dm_get_native_mode(connector);
5002         } else {
5003                 amdgpu_dm_connector->num_modes = 0;
5004         }
5005 }
5006 
5007 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
5008 {
5009         struct amdgpu_dm_connector *amdgpu_dm_connector =
5010                         to_amdgpu_dm_connector(connector);
5011         struct drm_encoder *encoder;
5012         struct edid *edid = amdgpu_dm_connector->edid;
5013 
5014         encoder = amdgpu_dm_connector_to_encoder(connector);
5015 
5016         if (!edid || !drm_edid_is_valid(edid)) {
5017                 amdgpu_dm_connector->num_modes =
5018                                 drm_add_modes_noedid(connector, 640, 480);
5019         } else {
5020                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
5021                 amdgpu_dm_connector_add_common_modes(encoder, connector);
5022         }
5023         amdgpu_dm_fbc_init(connector);
5024 
5025         return amdgpu_dm_connector->num_modes;
5026 }
5027 
5028 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
5029                                      struct amdgpu_dm_connector *aconnector,
5030                                      int connector_type,
5031                                      struct dc_link *link,
5032                                      int link_index)
5033 {
5034         struct amdgpu_device *adev = dm->ddev->dev_private;
5035 
5036         /*
5037          * Some of the properties below require access to state, like bpc.
5038          * Allocate some default initial connector state with our reset helper.
5039          */
5040         if (aconnector->base.funcs->reset)
5041                 aconnector->base.funcs->reset(&aconnector->base);
5042 
5043         aconnector->connector_id = link_index;
5044         aconnector->dc_link = link;
5045         aconnector->base.interlace_allowed = false;
5046         aconnector->base.doublescan_allowed = false;
5047         aconnector->base.stereo_allowed = false;
5048         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
5049         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
5050         aconnector->audio_inst = -1;
5051         mutex_init(&aconnector->hpd_lock);
5052 
5053         /*
5054          * configure support HPD hot plug connector_>polled default value is 0
5055          * which means HPD hot plug not supported
5056          */
5057         switch (connector_type) {
5058         case DRM_MODE_CONNECTOR_HDMIA:
5059                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5060                 aconnector->base.ycbcr_420_allowed =
5061                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
5062                 break;
5063         case DRM_MODE_CONNECTOR_DisplayPort:
5064                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5065                 aconnector->base.ycbcr_420_allowed =
5066                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
5067                 break;
5068         case DRM_MODE_CONNECTOR_DVID:
5069                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5070                 break;
5071         default:
5072                 break;
5073         }
5074 
5075         drm_object_attach_property(&aconnector->base.base,
5076                                 dm->ddev->mode_config.scaling_mode_property,
5077                                 DRM_MODE_SCALE_NONE);
5078 
5079         drm_object_attach_property(&aconnector->base.base,
5080                                 adev->mode_info.underscan_property,
5081                                 UNDERSCAN_OFF);
5082         drm_object_attach_property(&aconnector->base.base,
5083                                 adev->mode_info.underscan_hborder_property,
5084                                 0);
5085         drm_object_attach_property(&aconnector->base.base,
5086                                 adev->mode_info.underscan_vborder_property,
5087                                 0);
5088 
5089         drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5090 
5091         /* This defaults to the max in the range, but we want 8bpc. */
5092         aconnector->base.state->max_bpc = 8;
5093         aconnector->base.state->max_requested_bpc = 8;
5094 
5095         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5096             dc_is_dmcu_initialized(adev->dm.dc)) {
5097                 drm_object_attach_property(&aconnector->base.base,
5098                                 adev->mode_info.abm_level_property, 0);
5099         }
5100 
5101         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
5102             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5103             connector_type == DRM_MODE_CONNECTOR_eDP) {
5104                 drm_object_attach_property(
5105                         &aconnector->base.base,
5106                         dm->ddev->mode_config.hdr_output_metadata_property, 0);
5107 
5108                 drm_connector_attach_vrr_capable_property(
5109                         &aconnector->base);
5110         }
5111 }
5112 
5113 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5114                               struct i2c_msg *msgs, int num)
5115 {
5116         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5117         struct ddc_service *ddc_service = i2c->ddc_service;
5118         struct i2c_command cmd;
5119         int i;
5120         int result = -EIO;
5121 
5122         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
5123 
5124         if (!cmd.payloads)
5125                 return result;
5126 
5127         cmd.number_of_payloads = num;
5128         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5129         cmd.speed = 100;
5130 
5131         for (i = 0; i < num; i++) {
5132                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5133                 cmd.payloads[i].address = msgs[i].addr;
5134                 cmd.payloads[i].length = msgs[i].len;
5135                 cmd.payloads[i].data = msgs[i].buf;
5136         }
5137 
5138         if (dc_submit_i2c(
5139                         ddc_service->ctx->dc,
5140                         ddc_service->ddc_pin->hw_info.ddc_channel,
5141                         &cmd))
5142                 result = num;
5143 
5144         kfree(cmd.payloads);
5145         return result;
5146 }
5147 
5148 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
5149 {
5150         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5151 }
5152 
5153 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5154         .master_xfer = amdgpu_dm_i2c_xfer,
5155         .functionality = amdgpu_dm_i2c_func,
5156 };
5157 
5158 static struct amdgpu_i2c_adapter *
5159 create_i2c(struct ddc_service *ddc_service,
5160            int link_index,
5161            int *res)
5162 {
5163         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5164         struct amdgpu_i2c_adapter *i2c;
5165 
5166         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
5167         if (!i2c)
5168                 return NULL;
5169         i2c->base.owner = THIS_MODULE;
5170         i2c->base.class = I2C_CLASS_DDC;
5171         i2c->base.dev.parent = &adev->pdev->dev;
5172         i2c->base.algo = &amdgpu_dm_i2c_algo;
5173         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
5174         i2c_set_adapdata(&i2c->base, i2c);
5175         i2c->ddc_service = ddc_service;
5176         i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
5177 
5178         return i2c;
5179 }
5180 
5181 
5182 /*
5183  * Note: this function assumes that dc_link_detect() was called for the
5184  * dc_link which will be represented by this aconnector.
5185  */
5186 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5187                                     struct amdgpu_dm_connector *aconnector,
5188                                     uint32_t link_index,
5189                                     struct amdgpu_encoder *aencoder)
5190 {
5191         int res = 0;
5192         int connector_type;
5193         struct dc *dc = dm->dc;
5194         struct dc_link *link = dc_get_link_at_index(dc, link_index);
5195         struct amdgpu_i2c_adapter *i2c;
5196 
5197         link->priv = aconnector;
5198 
5199         DRM_DEBUG_DRIVER("%s()\n", __func__);
5200 
5201         i2c = create_i2c(link->ddc, link->link_index, &res);
5202         if (!i2c) {
5203                 DRM_ERROR("Failed to create i2c adapter data\n");
5204                 return -ENOMEM;
5205         }
5206 
5207         aconnector->i2c = i2c;
5208         res = i2c_add_adapter(&i2c->base);
5209 
5210         if (res) {
5211                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5212                 goto out_free;
5213         }
5214 
5215         connector_type = to_drm_connector_type(link->connector_signal);
5216 
5217         res = drm_connector_init(
5218                         dm->ddev,
5219                         &aconnector->base,
5220                         &amdgpu_dm_connector_funcs,
5221                         connector_type);
5222 
5223         if (res) {
5224                 DRM_ERROR("connector_init failed\n");
5225                 aconnector->connector_id = -1;
5226                 goto out_free;
5227         }
5228 
5229         drm_connector_helper_add(
5230                         &aconnector->base,
5231                         &amdgpu_dm_connector_helper_funcs);
5232 
5233         amdgpu_dm_connector_init_helper(
5234                 dm,
5235                 aconnector,
5236                 connector_type,
5237                 link,
5238                 link_index);
5239 
5240         drm_connector_attach_encoder(
5241                 &aconnector->base, &aencoder->base);
5242 
5243         drm_connector_register(&aconnector->base);
5244 #if defined(CONFIG_DEBUG_FS)
5245         connector_debugfs_init(aconnector);
5246         aconnector->debugfs_dpcd_address = 0;
5247         aconnector->debugfs_dpcd_size = 0;
5248 #endif
5249 
5250         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5251                 || connector_type == DRM_MODE_CONNECTOR_eDP)
5252                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
5253 
5254 out_free:
5255         if (res) {
5256                 kfree(i2c);
5257                 aconnector->i2c = NULL;
5258         }
5259         return res;
5260 }
5261 
5262 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5263 {
5264         switch (adev->mode_info.num_crtc) {
5265         case 1:
5266                 return 0x1;
5267         case 2:
5268                 return 0x3;
5269         case 3:
5270                 return 0x7;
5271         case 4:
5272                 return 0xf;
5273         case 5:
5274                 return 0x1f;
5275         case 6:
5276         default:
5277                 return 0x3f;
5278         }
5279 }
5280 
5281 static int amdgpu_dm_encoder_init(struct drm_device *dev,
5282                                   struct amdgpu_encoder *aencoder,
5283                                   uint32_t link_index)
5284 {
5285         struct amdgpu_device *adev = dev->dev_private;
5286 
5287         int res = drm_encoder_init(dev,
5288                                    &aencoder->base,
5289                                    &amdgpu_dm_encoder_funcs,
5290                                    DRM_MODE_ENCODER_TMDS,
5291                                    NULL);
5292 
5293         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5294 
5295         if (!res)
5296                 aencoder->encoder_id = link_index;
5297         else
5298                 aencoder->encoder_id = -1;
5299 
5300         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5301 
5302         return res;
5303 }
5304 
5305 static void manage_dm_interrupts(struct amdgpu_device *adev,
5306                                  struct amdgpu_crtc *acrtc,
5307                                  bool enable)
5308 {
5309         /*
5310          * this is not correct translation but will work as soon as VBLANK
5311          * constant is the same as PFLIP
5312          */
5313         int irq_type =
5314                 amdgpu_display_crtc_idx_to_irq_type(
5315                         adev,
5316                         acrtc->crtc_id);
5317 
5318         if (enable) {
5319                 drm_crtc_vblank_on(&acrtc->base);
5320                 amdgpu_irq_get(
5321                         adev,
5322                         &adev->pageflip_irq,
5323                         irq_type);
5324         } else {
5325 
5326                 amdgpu_irq_put(
5327                         adev,
5328                         &adev->pageflip_irq,
5329                         irq_type);
5330                 drm_crtc_vblank_off(&acrtc->base);
5331         }
5332 }
5333 
5334 static bool
5335 is_scaling_state_different(const struct dm_connector_state *dm_state,
5336                            const struct dm_connector_state *old_dm_state)
5337 {
5338         if (dm_state->scaling != old_dm_state->scaling)
5339                 return true;
5340         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5341                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5342                         return true;
5343         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5344                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5345                         return true;
5346         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5347                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5348                 return true;
5349         return false;
5350 }
5351 
5352 static void remove_stream(struct amdgpu_device *adev,
5353                           struct amdgpu_crtc *acrtc,
5354                           struct dc_stream_state *stream)
5355 {
5356         /* this is the update mode case */
5357 
5358         acrtc->otg_inst = -1;
5359         acrtc->enabled = false;
5360 }
5361 
5362 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5363                                struct dc_cursor_position *position)
5364 {
5365         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5366         int x, y;
5367         int xorigin = 0, yorigin = 0;
5368 
5369         position->enable = false;
5370         position->x = 0;
5371         position->y = 0;
5372 
5373         if (!crtc || !plane->state->fb)
5374                 return 0;
5375 
5376         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5377             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5378                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5379                           __func__,
5380                           plane->state->crtc_w,
5381                           plane->state->crtc_h);
5382                 return -EINVAL;
5383         }
5384 
5385         x = plane->state->crtc_x;
5386         y = plane->state->crtc_y;
5387 
5388         if (x <= -amdgpu_crtc->max_cursor_width ||
5389             y <= -amdgpu_crtc->max_cursor_height)
5390                 return 0;
5391 
5392         if (crtc->primary->state) {
5393                 /* avivo cursor are offset into the total surface */
5394                 x += crtc->primary->state->src_x >> 16;
5395                 y += crtc->primary->state->src_y >> 16;
5396         }
5397 
5398         if (x < 0) {
5399                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5400                 x = 0;
5401         }
5402         if (y < 0) {
5403                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5404                 y = 0;
5405         }
5406         position->enable = true;
5407         position->x = x;
5408         position->y = y;
5409         position->x_hotspot = xorigin;
5410         position->y_hotspot = yorigin;
5411 
5412         return 0;
5413 }
5414 
5415 static void handle_cursor_update(struct drm_plane *plane,
5416                                  struct drm_plane_state *old_plane_state)
5417 {
5418         struct amdgpu_device *adev = plane->dev->dev_private;
5419         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5420         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5421         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5422         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5423         uint64_t address = afb ? afb->address : 0;
5424         struct dc_cursor_position position;
5425         struct dc_cursor_attributes attributes;
5426         int ret;
5427 
5428         if (!plane->state->fb && !old_plane_state->fb)
5429                 return;
5430 
5431         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
5432                          __func__,
5433                          amdgpu_crtc->crtc_id,
5434                          plane->state->crtc_w,
5435                          plane->state->crtc_h);
5436 
5437         ret = get_cursor_position(plane, crtc, &position);
5438         if (ret)
5439                 return;
5440 
5441         if (!position.enable) {
5442                 /* turn off cursor */
5443                 if (crtc_state && crtc_state->stream) {
5444                         mutex_lock(&adev->dm.dc_lock);
5445                         dc_stream_set_cursor_position(crtc_state->stream,
5446                                                       &position);
5447                         mutex_unlock(&adev->dm.dc_lock);
5448                 }
5449                 return;
5450         }
5451 
5452         amdgpu_crtc->cursor_width = plane->state->crtc_w;
5453         amdgpu_crtc->cursor_height = plane->state->crtc_h;
5454 
5455         memset(&attributes, 0, sizeof(attributes));
5456         attributes.address.high_part = upper_32_bits(address);
5457         attributes.address.low_part  = lower_32_bits(address);
5458         attributes.width             = plane->state->crtc_w;
5459         attributes.height            = plane->state->crtc_h;
5460         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5461         attributes.rotation_angle    = 0;
5462         attributes.attribute_flags.value = 0;
5463 
5464         attributes.pitch = attributes.width;
5465 
5466         if (crtc_state->stream) {
5467                 mutex_lock(&adev->dm.dc_lock);
5468                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5469                                                          &attributes))
5470                         DRM_ERROR("DC failed to set cursor attributes\n");
5471 
5472                 if (!dc_stream_set_cursor_position(crtc_state->stream,
5473                                                    &position))
5474                         DRM_ERROR("DC failed to set cursor position\n");
5475                 mutex_unlock(&adev->dm.dc_lock);
5476         }
5477 }
5478 
5479 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5480 {
5481 
5482         assert_spin_locked(&acrtc->base.dev->event_lock);
5483         WARN_ON(acrtc->event);
5484 
5485         acrtc->event = acrtc->base.state->event;
5486 
5487         /* Set the flip status */
5488         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5489 
5490         /* Mark this event as consumed */
5491         acrtc->base.state->event = NULL;
5492 
5493         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5494                                                  acrtc->crtc_id);
5495 }
5496 
5497 static void update_freesync_state_on_stream(
5498         struct amdgpu_display_manager *dm,
5499         struct dm_crtc_state *new_crtc_state,
5500         struct dc_stream_state *new_stream,
5501         struct dc_plane_state *surface,
5502         u32 flip_timestamp_in_us)
5503 {
5504         struct mod_vrr_params vrr_params;
5505         struct dc_info_packet vrr_infopacket = {0};
5506         struct amdgpu_device *adev = dm->adev;
5507         unsigned long flags;
5508 
5509         if (!new_stream)
5510                 return;
5511 
5512         /*
5513          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5514          * For now it's sufficient to just guard against these conditions.
5515          */
5516 
5517         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5518                 return;
5519 
5520         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5521         vrr_params = new_crtc_state->vrr_params;
5522 
5523         if (surface) {
5524                 mod_freesync_handle_preflip(
5525                         dm->freesync_module,
5526                         surface,
5527                         new_stream,
5528                         flip_timestamp_in_us,
5529                         &vrr_params);
5530 
5531                 if (adev->family < AMDGPU_FAMILY_AI &&
5532                     amdgpu_dm_vrr_active(new_crtc_state)) {
5533                         mod_freesync_handle_v_update(dm->freesync_module,
5534                                                      new_stream, &vrr_params);
5535 
5536                         /* Need to call this before the frame ends. */
5537                         dc_stream_adjust_vmin_vmax(dm->dc,
5538                                                    new_crtc_state->stream,
5539                                                    &vrr_params.adjust);
5540                 }
5541         }
5542 
5543         mod_freesync_build_vrr_infopacket(
5544                 dm->freesync_module,
5545                 new_stream,
5546                 &vrr_params,
5547                 PACKET_TYPE_VRR,
5548                 TRANSFER_FUNC_UNKNOWN,
5549                 &vrr_infopacket);
5550 
5551         new_crtc_state->freesync_timing_changed |=
5552                 (memcmp(&new_crtc_state->vrr_params.adjust,
5553                         &vrr_params.adjust,
5554                         sizeof(vrr_params.adjust)) != 0);
5555 
5556         new_crtc_state->freesync_vrr_info_changed |=
5557                 (memcmp(&new_crtc_state->vrr_infopacket,
5558                         &vrr_infopacket,
5559                         sizeof(vrr_infopacket)) != 0);
5560 
5561         new_crtc_state->vrr_params = vrr_params;
5562         new_crtc_state->vrr_infopacket = vrr_infopacket;
5563 
5564         new_stream->adjust = new_crtc_state->vrr_params.adjust;
5565         new_stream->vrr_infopacket = vrr_infopacket;
5566 
5567         if (new_crtc_state->freesync_vrr_info_changed)
5568                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5569                               new_crtc_state->base.crtc->base.id,
5570                               (int)new_crtc_state->base.vrr_enabled,
5571                               (int)vrr_params.state);
5572 
5573         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5574 }
5575 
5576 static void pre_update_freesync_state_on_stream(
5577         struct amdgpu_display_manager *dm,
5578         struct dm_crtc_state *new_crtc_state)
5579 {
5580         struct dc_stream_state *new_stream = new_crtc_state->stream;
5581         struct mod_vrr_params vrr_params;
5582         struct mod_freesync_config config = new_crtc_state->freesync_config;
5583         struct amdgpu_device *adev = dm->adev;
5584         unsigned long flags;
5585 
5586         if (!new_stream)
5587                 return;
5588 
5589         /*
5590          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5591          * For now it's sufficient to just guard against these conditions.
5592          */
5593         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5594                 return;
5595 
5596         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5597         vrr_params = new_crtc_state->vrr_params;
5598 
5599         if (new_crtc_state->vrr_supported &&
5600             config.min_refresh_in_uhz &&
5601             config.max_refresh_in_uhz) {
5602                 config.state = new_crtc_state->base.vrr_enabled ?
5603                         VRR_STATE_ACTIVE_VARIABLE :
5604                         VRR_STATE_INACTIVE;
5605         } else {
5606                 config.state = VRR_STATE_UNSUPPORTED;
5607         }
5608 
5609         mod_freesync_build_vrr_params(dm->freesync_module,
5610                                       new_stream,
5611                                       &config, &vrr_params);
5612 
5613         new_crtc_state->freesync_timing_changed |=
5614                 (memcmp(&new_crtc_state->vrr_params.adjust,
5615                         &vrr_params.adjust,
5616                         sizeof(vrr_params.adjust)) != 0);
5617 
5618         new_crtc_state->vrr_params = vrr_params;
5619         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5620 }
5621 
5622 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5623                                             struct dm_crtc_state *new_state)
5624 {
5625         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5626         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5627 
5628         if (!old_vrr_active && new_vrr_active) {
5629                 /* Transition VRR inactive -> active:
5630                  * While VRR is active, we must not disable vblank irq, as a
5631                  * reenable after disable would compute bogus vblank/pflip
5632                  * timestamps if it likely happened inside display front-porch.
5633                  *
5634                  * We also need vupdate irq for the actual core vblank handling
5635                  * at end of vblank.
5636                  */
5637                 dm_set_vupdate_irq(new_state->base.crtc, true);
5638                 drm_crtc_vblank_get(new_state->base.crtc);
5639                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5640                                  __func__, new_state->base.crtc->base.id);
5641         } else if (old_vrr_active && !new_vrr_active) {
5642                 /* Transition VRR active -> inactive:
5643                  * Allow vblank irq disable again for fixed refresh rate.
5644                  */
5645                 dm_set_vupdate_irq(new_state->base.crtc, false);
5646                 drm_crtc_vblank_put(new_state->base.crtc);
5647                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5648                                  __func__, new_state->base.crtc->base.id);
5649         }
5650 }
5651 
5652 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5653 {
5654         struct drm_plane *plane;
5655         struct drm_plane_state *old_plane_state, *new_plane_state;
5656         int i;
5657 
5658         /*
5659          * TODO: Make this per-stream so we don't issue redundant updates for
5660          * commits with multiple streams.
5661          */
5662         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5663                                        new_plane_state, i)
5664                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5665                         handle_cursor_update(plane, old_plane_state);
5666 }
5667 
5668 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
5669                                     struct dc_state *dc_state,
5670                                     struct drm_device *dev,
5671                                     struct amdgpu_display_manager *dm,
5672                                     struct drm_crtc *pcrtc,
5673                                     bool wait_for_vblank)
5674 {
5675         uint32_t i;
5676         uint64_t timestamp_ns;
5677         struct drm_plane *plane;
5678         struct drm_plane_state *old_plane_state, *new_plane_state;
5679         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
5680         struct drm_crtc_state *new_pcrtc_state =
5681                         drm_atomic_get_new_crtc_state(state, pcrtc);
5682         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
5683         struct dm_crtc_state *dm_old_crtc_state =
5684                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
5685         int planes_count = 0, vpos, hpos;
5686         long r;
5687         unsigned long flags;
5688         struct amdgpu_bo *abo;
5689         uint64_t tiling_flags;
5690         uint32_t target_vblank, last_flip_vblank;
5691         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
5692         bool pflip_present = false;
5693         struct {
5694                 struct dc_surface_update surface_updates[MAX_SURFACES];
5695                 struct dc_plane_info plane_infos[MAX_SURFACES];
5696                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
5697                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
5698                 struct dc_stream_update stream_update;
5699         } *bundle;
5700 
5701         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
5702 
5703         if (!bundle) {
5704                 dm_error("Failed to allocate update bundle\n");
5705                 goto cleanup;
5706         }
5707 
5708         /*
5709          * Disable the cursor first if we're disabling all the planes.
5710          * It'll remain on the screen after the planes are re-enabled
5711          * if we don't.
5712          */
5713         if (acrtc_state->active_planes == 0)
5714                 amdgpu_dm_commit_cursors(state);
5715 
5716         /* update planes when needed */
5717         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5718                 struct drm_crtc *crtc = new_plane_state->crtc;
5719                 struct drm_crtc_state *new_crtc_state;
5720                 struct drm_framebuffer *fb = new_plane_state->fb;
5721                 bool plane_needs_flip;
5722                 struct dc_plane_state *dc_plane;
5723                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
5724 
5725                 /* Cursor plane is handled after stream updates */
5726                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5727                         continue;
5728 
5729                 if (!fb || !crtc || pcrtc != crtc)
5730                         continue;
5731 
5732                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5733                 if (!new_crtc_state->active)
5734                         continue;
5735 
5736                 dc_plane = dm_new_plane_state->dc_state;
5737 
5738                 bundle->surface_updates[planes_count].surface = dc_plane;
5739                 if (new_pcrtc_state->color_mgmt_changed) {
5740                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5741                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
5742                 }
5743 
5744                 fill_dc_scaling_info(new_plane_state,
5745                                      &bundle->scaling_infos[planes_count]);
5746 
5747                 bundle->surface_updates[planes_count].scaling_info =
5748                         &bundle->scaling_infos[planes_count];
5749 
5750                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
5751 
5752                 pflip_present = pflip_present || plane_needs_flip;
5753 
5754                 if (!plane_needs_flip) {
5755                         planes_count += 1;
5756                         continue;
5757                 }
5758 
5759                 abo = gem_to_amdgpu_bo(fb->obj[0]);
5760 
5761                 /*
5762                  * Wait for all fences on this FB. Do limited wait to avoid
5763                  * deadlock during GPU reset when this fence will not signal
5764                  * but we hold reservation lock for the BO.
5765                  */
5766                 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
5767                                                         false,
5768                                                         msecs_to_jiffies(5000));
5769                 if (unlikely(r <= 0))
5770                         DRM_ERROR("Waiting for fences timed out!");
5771 
5772                 /*
5773                  * TODO This might fail and hence better not used, wait
5774                  * explicitly on fences instead
5775                  * and in general should be called for
5776                  * blocking commit to as per framework helpers
5777                  */
5778                 r = amdgpu_bo_reserve(abo, true);
5779                 if (unlikely(r != 0))
5780                         DRM_ERROR("failed to reserve buffer before flip\n");
5781 
5782                 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
5783 
5784                 amdgpu_bo_unreserve(abo);
5785 
5786                 fill_dc_plane_info_and_addr(
5787                         dm->adev, new_plane_state, tiling_flags,
5788                         &bundle->plane_infos[planes_count],
5789                         &bundle->flip_addrs[planes_count].address,
5790                         false);
5791 
5792                 DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
5793                                  new_plane_state->plane->index,
5794                                  bundle->plane_infos[planes_count].dcc.enable);
5795 
5796                 bundle->surface_updates[planes_count].plane_info =
5797                         &bundle->plane_infos[planes_count];
5798 
5799                 /*
5800                  * Only allow immediate flips for fast updates that don't
5801                  * change FB pitch, DCC state, rotation or mirroing.
5802                  */
5803                 bundle->flip_addrs[planes_count].flip_immediate =
5804                         crtc->state->async_flip &&
5805                         acrtc_state->update_type == UPDATE_TYPE_FAST;
5806 
5807                 timestamp_ns = ktime_get_ns();
5808                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5809                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5810                 bundle->surface_updates[planes_count].surface = dc_plane;
5811 
5812                 if (!bundle->surface_updates[planes_count].surface) {
5813                         DRM_ERROR("No surface for CRTC: id=%d\n",
5814                                         acrtc_attach->crtc_id);
5815                         continue;
5816                 }
5817 
5818                 if (plane == pcrtc->primary)
5819                         update_freesync_state_on_stream(
5820                                 dm,
5821                                 acrtc_state,
5822                                 acrtc_state->stream,
5823                                 dc_plane,
5824                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
5825 
5826                 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5827                                  __func__,
5828                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5829                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
5830 
5831                 planes_count += 1;
5832 
5833         }
5834 
5835         if (pflip_present) {
5836                 if (!vrr_active) {
5837                         /* Use old throttling in non-vrr fixed refresh rate mode
5838                          * to keep flip scheduling based on target vblank counts
5839                          * working in a backwards compatible way, e.g., for
5840                          * clients using the GLX_OML_sync_control extension or
5841                          * DRI3/Present extension with defined target_msc.
5842                          */
5843                         last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
5844                 }
5845                 else {
5846                         /* For variable refresh rate mode only:
5847                          * Get vblank of last completed flip to avoid > 1 vrr
5848                          * flips per video frame by use of throttling, but allow
5849                          * flip programming anywhere in the possibly large
5850                          * variable vrr vblank interval for fine-grained flip
5851                          * timing control and more opportunity to avoid stutter
5852                          * on late submission of flips.
5853                          */
5854                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5855                         last_flip_vblank = acrtc_attach->last_flip_vblank;
5856                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5857                 }
5858 
5859                 target_vblank = last_flip_vblank + wait_for_vblank;
5860 
5861                 /*
5862                  * Wait until we're out of the vertical blank period before the one
5863                  * targeted by the flip
5864                  */
5865                 while ((acrtc_attach->enabled &&
5866                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5867                                                             0, &vpos, &hpos, NULL,
5868                                                             NULL, &pcrtc->hwmode)
5869                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5870                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5871                         (int)(target_vblank -
5872                           amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5873                         usleep_range(1000, 1100);
5874                 }
5875 
5876                 if (acrtc_attach->base.state->event) {
5877                         drm_crtc_vblank_get(pcrtc);
5878 
5879                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5880 
5881                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5882                         prepare_flip_isr(acrtc_attach);
5883 
5884                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5885                 }
5886 
5887                 if (acrtc_state->stream) {
5888                         if (acrtc_state->freesync_vrr_info_changed)
5889                                 bundle->stream_update.vrr_infopacket =
5890                                         &acrtc_state->stream->vrr_infopacket;
5891                 }
5892         }
5893 
5894         /* Update the planes if changed or disable if we don't have any. */
5895         if ((planes_count || acrtc_state->active_planes == 0) &&
5896                 acrtc_state->stream) {
5897                 if (new_pcrtc_state->mode_changed) {
5898                         bundle->stream_update.src = acrtc_state->stream->src;
5899                         bundle->stream_update.dst = acrtc_state->stream->dst;
5900                 }
5901 
5902                 if (new_pcrtc_state->color_mgmt_changed) {
5903                         /*
5904                          * TODO: This isn't fully correct since we've actually
5905                          * already modified the stream in place.
5906                          */
5907                         bundle->stream_update.gamut_remap =
5908                                 &acrtc_state->stream->gamut_remap_matrix;
5909                         bundle->stream_update.output_csc_transform =
5910                                 &acrtc_state->stream->csc_color_matrix;
5911                         bundle->stream_update.out_transfer_func =
5912                                 acrtc_state->stream->out_transfer_func;
5913                 }
5914 
5915                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
5916                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
5917                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
5918 
5919                 /*
5920                  * If FreeSync state on the stream has changed then we need to
5921                  * re-adjust the min/max bounds now that DC doesn't handle this
5922                  * as part of commit.
5923                  */
5924                 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
5925                     amdgpu_dm_vrr_active(acrtc_state)) {
5926                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5927                         dc_stream_adjust_vmin_vmax(
5928                                 dm->dc, acrtc_state->stream,
5929                                 &acrtc_state->vrr_params.adjust);
5930                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5931                 }
5932 
5933                 mutex_lock(&dm->dc_lock);
5934                 dc_commit_updates_for_stream(dm->dc,
5935                                                      bundle->surface_updates,
5936                                                      planes_count,
5937                                                      acrtc_state->stream,
5938                                                      &bundle->stream_update,
5939                                                      dc_state);
5940                 mutex_unlock(&dm->dc_lock);
5941         }
5942 
5943         /*
5944          * Update cursor state *after* programming all the planes.
5945          * This avoids redundant programming in the case where we're going
5946          * to be disabling a single plane - those pipes are being disabled.
5947          */
5948         if (acrtc_state->active_planes)
5949                 amdgpu_dm_commit_cursors(state);
5950 
5951 cleanup:
5952         kfree(bundle);
5953 }
5954 
5955 static void amdgpu_dm_commit_audio(struct drm_device *dev,
5956                                    struct drm_atomic_state *state)
5957 {
5958         struct amdgpu_device *adev = dev->dev_private;
5959         struct amdgpu_dm_connector *aconnector;
5960         struct drm_connector *connector;
5961         struct drm_connector_state *old_con_state, *new_con_state;
5962         struct drm_crtc_state *new_crtc_state;
5963         struct dm_crtc_state *new_dm_crtc_state;
5964         const struct dc_stream_status *status;
5965         int i, inst;
5966 
5967         /* Notify device removals. */
5968         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5969                 if (old_con_state->crtc != new_con_state->crtc) {
5970                         /* CRTC changes require notification. */
5971                         goto notify;
5972                 }
5973 
5974                 if (!new_con_state->crtc)
5975                         continue;
5976 
5977                 new_crtc_state = drm_atomic_get_new_crtc_state(
5978                         state, new_con_state->crtc);
5979 
5980                 if (!new_crtc_state)
5981                         continue;
5982 
5983                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5984                         continue;
5985 
5986         notify:
5987                 aconnector = to_amdgpu_dm_connector(connector);
5988 
5989                 mutex_lock(&adev->dm.audio_lock);
5990                 inst = aconnector->audio_inst;
5991                 aconnector->audio_inst = -1;
5992                 mutex_unlock(&adev->dm.audio_lock);
5993 
5994                 amdgpu_dm_audio_eld_notify(adev, inst);
5995         }
5996 
5997         /* Notify audio device additions. */
5998         for_each_new_connector_in_state(state, connector, new_con_state, i) {
5999                 if (!new_con_state->crtc)
6000                         continue;
6001 
6002                 new_crtc_state = drm_atomic_get_new_crtc_state(
6003                         state, new_con_state->crtc);
6004 
6005                 if (!new_crtc_state)
6006                         continue;
6007 
6008                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6009                         continue;
6010 
6011                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6012                 if (!new_dm_crtc_state->stream)
6013                         continue;
6014 
6015                 status = dc_stream_get_status(new_dm_crtc_state->stream);
6016                 if (!status)
6017                         continue;
6018 
6019                 aconnector = to_amdgpu_dm_connector(connector);
6020 
6021                 mutex_lock(&adev->dm.audio_lock);
6022                 inst = status->audio_inst;
6023                 aconnector->audio_inst = inst;
6024                 mutex_unlock(&adev->dm.audio_lock);
6025 
6026                 amdgpu_dm_audio_eld_notify(adev, inst);
6027         }
6028 }
6029 
6030 /*
6031  * Enable interrupts on CRTCs that are newly active, undergone
6032  * a modeset, or have active planes again.
6033  *
6034  * Done in two passes, based on the for_modeset flag:
6035  * Pass 1: For CRTCs going through modeset
6036  * Pass 2: For CRTCs going from 0 to n active planes
6037  *
6038  * Interrupts can only be enabled after the planes are programmed,
6039  * so this requires a two-pass approach since we don't want to
6040  * just defer the interrupts until after commit planes every time.
6041  */
6042 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
6043                                              struct drm_atomic_state *state,
6044                                              bool for_modeset)
6045 {
6046         struct amdgpu_device *adev = dev->dev_private;
6047         struct drm_crtc *crtc;
6048         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6049         int i;
6050 #ifdef CONFIG_DEBUG_FS
6051         enum amdgpu_dm_pipe_crc_source source;
6052 #endif
6053 
6054         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6055                                       new_crtc_state, i) {
6056                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6057                 struct dm_crtc_state *dm_new_crtc_state =
6058                         to_dm_crtc_state(new_crtc_state);
6059                 struct dm_crtc_state *dm_old_crtc_state =
6060                         to_dm_crtc_state(old_crtc_state);
6061                 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
6062                 bool run_pass;
6063 
6064                 run_pass = (for_modeset && modeset) ||
6065                            (!for_modeset && !modeset &&
6066                             !dm_old_crtc_state->interrupts_enabled);
6067 
6068                 if (!run_pass)
6069                         continue;
6070 
6071                 if (!dm_new_crtc_state->interrupts_enabled)
6072                         continue;
6073 
6074                 manage_dm_interrupts(adev, acrtc, true);
6075 
6076 #ifdef CONFIG_DEBUG_FS
6077                 /* The stream has changed so CRC capture needs to re-enabled. */
6078                 source = dm_new_crtc_state->crc_src;
6079                 if (amdgpu_dm_is_valid_crc_source(source)) {
6080                         amdgpu_dm_crtc_configure_crc_source(
6081                                 crtc, dm_new_crtc_state,
6082                                 dm_new_crtc_state->crc_src);
6083                 }
6084 #endif
6085         }
6086 }
6087 
6088 /*
6089  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6090  * @crtc_state: the DRM CRTC state
6091  * @stream_state: the DC stream state.
6092  *
6093  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6094  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6095  */
6096 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6097                                                 struct dc_stream_state *stream_state)
6098 {
6099         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
6100 }
6101 
6102 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6103                                    struct drm_atomic_state *state,
6104                                    bool nonblock)
6105 {
6106         struct drm_crtc *crtc;
6107         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6108         struct amdgpu_device *adev = dev->dev_private;
6109         int i;
6110 
6111         /*
6112          * We evade vblank and pflip interrupts on CRTCs that are undergoing
6113          * a modeset, being disabled, or have no active planes.
6114          *
6115          * It's done in atomic commit rather than commit tail for now since
6116          * some of these interrupt handlers access the current CRTC state and
6117          * potentially the stream pointer itself.
6118          *
6119          * Since the atomic state is swapped within atomic commit and not within
6120          * commit tail this would leave to new state (that hasn't been committed yet)
6121          * being accesssed from within the handlers.
6122          *
6123          * TODO: Fix this so we can do this in commit tail and not have to block
6124          * in atomic check.
6125          */
6126         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6127                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6128                 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6129                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6130 
6131                 if (dm_old_crtc_state->interrupts_enabled &&
6132                     (!dm_new_crtc_state->interrupts_enabled ||
6133                      drm_atomic_crtc_needs_modeset(new_crtc_state)))
6134                         manage_dm_interrupts(adev, acrtc, false);
6135         }
6136         /*
6137          * Add check here for SoC's that support hardware cursor plane, to
6138          * unset legacy_cursor_update
6139          */
6140 
6141         return drm_atomic_helper_commit(dev, state, nonblock);
6142 
6143         /*TODO Handle EINTR, reenable IRQ*/
6144 }
6145 
6146 /**
6147  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6148  * @state: The atomic state to commit
6149  *
6150  * This will tell DC to commit the constructed DC state from atomic_check,
6151  * programming the hardware. Any failures here implies a hardware failure, since
6152  * atomic check should have filtered anything non-kosher.
6153  */
6154 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
6155 {
6156         struct drm_device *dev = state->dev;
6157         struct amdgpu_device *adev = dev->dev_private;
6158         struct amdgpu_display_manager *dm = &adev->dm;
6159         struct dm_atomic_state *dm_state;
6160         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
6161         uint32_t i, j;
6162         struct drm_crtc *crtc;
6163         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6164         unsigned long flags;
6165         bool wait_for_vblank = true;
6166         struct drm_connector *connector;
6167         struct drm_connector_state *old_con_state, *new_con_state;
6168         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6169         int crtc_disable_count = 0;
6170 
6171         drm_atomic_helper_update_legacy_modeset_state(dev, state);
6172 
6173         dm_state = dm_atomic_get_new_state(state);
6174         if (dm_state && dm_state->context) {
6175                 dc_state = dm_state->context;
6176         } else {
6177                 /* No state changes, retain current state. */
6178                 dc_state_temp = dc_create_state(dm->dc);
6179                 ASSERT(dc_state_temp);
6180                 dc_state = dc_state_temp;
6181                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
6182         }
6183 
6184         /* update changed items */
6185         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6186                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6187 
6188                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6189                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6190 
6191                 DRM_DEBUG_DRIVER(
6192                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6193                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6194                         "connectors_changed:%d\n",
6195                         acrtc->crtc_id,
6196                         new_crtc_state->enable,
6197                         new_crtc_state->active,
6198                         new_crtc_state->planes_changed,
6199                         new_crtc_state->mode_changed,
6200                         new_crtc_state->active_changed,
6201                         new_crtc_state->connectors_changed);
6202 
6203                 /* Copy all transient state flags into dc state */
6204                 if (dm_new_crtc_state->stream) {
6205                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6206                                                             dm_new_crtc_state->stream);
6207                 }
6208 
6209                 /* handles headless hotplug case, updating new_state and
6210                  * aconnector as needed
6211                  */
6212 
6213                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
6214 
6215                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
6216 
6217                         if (!dm_new_crtc_state->stream) {
6218                                 /*
6219                                  * this could happen because of issues with
6220                                  * userspace notifications delivery.
6221                                  * In this case userspace tries to set mode on
6222                                  * display which is disconnected in fact.
6223                                  * dc_sink is NULL in this case on aconnector.
6224                                  * We expect reset mode will come soon.
6225                                  *
6226                                  * This can also happen when unplug is done
6227                                  * during resume sequence ended
6228                                  *
6229                                  * In this case, we want to pretend we still
6230                                  * have a sink to keep the pipe running so that
6231                                  * hw state is consistent with the sw state
6232                                  */
6233                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6234                                                 __func__, acrtc->base.base.id);
6235                                 continue;
6236                         }
6237 
6238                         if (dm_old_crtc_state->stream)
6239                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6240 
6241                         pm_runtime_get_noresume(dev->dev);
6242 
6243                         acrtc->enabled = true;
6244                         acrtc->hw_mode = new_crtc_state->mode;
6245                         crtc->hwmode = new_crtc_state->mode;
6246                 } else if (modereset_required(new_crtc_state)) {
6247                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
6248 
6249                         /* i.e. reset mode */
6250                         if (dm_old_crtc_state->stream)
6251                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6252                 }
6253         } /* for_each_crtc_in_state() */
6254 
6255         if (dc_state) {
6256                 dm_enable_per_frame_crtc_master_sync(dc_state);
6257                 mutex_lock(&dm->dc_lock);
6258                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
6259                 mutex_unlock(&dm->dc_lock);
6260         }
6261 
6262         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6263                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6264 
6265                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6266 
6267                 if (dm_new_crtc_state->stream != NULL) {
6268                         const struct dc_stream_status *status =
6269                                         dc_stream_get_status(dm_new_crtc_state->stream);
6270 
6271                         if (!status)
6272                                 status = dc_stream_get_status_from_state(dc_state,
6273                                                                          dm_new_crtc_state->stream);
6274 
6275                         if (!status)
6276                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
6277                         else
6278                                 acrtc->otg_inst = status->primary_otg_inst;
6279                 }
6280         }
6281 
6282         /* Handle connector state changes */
6283         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6284                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6285                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6286                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6287                 struct dc_surface_update dummy_updates[MAX_SURFACES];
6288                 struct dc_stream_update stream_update;
6289                 struct dc_info_packet hdr_packet;
6290                 struct dc_stream_status *status = NULL;
6291                 bool abm_changed, hdr_changed, scaling_changed;
6292 
6293                 memset(&dummy_updates, 0, sizeof(dummy_updates));
6294                 memset(&stream_update, 0, sizeof(stream_update));
6295 
6296                 if (acrtc) {
6297                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6298                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6299                 }
6300 
6301                 /* Skip any modesets/resets */
6302                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
6303                         continue;
6304 
6305                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6306                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6307 
6308                 scaling_changed = is_scaling_state_different(dm_new_con_state,
6309                                                              dm_old_con_state);
6310 
6311                 abm_changed = dm_new_crtc_state->abm_level !=
6312                               dm_old_crtc_state->abm_level;
6313 
6314                 hdr_changed =
6315                         is_hdr_metadata_different(old_con_state, new_con_state);
6316 
6317                 if (!scaling_changed && !abm_changed && !hdr_changed)
6318                         continue;
6319 
6320                 if (scaling_changed) {
6321                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
6322                                         dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
6323 
6324                         stream_update.src = dm_new_crtc_state->stream->src;
6325                         stream_update.dst = dm_new_crtc_state->stream->dst;
6326                 }
6327 
6328                 if (abm_changed) {
6329                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
6330 
6331                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
6332                 }
6333 
6334                 if (hdr_changed) {
6335                         fill_hdr_info_packet(new_con_state, &hdr_packet);
6336                         stream_update.hdr_static_metadata = &hdr_packet;
6337                 }
6338 
6339                 status = dc_stream_get_status(dm_new_crtc_state->stream);
6340                 WARN_ON(!status);
6341                 WARN_ON(!status->plane_count);
6342 
6343                 /*
6344                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
6345                  * Here we create an empty update on each plane.
6346                  * To fix this, DC should permit updating only stream properties.
6347                  */
6348                 for (j = 0; j < status->plane_count; j++)
6349                         dummy_updates[j].surface = status->plane_states[0];
6350 
6351 
6352                 mutex_lock(&dm->dc_lock);
6353                 dc_commit_updates_for_stream(dm->dc,
6354                                                      dummy_updates,
6355                                                      status->plane_count,
6356                                                      dm_new_crtc_state->stream,
6357                                                      &stream_update,
6358                                                      dc_state);
6359                 mutex_unlock(&dm->dc_lock);
6360         }
6361 
6362         /* Count number of newly disabled CRTCs for dropping PM refs later. */
6363         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6364                                       new_crtc_state, i) {
6365                 if (old_crtc_state->active && !new_crtc_state->active)
6366                         crtc_disable_count++;
6367 
6368                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6369                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6370 
6371                 /* Update freesync active state. */
6372                 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6373 
6374                 /* Handle vrr on->off / off->on transitions */
6375                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6376                                                 dm_new_crtc_state);
6377         }
6378 
6379         /* Enable interrupts for CRTCs going through a modeset. */
6380         amdgpu_dm_enable_crtc_interrupts(dev, state, true);
6381 
6382         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
6383                 if (new_crtc_state->async_flip)
6384                         wait_for_vblank = false;
6385 
6386         /* update planes when needed per crtc*/
6387         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
6388                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6389 
6390                 if (dm_new_crtc_state->stream)
6391                         amdgpu_dm_commit_planes(state, dc_state, dev,
6392                                                 dm, crtc, wait_for_vblank);
6393         }
6394 
6395         /* Enable interrupts for CRTCs going from 0 to n active planes. */
6396         amdgpu_dm_enable_crtc_interrupts(dev, state, false);
6397 
6398         /* Update audio instances for each connector. */
6399         amdgpu_dm_commit_audio(dev, state);
6400 
6401         /*
6402          * send vblank event on all events not handled in flip and
6403          * mark consumed event for drm_atomic_helper_commit_hw_done
6404          */
6405         spin_lock_irqsave(&adev->ddev->event_lock, flags);
6406         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6407 
6408                 if (new_crtc_state->event)
6409                         drm_send_event_locked(dev, &new_crtc_state->event->base);
6410 
6411                 new_crtc_state->event = NULL;
6412         }
6413         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6414 
6415         /* Signal HW programming completion */
6416         drm_atomic_helper_commit_hw_done(state);
6417 
6418         if (wait_for_vblank)
6419                 drm_atomic_helper_wait_for_flip_done(dev, state);
6420 
6421         drm_atomic_helper_cleanup_planes(dev, state);
6422 
6423         /*
6424          * Finally, drop a runtime PM reference for each newly disabled CRTC,
6425          * so we can put the GPU into runtime suspend if we're not driving any
6426          * displays anymore
6427          */
6428         for (i = 0; i < crtc_disable_count; i++)
6429                 pm_runtime_put_autosuspend(dev->dev);
6430         pm_runtime_mark_last_busy(dev->dev);
6431 
6432         if (dc_state_temp)
6433                 dc_release_state(dc_state_temp);
6434 }
6435 
6436 
6437 static int dm_force_atomic_commit(struct drm_connector *connector)
6438 {
6439         int ret = 0;
6440         struct drm_device *ddev = connector->dev;
6441         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
6442         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6443         struct drm_plane *plane = disconnected_acrtc->base.primary;
6444         struct drm_connector_state *conn_state;
6445         struct drm_crtc_state *crtc_state;
6446         struct drm_plane_state *plane_state;
6447 
6448         if (!state)
6449                 return -ENOMEM;
6450 
6451         state->acquire_ctx = ddev->mode_config.acquire_ctx;
6452 
6453         /* Construct an atomic state to restore previous display setting */
6454 
6455         /*
6456          * Attach connectors to drm_atomic_state
6457          */
6458         conn_state = drm_atomic_get_connector_state(state, connector);
6459 
6460         ret = PTR_ERR_OR_ZERO(conn_state);
6461         if (ret)
6462                 goto err;
6463 
6464         /* Attach crtc to drm_atomic_state*/
6465         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
6466 
6467         ret = PTR_ERR_OR_ZERO(crtc_state);
6468         if (ret)
6469                 goto err;
6470 
6471         /* force a restore */
6472         crtc_state->mode_changed = true;
6473 
6474         /* Attach plane to drm_atomic_state */
6475         plane_state = drm_atomic_get_plane_state(state, plane);
6476 
6477         ret = PTR_ERR_OR_ZERO(plane_state);
6478         if (ret)
6479                 goto err;
6480 
6481 
6482         /* Call commit internally with the state we just constructed */
6483         ret = drm_atomic_commit(state);
6484         if (!ret)
6485                 return 0;
6486 
6487 err:
6488         DRM_ERROR("Restoring old state failed with %i\n", ret);
6489         drm_atomic_state_put(state);
6490 
6491         return ret;
6492 }
6493 
6494 /*
6495  * This function handles all cases when set mode does not come upon hotplug.
6496  * This includes when a display is unplugged then plugged back into the
6497  * same port and when running without usermode desktop manager supprot
6498  */
6499 void dm_restore_drm_connector_state(struct drm_device *dev,
6500                                     struct drm_connector *connector)
6501 {
6502         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6503         struct amdgpu_crtc *disconnected_acrtc;
6504         struct dm_crtc_state *acrtc_state;
6505 
6506         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
6507                 return;
6508 
6509         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
6510         if (!disconnected_acrtc)
6511                 return;
6512 
6513         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
6514         if (!acrtc_state->stream)
6515                 return;
6516 
6517         /*
6518          * If the previous sink is not released and different from the current,
6519          * we deduce we are in a state where we can not rely on usermode call
6520          * to turn on the display, so we do it here
6521          */
6522         if (acrtc_state->stream->sink != aconnector->dc_sink)
6523                 dm_force_atomic_commit(&aconnector->base);
6524 }
6525 
6526 /*
6527  * Grabs all modesetting locks to serialize against any blocking commits,
6528  * Waits for completion of all non blocking commits.
6529  */
6530 static int do_aquire_global_lock(struct drm_device *dev,
6531                                  struct drm_atomic_state *state)
6532 {
6533         struct drm_crtc *crtc;
6534         struct drm_crtc_commit *commit;
6535         long ret;
6536 
6537         /*
6538          * Adding all modeset locks to aquire_ctx will
6539          * ensure that when the framework release it the
6540          * extra locks we are locking here will get released to
6541          */
6542         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6543         if (ret)
6544                 return ret;
6545 
6546         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6547                 spin_lock(&crtc->commit_lock);
6548                 commit = list_first_entry_or_null(&crtc->commit_list,
6549                                 struct drm_crtc_commit, commit_entry);
6550                 if (commit)
6551                         drm_crtc_commit_get(commit);
6552                 spin_unlock(&crtc->commit_lock);
6553 
6554                 if (!commit)
6555                         continue;
6556 
6557                 /*
6558                  * Make sure all pending HW programming completed and
6559                  * page flips done
6560                  */
6561                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6562 
6563                 if (ret > 0)
6564                         ret = wait_for_completion_interruptible_timeout(
6565                                         &commit->flip_done, 10*HZ);
6566 
6567                 if (ret == 0)
6568                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
6569                                   "timed out\n", crtc->base.id, crtc->name);
6570 
6571                 drm_crtc_commit_put(commit);
6572         }
6573 
6574         return ret < 0 ? ret : 0;
6575 }
6576 
6577 static void get_freesync_config_for_crtc(
6578         struct dm_crtc_state *new_crtc_state,
6579         struct dm_connector_state *new_con_state)
6580 {
6581         struct mod_freesync_config config = {0};
6582         struct amdgpu_dm_connector *aconnector =
6583                         to_amdgpu_dm_connector(new_con_state->base.connector);
6584         struct drm_display_mode *mode = &new_crtc_state->base.mode;
6585         int vrefresh = drm_mode_vrefresh(mode);
6586 
6587         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
6588                                         vrefresh >= aconnector->min_vfreq &&
6589                                         vrefresh <= aconnector->max_vfreq;
6590 
6591         if (new_crtc_state->vrr_supported) {
6592                 new_crtc_state->stream->ignore_msa_timing_param = true;
6593                 config.state = new_crtc_state->base.vrr_enabled ?
6594                                 VRR_STATE_ACTIVE_VARIABLE :
6595                                 VRR_STATE_INACTIVE;
6596                 config.min_refresh_in_uhz =
6597                                 aconnector->min_vfreq * 1000000;
6598                 config.max_refresh_in_uhz =
6599                                 aconnector->max_vfreq * 1000000;
6600                 config.vsif_supported = true;
6601                 config.btr = true;
6602         }
6603 
6604         new_crtc_state->freesync_config = config;
6605 }
6606 
6607 static void reset_freesync_config_for_crtc(
6608         struct dm_crtc_state *new_crtc_state)
6609 {
6610         new_crtc_state->vrr_supported = false;
6611 
6612         memset(&new_crtc_state->vrr_params, 0,
6613                sizeof(new_crtc_state->vrr_params));
6614         memset(&new_crtc_state->vrr_infopacket, 0,
6615                sizeof(new_crtc_state->vrr_infopacket));
6616 }
6617 
6618 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6619                                 struct drm_atomic_state *state,
6620                                 struct drm_crtc *crtc,
6621                                 struct drm_crtc_state *old_crtc_state,
6622                                 struct drm_crtc_state *new_crtc_state,
6623                                 bool enable,
6624                                 bool *lock_and_validation_needed)
6625 {
6626         struct dm_atomic_state *dm_state = NULL;
6627         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6628         struct dc_stream_state *new_stream;
6629         int ret = 0;
6630 
6631         /*
6632          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6633          * update changed items
6634          */
6635         struct amdgpu_crtc *acrtc = NULL;
6636         struct amdgpu_dm_connector *aconnector = NULL;
6637         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6638         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
6639 
6640         new_stream = NULL;
6641 
6642         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6643         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6644         acrtc = to_amdgpu_crtc(crtc);
6645         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
6646 
6647         /* TODO This hack should go away */
6648         if (aconnector && enable) {
6649                 /* Make sure fake sink is created in plug-in scenario */
6650                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6651                                                             &aconnector->base);
6652                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6653                                                             &aconnector->base);
6654 
6655                 if (IS_ERR(drm_new_conn_state)) {
6656                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6657                         goto fail;
6658                 }
6659 
6660                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6661                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
6662 
6663                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6664                         goto skip_modeset;
6665 
6666                 new_stream = create_stream_for_sink(aconnector,
6667                                                      &new_crtc_state->mode,
6668                                                     dm_new_conn_state,
6669                                                     dm_old_crtc_state->stream);
6670 
6671                 /*
6672                  * we can have no stream on ACTION_SET if a display
6673                  * was disconnected during S3, in this case it is not an
6674                  * error, the OS will be updated after detection, and
6675                  * will do the right thing on next atomic commit
6676                  */
6677 
6678                 if (!new_stream) {
6679                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6680                                         __func__, acrtc->base.base.id);
6681                         ret = -ENOMEM;
6682                         goto fail;
6683                 }
6684 
6685                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6686 
6687                 ret = fill_hdr_info_packet(drm_new_conn_state,
6688                                            &new_stream->hdr_static_metadata);
6689                 if (ret)
6690                         goto fail;
6691 
6692                 /*
6693                  * If we already removed the old stream from the context
6694                  * (and set the new stream to NULL) then we can't reuse
6695                  * the old stream even if the stream and scaling are unchanged.
6696                  * We'll hit the BUG_ON and black screen.
6697                  *
6698                  * TODO: Refactor this function to allow this check to work
6699                  * in all conditions.
6700                  */
6701                 if (dm_new_crtc_state->stream &&
6702                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
6703                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6704                         new_crtc_state->mode_changed = false;
6705                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6706                                          new_crtc_state->mode_changed);
6707                 }
6708         }
6709 
6710         /* mode_changed flag may get updated above, need to check again */
6711         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6712                 goto skip_modeset;
6713 
6714         DRM_DEBUG_DRIVER(
6715                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6716                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6717                 "connectors_changed:%d\n",
6718                 acrtc->crtc_id,
6719                 new_crtc_state->enable,
6720                 new_crtc_state->active,
6721                 new_crtc_state->planes_changed,
6722                 new_crtc_state->mode_changed,
6723                 new_crtc_state->active_changed,
6724                 new_crtc_state->connectors_changed);
6725 
6726         /* Remove stream for any changed/disabled CRTC */
6727         if (!enable) {
6728 
6729                 if (!dm_old_crtc_state->stream)
6730                         goto skip_modeset;
6731 
6732                 ret = dm_atomic_get_state(state, &dm_state);
6733                 if (ret)
6734                         goto fail;
6735 
6736                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6737                                 crtc->base.id);
6738 
6739                 /* i.e. reset mode */
6740                 if (dc_remove_stream_from_ctx(
6741                                 dm->dc,
6742                                 dm_state->context,
6743                                 dm_old_crtc_state->stream) != DC_OK) {
6744                         ret = -EINVAL;
6745                         goto fail;
6746                 }
6747 
6748                 dc_stream_release(dm_old_crtc_state->stream);
6749                 dm_new_crtc_state->stream = NULL;
6750 
6751                 reset_freesync_config_for_crtc(dm_new_crtc_state);
6752 
6753                 *lock_and_validation_needed = true;
6754 
6755         } else {/* Add stream for any updated/enabled CRTC */
6756                 /*
6757                  * Quick fix to prevent NULL pointer on new_stream when
6758                  * added MST connectors not found in existing crtc_state in the chained mode
6759                  * TODO: need to dig out the root cause of that
6760                  */
6761                 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6762                         goto skip_modeset;
6763 
6764                 if (modereset_required(new_crtc_state))
6765                         goto skip_modeset;
6766 
6767                 if (modeset_required(new_crtc_state, new_stream,
6768                                      dm_old_crtc_state->stream)) {
6769 
6770                         WARN_ON(dm_new_crtc_state->stream);
6771 
6772                         ret = dm_atomic_get_state(state, &dm_state);
6773                         if (ret)
6774                                 goto fail;
6775 
6776                         dm_new_crtc_state->stream = new_stream;
6777 
6778                         dc_stream_retain(new_stream);
6779 
6780                         DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6781                                                 crtc->base.id);
6782 
6783                         if (dc_add_stream_to_ctx(
6784                                         dm->dc,
6785                                         dm_state->context,
6786                                         dm_new_crtc_state->stream) != DC_OK) {
6787                                 ret = -EINVAL;
6788                                 goto fail;
6789                         }
6790 
6791                         *lock_and_validation_needed = true;
6792                 }
6793         }
6794 
6795 skip_modeset:
6796         /* Release extra reference */
6797         if (new_stream)
6798                  dc_stream_release(new_stream);
6799 
6800         /*
6801          * We want to do dc stream updates that do not require a
6802          * full modeset below.
6803          */
6804         if (!(enable && aconnector && new_crtc_state->enable &&
6805               new_crtc_state->active))
6806                 return 0;
6807         /*
6808          * Given above conditions, the dc state cannot be NULL because:
6809          * 1. We're in the process of enabling CRTCs (just been added
6810          *    to the dc context, or already is on the context)
6811          * 2. Has a valid connector attached, and
6812          * 3. Is currently active and enabled.
6813          * => The dc stream state currently exists.
6814          */
6815         BUG_ON(dm_new_crtc_state->stream == NULL);
6816 
6817         /* Scaling or underscan settings */
6818         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6819                 update_stream_scaling_settings(
6820                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
6821 
6822         /* ABM settings */
6823         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6824 
6825         /*
6826          * Color management settings. We also update color properties
6827          * when a modeset is needed, to ensure it gets reprogrammed.
6828          */
6829         if (dm_new_crtc_state->base.color_mgmt_changed ||
6830             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
6831                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
6832                 if (ret)
6833                         goto fail;
6834         }
6835 
6836         /* Update Freesync settings. */
6837         get_freesync_config_for_crtc(dm_new_crtc_state,
6838                                      dm_new_conn_state);
6839 
6840         return ret;
6841 
6842 fail:
6843         if (new_stream)
6844                 dc_stream_release(new_stream);
6845         return ret;
6846 }
6847 
6848 static bool should_reset_plane(struct drm_atomic_state *state,
6849                                struct drm_plane *plane,
6850                                struct drm_plane_state *old_plane_state,
6851                                struct drm_plane_state *new_plane_state)
6852 {
6853         struct drm_plane *other;
6854         struct drm_plane_state *old_other_state, *new_other_state;
6855         struct drm_crtc_state *new_crtc_state;
6856         int i;
6857 
6858         /*
6859          * TODO: Remove this hack once the checks below are sufficient
6860          * enough to determine when we need to reset all the planes on
6861          * the stream.
6862          */
6863         if (state->allow_modeset)
6864                 return true;
6865 
6866         /* Exit early if we know that we're adding or removing the plane. */
6867         if (old_plane_state->crtc != new_plane_state->crtc)
6868                 return true;
6869 
6870         /* old crtc == new_crtc == NULL, plane not in context. */
6871         if (!new_plane_state->crtc)
6872                 return false;
6873 
6874         new_crtc_state =
6875                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
6876 
6877         if (!new_crtc_state)
6878                 return true;
6879 
6880         /* CRTC Degamma changes currently require us to recreate planes. */
6881         if (new_crtc_state->color_mgmt_changed)
6882                 return true;
6883 
6884         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
6885                 return true;
6886 
6887         /*
6888          * If there are any new primary or overlay planes being added or
6889          * removed then the z-order can potentially change. To ensure
6890          * correct z-order and pipe acquisition the current DC architecture
6891          * requires us to remove and recreate all existing planes.
6892          *
6893          * TODO: Come up with a more elegant solution for this.
6894          */
6895         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6896                 if (other->type == DRM_PLANE_TYPE_CURSOR)
6897                         continue;
6898 
6899                 if (old_other_state->crtc != new_plane_state->crtc &&
6900                     new_other_state->crtc != new_plane_state->crtc)
6901                         continue;
6902 
6903                 if (old_other_state->crtc != new_other_state->crtc)
6904                         return true;
6905 
6906                 /* TODO: Remove this once we can handle fast format changes. */
6907                 if (old_other_state->fb && new_other_state->fb &&
6908                     old_other_state->fb->format != new_other_state->fb->format)
6909                         return true;
6910         }
6911 
6912         return false;
6913 }
6914 
6915 static int dm_update_plane_state(struct dc *dc,
6916                                  struct drm_atomic_state *state,
6917                                  struct drm_plane *plane,
6918                                  struct drm_plane_state *old_plane_state,
6919                                  struct drm_plane_state *new_plane_state,
6920                                  bool enable,
6921                                  bool *lock_and_validation_needed)
6922 {
6923 
6924         struct dm_atomic_state *dm_state = NULL;
6925         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6926         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6927         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
6928         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
6929         struct amdgpu_crtc *new_acrtc;
6930         bool needs_reset;
6931         int ret = 0;
6932 
6933 
6934         new_plane_crtc = new_plane_state->crtc;
6935         old_plane_crtc = old_plane_state->crtc;
6936         dm_new_plane_state = to_dm_plane_state(new_plane_state);
6937         dm_old_plane_state = to_dm_plane_state(old_plane_state);
6938 
6939         /*TODO Implement better atomic check for cursor plane */
6940         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
6941                 if (!enable || !new_plane_crtc ||
6942                         drm_atomic_plane_disabling(plane->state, new_plane_state))
6943                         return 0;
6944 
6945                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
6946 
6947                 if ((new_plane_state->crtc_w > new_acrtc->max_cursor_width) ||
6948                         (new_plane_state->crtc_h > new_acrtc->max_cursor_height)) {
6949                         DRM_DEBUG_ATOMIC("Bad cursor size %d x %d\n",
6950                                                          new_plane_state->crtc_w, new_plane_state->crtc_h);
6951                         return -EINVAL;
6952                 }
6953 
6954                 return 0;
6955         }
6956 
6957         needs_reset = should_reset_plane(state, plane, old_plane_state,
6958                                          new_plane_state);
6959 
6960         /* Remove any changed/removed planes */
6961         if (!enable) {
6962                 if (!needs_reset)
6963                         return 0;
6964 
6965                 if (!old_plane_crtc)
6966                         return 0;
6967 
6968                 old_crtc_state = drm_atomic_get_old_crtc_state(
6969                                 state, old_plane_crtc);
6970                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6971 
6972                 if (!dm_old_crtc_state->stream)
6973                         return 0;
6974 
6975                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
6976                                 plane->base.id, old_plane_crtc->base.id);
6977 
6978                 ret = dm_atomic_get_state(state, &dm_state);
6979                 if (ret)
6980                         return ret;
6981 
6982                 if (!dc_remove_plane_from_context(
6983                                 dc,
6984                                 dm_old_crtc_state->stream,
6985                                 dm_old_plane_state->dc_state,
6986                                 dm_state->context)) {
6987 
6988                         ret = EINVAL;
6989                         return ret;
6990                 }
6991 
6992 
6993                 dc_plane_state_release(dm_old_plane_state->dc_state);
6994                 dm_new_plane_state->dc_state = NULL;
6995 
6996                 *lock_and_validation_needed = true;
6997 
6998         } else { /* Add new planes */
6999                 struct dc_plane_state *dc_new_plane_state;
7000 
7001                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
7002                         return 0;
7003 
7004                 if (!new_plane_crtc)
7005                         return 0;
7006 
7007                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
7008                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7009 
7010                 if (!dm_new_crtc_state->stream)
7011                         return 0;
7012 
7013                 if (!needs_reset)
7014                         return 0;
7015 
7016                 WARN_ON(dm_new_plane_state->dc_state);
7017 
7018                 dc_new_plane_state = dc_create_plane_state(dc);
7019                 if (!dc_new_plane_state)
7020                         return -ENOMEM;
7021 
7022                 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
7023                                 plane->base.id, new_plane_crtc->base.id);
7024 
7025                 ret = fill_dc_plane_attributes(
7026                         new_plane_crtc->dev->dev_private,
7027                         dc_new_plane_state,
7028                         new_plane_state,
7029                         new_crtc_state);
7030                 if (ret) {
7031                         dc_plane_state_release(dc_new_plane_state);
7032                         return ret;
7033                 }
7034 
7035                 ret = dm_atomic_get_state(state, &dm_state);
7036                 if (ret) {
7037                         dc_plane_state_release(dc_new_plane_state);
7038                         return ret;
7039                 }
7040 
7041                 /*
7042                  * Any atomic check errors that occur after this will
7043                  * not need a release. The plane state will be attached
7044                  * to the stream, and therefore part of the atomic
7045                  * state. It'll be released when the atomic state is
7046                  * cleaned.
7047                  */
7048                 if (!dc_add_plane_to_context(
7049                                 dc,
7050                                 dm_new_crtc_state->stream,
7051                                 dc_new_plane_state,
7052                                 dm_state->context)) {
7053 
7054                         dc_plane_state_release(dc_new_plane_state);
7055                         return -EINVAL;
7056                 }
7057 
7058                 dm_new_plane_state->dc_state = dc_new_plane_state;
7059 
7060                 /* Tell DC to do a full surface update every time there
7061                  * is a plane change. Inefficient, but works for now.
7062                  */
7063                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
7064 
7065                 *lock_and_validation_needed = true;
7066         }
7067 
7068 
7069         return ret;
7070 }
7071 
7072 static int
7073 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
7074                                     struct drm_atomic_state *state,
7075                                     enum surface_update_type *out_type)
7076 {
7077         struct dc *dc = dm->dc;
7078         struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
7079         int i, j, num_plane, ret = 0;
7080         struct drm_plane_state *old_plane_state, *new_plane_state;
7081         struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
7082         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
7083         struct drm_plane *plane;
7084 
7085         struct drm_crtc *crtc;
7086         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7087         struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7088         struct dc_stream_status *status = NULL;
7089 
7090         struct dc_surface_update *updates;
7091         enum surface_update_type update_type = UPDATE_TYPE_FAST;
7092 
7093         updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
7094 
7095         if (!updates) {
7096                 DRM_ERROR("Failed to allocate plane updates\n");
7097                 /* Set type to FULL to avoid crashing in DC*/
7098                 update_type = UPDATE_TYPE_FULL;
7099                 goto cleanup;
7100         }
7101 
7102         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7103                 struct dc_scaling_info scaling_info;
7104                 struct dc_stream_update stream_update;
7105 
7106                 memset(&stream_update, 0, sizeof(stream_update));
7107 
7108                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7109                 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7110                 num_plane = 0;
7111 
7112                 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7113                         update_type = UPDATE_TYPE_FULL;
7114                         goto cleanup;
7115                 }
7116 
7117                 if (!new_dm_crtc_state->stream)
7118                         continue;
7119 
7120                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
7121                         const struct amdgpu_framebuffer *amdgpu_fb =
7122                                 to_amdgpu_framebuffer(new_plane_state->fb);
7123                         struct dc_plane_info plane_info;
7124                         struct dc_flip_addrs flip_addr;
7125                         uint64_t tiling_flags;
7126 
7127                         new_plane_crtc = new_plane_state->crtc;
7128                         old_plane_crtc = old_plane_state->crtc;
7129                         new_dm_plane_state = to_dm_plane_state(new_plane_state);
7130                         old_dm_plane_state = to_dm_plane_state(old_plane_state);
7131 
7132                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7133                                 continue;
7134 
7135                         if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7136                                 update_type = UPDATE_TYPE_FULL;
7137                                 goto cleanup;
7138                         }
7139 
7140                         if (crtc != new_plane_crtc)
7141                                 continue;
7142 
7143                         updates[num_plane].surface = new_dm_plane_state->dc_state;
7144 
7145                         if (new_crtc_state->mode_changed) {
7146                                 stream_update.dst = new_dm_crtc_state->stream->dst;
7147                                 stream_update.src = new_dm_crtc_state->stream->src;
7148                         }
7149 
7150                         if (new_crtc_state->color_mgmt_changed) {
7151                                 updates[num_plane].gamma =
7152                                                 new_dm_plane_state->dc_state->gamma_correction;
7153                                 updates[num_plane].in_transfer_func =
7154                                                 new_dm_plane_state->dc_state->in_transfer_func;
7155                                 stream_update.gamut_remap =
7156                                                 &new_dm_crtc_state->stream->gamut_remap_matrix;
7157                                 stream_update.output_csc_transform =
7158                                                 &new_dm_crtc_state->stream->csc_color_matrix;
7159                                 stream_update.out_transfer_func =
7160                                                 new_dm_crtc_state->stream->out_transfer_func;
7161                         }
7162 
7163                         ret = fill_dc_scaling_info(new_plane_state,
7164                                                    &scaling_info);
7165                         if (ret)
7166                                 goto cleanup;
7167 
7168                         updates[num_plane].scaling_info = &scaling_info;
7169 
7170                         if (amdgpu_fb) {
7171                                 ret = get_fb_info(amdgpu_fb, &tiling_flags);
7172                                 if (ret)
7173                                         goto cleanup;
7174 
7175                                 memset(&flip_addr, 0, sizeof(flip_addr));
7176 
7177                                 ret = fill_dc_plane_info_and_addr(
7178                                         dm->adev, new_plane_state, tiling_flags,
7179                                         &plane_info,
7180                                         &flip_addr.address,
7181                                         false);
7182                                 if (ret)
7183                                         goto cleanup;
7184 
7185                                 updates[num_plane].plane_info = &plane_info;
7186                                 updates[num_plane].flip_addr = &flip_addr;
7187                         }
7188 
7189                         num_plane++;
7190                 }
7191 
7192                 if (num_plane == 0)
7193                         continue;
7194 
7195                 ret = dm_atomic_get_state(state, &dm_state);
7196                 if (ret)
7197                         goto cleanup;
7198 
7199                 old_dm_state = dm_atomic_get_old_state(state);
7200                 if (!old_dm_state) {
7201                         ret = -EINVAL;
7202                         goto cleanup;
7203                 }
7204 
7205                 status = dc_stream_get_status_from_state(old_dm_state->context,
7206                                                          new_dm_crtc_state->stream);
7207 
7208                 /*
7209                  * TODO: DC modifies the surface during this call so we need
7210                  * to lock here - find a way to do this without locking.
7211                  */
7212                 mutex_lock(&dm->dc_lock);
7213                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
7214                                                                   &stream_update, status);
7215                 mutex_unlock(&dm->dc_lock);
7216 
7217                 if (update_type > UPDATE_TYPE_MED) {
7218                         update_type = UPDATE_TYPE_FULL;
7219                         goto cleanup;
7220                 }
7221         }
7222 
7223 cleanup:
7224         kfree(updates);
7225 
7226         *out_type = update_type;
7227         return ret;
7228 }
7229 
7230 /**
7231  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7232  * @dev: The DRM device
7233  * @state: The atomic state to commit
7234  *
7235  * Validate that the given atomic state is programmable by DC into hardware.
7236  * This involves constructing a &struct dc_state reflecting the new hardware
7237  * state we wish to commit, then querying DC to see if it is programmable. It's
7238  * important not to modify the existing DC state. Otherwise, atomic_check
7239  * may unexpectedly commit hardware changes.
7240  *
7241  * When validating the DC state, it's important that the right locks are
7242  * acquired. For full updates case which removes/adds/updates streams on one
7243  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7244  * that any such full update commit will wait for completion of any outstanding
7245  * flip using DRMs synchronization events. See
7246  * dm_determine_update_type_for_commit()
7247  *
7248  * Note that DM adds the affected connectors for all CRTCs in state, when that
7249  * might not seem necessary. This is because DC stream creation requires the
7250  * DC sink, which is tied to the DRM connector state. Cleaning this up should
7251  * be possible but non-trivial - a possible TODO item.
7252  *
7253  * Return: -Error code if validation failed.
7254  */
7255 static int amdgpu_dm_atomic_check(struct drm_device *dev,
7256                                   struct drm_atomic_state *state)
7257 {
7258         struct amdgpu_device *adev = dev->dev_private;
7259         struct dm_atomic_state *dm_state = NULL;
7260         struct dc *dc = adev->dm.dc;
7261         struct drm_connector *connector;
7262         struct drm_connector_state *old_con_state, *new_con_state;
7263         struct drm_crtc *crtc;
7264         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7265         struct drm_plane *plane;
7266         struct drm_plane_state *old_plane_state, *new_plane_state;
7267         enum surface_update_type update_type = UPDATE_TYPE_FAST;
7268         enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7269 
7270         int ret, i;
7271 
7272         /*
7273          * This bool will be set for true for any modeset/reset
7274          * or plane update which implies non fast surface update.
7275          */
7276         bool lock_and_validation_needed = false;
7277 
7278         ret = drm_atomic_helper_check_modeset(dev, state);
7279         if (ret)
7280                 goto fail;
7281 
7282         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7283                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
7284                     !new_crtc_state->color_mgmt_changed &&
7285                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
7286                         continue;
7287 
7288                 if (!new_crtc_state->enable)
7289                         continue;
7290 
7291                 ret = drm_atomic_add_affected_connectors(state, crtc);
7292                 if (ret)
7293                         return ret;
7294 
7295                 ret = drm_atomic_add_affected_planes(state, crtc);
7296                 if (ret)
7297                         goto fail;
7298         }
7299 
7300         /*
7301          * Add all primary and overlay planes on the CRTC to the state
7302          * whenever a plane is enabled to maintain correct z-ordering
7303          * and to enable fast surface updates.
7304          */
7305         drm_for_each_crtc(crtc, dev) {
7306                 bool modified = false;
7307 
7308                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7309                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7310                                 continue;
7311 
7312                         if (new_plane_state->crtc == crtc ||
7313                             old_plane_state->crtc == crtc) {
7314                                 modified = true;
7315                                 break;
7316                         }
7317                 }
7318 
7319                 if (!modified)
7320                         continue;
7321 
7322                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
7323                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
7324                                 continue;
7325 
7326                         new_plane_state =
7327                                 drm_atomic_get_plane_state(state, plane);
7328 
7329                         if (IS_ERR(new_plane_state)) {
7330                                 ret = PTR_ERR(new_plane_state);
7331                                 goto fail;
7332                         }
7333                 }
7334         }
7335 
7336         /* Remove exiting planes if they are modified */
7337         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7338                 ret = dm_update_plane_state(dc, state, plane,
7339                                             old_plane_state,
7340                                             new_plane_state,
7341                                             false,
7342                                             &lock_and_validation_needed);
7343                 if (ret)
7344                         goto fail;
7345         }
7346 
7347         /* Disable all crtcs which require disable */
7348         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7349                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7350                                            old_crtc_state,
7351                                            new_crtc_state,
7352                                            false,
7353                                            &lock_and_validation_needed);
7354                 if (ret)
7355                         goto fail;
7356         }
7357 
7358         /* Enable all crtcs which require enable */
7359         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7360                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7361                                            old_crtc_state,
7362                                            new_crtc_state,
7363                                            true,
7364                                            &lock_and_validation_needed);
7365                 if (ret)
7366                         goto fail;
7367         }
7368 
7369         /* Add new/modified planes */
7370         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7371                 ret = dm_update_plane_state(dc, state, plane,
7372                                             old_plane_state,
7373                                             new_plane_state,
7374                                             true,
7375                                             &lock_and_validation_needed);
7376                 if (ret)
7377                         goto fail;
7378         }
7379 
7380         /* Run this here since we want to validate the streams we created */
7381         ret = drm_atomic_helper_check_planes(dev, state);
7382         if (ret)
7383                 goto fail;
7384 
7385         if (state->legacy_cursor_update) {
7386                 /*
7387                  * This is a fast cursor update coming from the plane update
7388                  * helper, check if it can be done asynchronously for better
7389                  * performance.
7390                  */
7391                 state->async_update =
7392                         !drm_atomic_helper_async_check(dev, state);
7393 
7394                 /*
7395                  * Skip the remaining global validation if this is an async
7396                  * update. Cursor updates can be done without affecting
7397                  * state or bandwidth calcs and this avoids the performance
7398                  * penalty of locking the private state object and
7399                  * allocating a new dc_state.
7400                  */
7401                 if (state->async_update)
7402                         return 0;
7403         }
7404 
7405         /* Check scaling and underscan changes*/
7406         /* TODO Removed scaling changes validation due to inability to commit
7407          * new stream into context w\o causing full reset. Need to
7408          * decide how to handle.
7409          */
7410         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
7411                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
7412                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
7413                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
7414 
7415                 /* Skip any modesets/resets */
7416                 if (!acrtc || drm_atomic_crtc_needs_modeset(
7417                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
7418                         continue;
7419 
7420                 /* Skip any thing not scale or underscan changes */
7421                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
7422                         continue;
7423 
7424                 overall_update_type = UPDATE_TYPE_FULL;
7425                 lock_and_validation_needed = true;
7426         }
7427 
7428         ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
7429         if (ret)
7430                 goto fail;
7431 
7432         if (overall_update_type < update_type)
7433                 overall_update_type = update_type;
7434 
7435         /*
7436          * lock_and_validation_needed was an old way to determine if we need to set
7437          * the global lock. Leaving it in to check if we broke any corner cases
7438          * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
7439          * lock_and_validation_needed false = UPDATE_TYPE_FAST
7440          */
7441         if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
7442                 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
7443 
7444         if (overall_update_type > UPDATE_TYPE_FAST) {
7445                 ret = dm_atomic_get_state(state, &dm_state);
7446                 if (ret)
7447                         goto fail;
7448 
7449                 ret = do_aquire_global_lock(dev, state);
7450                 if (ret)
7451                         goto fail;
7452 
7453                 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
7454                         ret = -EINVAL;
7455                         goto fail;
7456                 }
7457         } else {
7458                 /*
7459                  * The commit is a fast update. Fast updates shouldn't change
7460                  * the DC context, affect global validation, and can have their
7461                  * commit work done in parallel with other commits not touching
7462                  * the same resource. If we have a new DC context as part of
7463                  * the DM atomic state from validation we need to free it and
7464                  * retain the existing one instead.
7465                  */
7466                 struct dm_atomic_state *new_dm_state, *old_dm_state;
7467 
7468                 new_dm_state = dm_atomic_get_new_state(state);
7469                 old_dm_state = dm_atomic_get_old_state(state);
7470 
7471                 if (new_dm_state && old_dm_state) {
7472                         if (new_dm_state->context)
7473                                 dc_release_state(new_dm_state->context);
7474 
7475                         new_dm_state->context = old_dm_state->context;
7476 
7477                         if (old_dm_state->context)
7478                                 dc_retain_state(old_dm_state->context);
7479                 }
7480         }
7481 
7482         /* Store the overall update type for use later in atomic check. */
7483         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
7484                 struct dm_crtc_state *dm_new_crtc_state =
7485                         to_dm_crtc_state(new_crtc_state);
7486 
7487                 dm_new_crtc_state->update_type = (int)overall_update_type;
7488         }
7489 
7490         /* Must be success */
7491         WARN_ON(ret);
7492         return ret;
7493 
7494 fail:
7495         if (ret == -EDEADLK)
7496                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
7497         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
7498                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
7499         else
7500                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
7501 
7502         return ret;
7503 }
7504 
7505 static bool is_dp_capable_without_timing_msa(struct dc *dc,
7506                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
7507 {
7508         uint8_t dpcd_data;
7509         bool capable = false;
7510 
7511         if (amdgpu_dm_connector->dc_link &&
7512                 dm_helpers_dp_read_dpcd(
7513                                 NULL,
7514                                 amdgpu_dm_connector->dc_link,
7515                                 DP_DOWN_STREAM_PORT_COUNT,
7516                                 &dpcd_data,
7517                                 sizeof(dpcd_data))) {
7518                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
7519         }
7520 
7521         return capable;
7522 }
7523 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
7524                                         struct edid *edid)
7525 {
7526         int i;
7527         bool edid_check_required;
7528         struct detailed_timing *timing;
7529         struct detailed_non_pixel *data;
7530         struct detailed_data_monitor_range *range;
7531         struct amdgpu_dm_connector *amdgpu_dm_connector =
7532                         to_amdgpu_dm_connector(connector);
7533         struct dm_connector_state *dm_con_state = NULL;
7534 
7535         struct drm_device *dev = connector->dev;
7536         struct amdgpu_device *adev = dev->dev_private;
7537         bool freesync_capable = false;
7538 
7539         if (!connector->state) {
7540                 DRM_ERROR("%s - Connector has no state", __func__);
7541                 goto update;
7542         }
7543 
7544         if (!edid) {
7545                 dm_con_state = to_dm_connector_state(connector->state);
7546 
7547                 amdgpu_dm_connector->min_vfreq = 0;
7548                 amdgpu_dm_connector->max_vfreq = 0;
7549                 amdgpu_dm_connector->pixel_clock_mhz = 0;
7550 
7551                 goto update;
7552         }
7553 
7554         dm_con_state = to_dm_connector_state(connector->state);
7555 
7556         edid_check_required = false;
7557         if (!amdgpu_dm_connector->dc_sink) {
7558                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
7559                 goto update;
7560         }
7561         if (!adev->dm.freesync_module)
7562                 goto update;
7563         /*
7564          * if edid non zero restrict freesync only for dp and edp
7565          */
7566         if (edid) {
7567                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
7568                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
7569                         edid_check_required = is_dp_capable_without_timing_msa(
7570                                                 adev->dm.dc,
7571                                                 amdgpu_dm_connector);
7572                 }
7573         }
7574         if (edid_check_required == true && (edid->version > 1 ||
7575            (edid->version == 1 && edid->revision > 1))) {
7576                 for (i = 0; i < 4; i++) {
7577 
7578                         timing  = &edid->detailed_timings[i];
7579                         data    = &timing->data.other_data;
7580                         range   = &data->data.range;
7581                         /*
7582                          * Check if monitor has continuous frequency mode
7583                          */
7584                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
7585                                 continue;
7586                         /*
7587                          * Check for flag range limits only. If flag == 1 then
7588                          * no additional timing information provided.
7589                          * Default GTF, GTF Secondary curve and CVT are not
7590                          * supported
7591                          */
7592                         if (range->flags != 1)
7593                                 continue;
7594 
7595                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
7596                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
7597                         amdgpu_dm_connector->pixel_clock_mhz =
7598                                 range->pixel_clock_mhz * 10;
7599                         break;
7600                 }
7601 
7602                 if (amdgpu_dm_connector->max_vfreq -
7603                     amdgpu_dm_connector->min_vfreq > 10) {
7604 
7605                         freesync_capable = true;
7606                 }
7607         }
7608 
7609 update:
7610         if (dm_con_state)
7611                 dm_con_state->freesync_capable = freesync_capable;
7612 
7613         if (connector->vrr_capable_property)
7614                 drm_connector_set_vrr_capable_property(connector,
7615                                                        freesync_capable);
7616 }
7617
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

DEFINITIONS
