root/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c

DEFINITIONS

1. smu9_is_smc_ram_running
2. smu9_wait_for_response
3. smu9_send_msg_to_smc_without_waiting
4. smu9_send_msg_to_smc
5. smu9_send_msg_to_smc_with_parameter
6. smu9_get_argument

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 
  24 #include "smumgr.h"
  25 #include "vega10_inc.h"
  26 #include "soc15_common.h"
  27 #include "pp_debug.h"
  28 
  29 
  30 /* MP Apertures */
  31 #define MP0_Public                  0x03800000
  32 #define MP0_SRAM                    0x03900000
  33 #define MP1_Public                  0x03b00000
  34 #define MP1_SRAM                    0x03c00004
  35 
  36 #define smnMP1_FIRMWARE_FLAGS                                                                           0x3010028
  37 
  38 bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr)
  39 {
  40         struct amdgpu_device *adev = hwmgr->adev;
  41         uint32_t mp1_fw_flags;
  42 
  43         mp1_fw_flags = RREG32_PCIE(MP1_Public |
  44                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
  45 
  46         if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
  47                 return true;
  48 
  49         return false;
  50 }
  51 
  52 /*
  53  * Check if SMC has responded to previous message.
  54  *
  55  * @param    smumgr  the address of the powerplay hardware manager.
  56  * @return   TRUE    SMC has responded, FALSE otherwise.
  57  */
  58 static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)
  59 {
  60         struct amdgpu_device *adev = hwmgr->adev;
  61         uint32_t reg;
  62         uint32_t ret;
  63 
  64         reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
  65 
  66         ret = phm_wait_for_register_unequal(hwmgr, reg,
  67                         0, MP1_C2PMSG_90__CONTENT_MASK);
  68 
  69         if (ret)
  70                 pr_err("No response from smu\n");
  71 
  72         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  73 }
  74 
  75 /*
  76  * Send a message to the SMC, and do not wait for its response.
  77  * @param    smumgr  the address of the powerplay hardware manager.
  78  * @param    msg the message to send.
  79  * @return   Always return 0.
  80  */
  81 static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
  82                                                 uint16_t msg)
  83 {
  84         struct amdgpu_device *adev = hwmgr->adev;
  85 
  86         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  87 
  88         return 0;
  89 }
  90 
  91 /*
  92  * Send a message to the SMC, and wait for its response.
  93  * @param    hwmgr  the address of the powerplay hardware manager.
  94  * @param    msg the message to send.
  95  * @return   Always return 0.
  96  */
  97 int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
  98 {
  99         struct amdgpu_device *adev = hwmgr->adev;
 100         uint32_t ret;
 101 
 102         smu9_wait_for_response(hwmgr);
 103 
 104         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 105 
 106         smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
 107 
 108         ret = smu9_wait_for_response(hwmgr);
 109         if (ret != 1)
 110                 pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret);
 111 
 112         return 0;
 113 }
 114 
 115 /*
 116  * Send a message to the SMC with parameter
 117  * @param    hwmgr:  the address of the powerplay hardware manager.
 118  * @param    msg: the message to send.
 119  * @param    parameter: the parameter to send
 120  * @return   Always return 0.
 121  */
 122 int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
 123                                         uint16_t msg, uint32_t parameter)
 124 {
 125         struct amdgpu_device *adev = hwmgr->adev;
 126         uint32_t ret;
 127 
 128         smu9_wait_for_response(hwmgr);
 129 
 130         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 131 
 132         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
 133 
 134         smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
 135 
 136         ret = smu9_wait_for_response(hwmgr);
 137         if (ret != 1)
 138                 pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret);
 139 
 140         return 0;
 141 }
 142 
 143 uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr)
 144 {
 145         struct amdgpu_device *adev = hwmgr->adev;
 146 
 147         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
 148 }