1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 #ifndef _VEGA10_POWERTUNE_H_
24 #define _VEGA10_POWERTUNE_H_
25
26 enum vega10_pt_config_reg_type {
27 VEGA10_CONFIGREG_MMR = 0,
28 VEGA10_CONFIGREG_SMC_IND,
29 VEGA10_CONFIGREG_DIDT_IND,
30 VEGA10_CONFIGREG_CACHE,
31 VEGA10_CONFIGREG_MAX
32 };
33
34 enum vega10_didt_config_reg_type {
35 VEGA10_CONFIGREG_DIDT = 0,
36 VEGA10_CONFIGREG_GCCAC,
37 VEGA10_CONFIGREG_SECAC
38 };
39
40
41 #define POWERCONTAINMENT_FEATURE_DTE 0x00000001
42 #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
43 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
44
45 struct vega10_pt_config_reg {
46 uint32_t offset;
47 uint32_t mask;
48 uint32_t shift;
49 uint32_t value;
50 enum vega10_pt_config_reg_type type;
51 };
52
53 struct vega10_didt_config_reg {
54 uint32_t offset;
55 uint32_t mask;
56 uint32_t shift;
57 uint32_t value;
58 };
59
60 struct vega10_pt_defaults {
61 uint8_t SviLoadLineEn;
62 uint8_t SviLoadLineVddC;
63 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
64 uint8_t TDC_MAWt;
65 uint8_t TdcWaterfallCtl;
66 uint8_t DTEAmbientTempBase;
67 };
68
69 void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
70 int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
71 int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
72 int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr);
73 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr);
74 int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
75 int vega10_power_control_set_level(struct pp_hwmgr *hwmgr);
76 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr);
77
78 int vega10_enable_didt_config(struct pp_hwmgr *hwmgr);
79 int vega10_disable_didt_config(struct pp_hwmgr *hwmgr);
80
81 #endif
82