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24 #ifndef SMU75_DISCRETE_H
25 #define SMU75_DISCRETE_H
26
27 #include "smu75.h"
28
29 #pragma pack(push, 1)
30
31 #define NUM_SCLK_RANGE 8
32
33 #define VCO_3_6 1
34 #define VCO_2_4 3
35
36 #define POSTDIV_DIV_BY_1 0
37 #define POSTDIV_DIV_BY_2 1
38 #define POSTDIV_DIV_BY_4 2
39 #define POSTDIV_DIV_BY_8 3
40 #define POSTDIV_DIV_BY_16 4
41
42 struct sclkFcwRange_t {
43 uint8_t vco_setting;
44 uint8_t postdiv;
45 uint16_t fcw_pcc;
46 uint16_t fcw_trans_upper;
47 uint16_t fcw_trans_lower;
48 };
49 typedef struct sclkFcwRange_t sclkFcwRange_t;
50
51 struct SMIO_Pattern {
52 uint16_t Voltage;
53 uint8_t Smio;
54 uint8_t padding;
55 };
56
57 typedef struct SMIO_Pattern SMIO_Pattern;
58
59 struct SMIO_Table {
60 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
61 };
62
63 typedef struct SMIO_Table SMIO_Table;
64
65 struct SMU_SclkSetting {
66 uint32_t SclkFrequency;
67 uint16_t Fcw_int;
68 uint16_t Fcw_frac;
69 uint16_t Pcc_fcw_int;
70 uint8_t PllRange;
71 uint8_t SSc_En;
72 uint16_t Sclk_slew_rate;
73 uint16_t Pcc_up_slew_rate;
74 uint16_t Pcc_down_slew_rate;
75 uint16_t Fcw1_int;
76 uint16_t Fcw1_frac;
77 uint16_t Sclk_ss_slew_rate;
78 };
79 typedef struct SMU_SclkSetting SMU_SclkSetting;
80
81 struct SMU75_Discrete_GraphicsLevel {
82 SMU_VoltageLevel MinVoltage;
83
84 uint8_t pcieDpmLevel;
85 uint8_t DeepSleepDivId;
86 uint16_t ActivityLevel;
87
88 uint32_t CgSpllFuncCntl3;
89 uint32_t CgSpllFuncCntl4;
90 uint32_t CcPwrDynRm;
91 uint32_t CcPwrDynRm1;
92
93 uint8_t SclkDid;
94 uint8_t padding;
95 uint8_t EnabledForActivity;
96 uint8_t EnabledForThrottle;
97 uint8_t UpHyst;
98 uint8_t DownHyst;
99 uint8_t VoltageDownHyst;
100 uint8_t PowerThrottle;
101
102 SMU_SclkSetting SclkSetting;
103
104 uint8_t ScksStretchThreshVid[NUM_SCKS_STATE_TYPES];
105 uint16_t Padding;
106 };
107
108 typedef struct SMU75_Discrete_GraphicsLevel SMU75_Discrete_GraphicsLevel;
109
110 struct SMU75_Discrete_ACPILevel {
111 uint32_t Flags;
112 SMU_VoltageLevel MinVoltage;
113 uint32_t SclkFrequency;
114 uint8_t SclkDid;
115 uint8_t DisplayWatermark;
116 uint8_t DeepSleepDivId;
117 uint8_t padding;
118 uint32_t CcPwrDynRm;
119 uint32_t CcPwrDynRm1;
120
121 SMU_SclkSetting SclkSetting;
122 };
123
124 typedef struct SMU75_Discrete_ACPILevel SMU75_Discrete_ACPILevel;
125
126 struct SMU75_Discrete_Ulv {
127 uint32_t CcPwrDynRm;
128 uint32_t CcPwrDynRm1;
129 uint16_t VddcOffset;
130 uint8_t VddcOffsetVid;
131 uint8_t VddcPhase;
132 uint16_t BifSclkDfs;
133 uint16_t Reserved;
134 };
135
136 typedef struct SMU75_Discrete_Ulv SMU75_Discrete_Ulv;
137
138 struct SMU75_Discrete_MemoryLevel {
139 SMU_VoltageLevel MinVoltage;
140 uint32_t MinMvdd;
141
142 uint32_t MclkFrequency;
143
144 uint8_t StutterEnable;
145 uint8_t EnabledForThrottle;
146 uint8_t EnabledForActivity;
147 uint8_t padding_0;
148
149 uint8_t UpHyst;
150 uint8_t DownHyst;
151 uint8_t VoltageDownHyst;
152 uint8_t padding_1;
153
154 uint16_t ActivityLevel;
155 uint8_t DisplayWatermark;
156 uint8_t padding_2;
157
158 uint16_t Fcw_int;
159 uint16_t Fcw_frac;
160 uint8_t Postdiv;
161 uint8_t padding_3[3];
162 };
163
164 typedef struct SMU75_Discrete_MemoryLevel SMU75_Discrete_MemoryLevel;
165
166 struct SMU75_Discrete_LinkLevel {
167 uint8_t PcieGenSpeed;
168 uint8_t PcieLaneCount;
169 uint8_t EnabledForActivity;
170 uint8_t SPC;
171 uint32_t DownThreshold;
172 uint32_t UpThreshold;
173 uint16_t BifSclkDfs;
174 uint16_t Reserved;
175 };
176
177 typedef struct SMU75_Discrete_LinkLevel SMU75_Discrete_LinkLevel;
178
179
180
181 struct SMU75_Discrete_MCArbDramTimingTableEntry {
182 uint32_t McArbDramTiming;
183 uint32_t McArbDramTiming2;
184 uint32_t McArbBurstTime;
185 uint32_t McArbRfshRate;
186 uint32_t McArbMisc3;
187 };
188
189 typedef struct SMU75_Discrete_MCArbDramTimingTableEntry SMU75_Discrete_MCArbDramTimingTableEntry;
190
191 struct SMU75_Discrete_MCArbDramTimingTable {
192 SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
193 };
194
195 typedef struct SMU75_Discrete_MCArbDramTimingTable SMU75_Discrete_MCArbDramTimingTable;
196
197
198 struct SMU75_Discrete_UvdLevel {
199 uint32_t VclkFrequency;
200 uint32_t DclkFrequency;
201 SMU_VoltageLevel MinVoltage;
202 uint8_t VclkDivider;
203 uint8_t DclkDivider;
204 uint8_t padding[2];
205 };
206
207 typedef struct SMU75_Discrete_UvdLevel SMU75_Discrete_UvdLevel;
208
209
210 struct SMU75_Discrete_ExtClkLevel {
211 uint32_t Frequency;
212 SMU_VoltageLevel MinVoltage;
213 uint8_t Divider;
214 uint8_t padding[3];
215 };
216
217 typedef struct SMU75_Discrete_ExtClkLevel SMU75_Discrete_ExtClkLevel;
218
219 struct SMU75_Discrete_StateInfo {
220 uint32_t SclkFrequency;
221 uint32_t MclkFrequency;
222 uint32_t VclkFrequency;
223 uint32_t DclkFrequency;
224 uint32_t SamclkFrequency;
225 uint32_t AclkFrequency;
226 uint32_t EclkFrequency;
227 uint16_t MvddVoltage;
228 uint16_t padding16;
229 uint8_t DisplayWatermark;
230 uint8_t McArbIndex;
231 uint8_t McRegIndex;
232 uint8_t SeqIndex;
233 uint8_t SclkDid;
234 int8_t SclkIndex;
235 int8_t MclkIndex;
236 uint8_t PCIeGen;
237 };
238
239 typedef struct SMU75_Discrete_StateInfo SMU75_Discrete_StateInfo;
240
241 struct SMU75_Discrete_DpmTable {
242 SMU75_PIDController GraphicsPIDController;
243 SMU75_PIDController MemoryPIDController;
244 SMU75_PIDController LinkPIDController;
245
246 uint32_t SystemFlags;
247
248 uint32_t VRConfig;
249 uint32_t SmioMask1;
250 uint32_t SmioMask2;
251 SMIO_Table SmioTable1;
252 SMIO_Table SmioTable2;
253
254 uint32_t MvddLevelCount;
255
256 uint8_t BapmVddcVidHiSidd [SMU75_MAX_LEVELS_VDDC];
257 uint8_t BapmVddcVidLoSidd [SMU75_MAX_LEVELS_VDDC];
258 uint8_t BapmVddcVidHiSidd2 [SMU75_MAX_LEVELS_VDDC];
259
260 uint8_t GraphicsDpmLevelCount;
261 uint8_t MemoryDpmLevelCount;
262 uint8_t LinkLevelCount;
263 uint8_t MasterDeepSleepControl;
264
265 uint8_t UvdLevelCount;
266 uint8_t VceLevelCount;
267 uint8_t AcpLevelCount;
268 uint8_t SamuLevelCount;
269
270 uint8_t ThermOutGpio;
271 uint8_t ThermOutPolarity;
272 uint8_t ThermOutMode;
273 uint8_t BootPhases;
274
275 uint8_t VRHotLevel;
276 uint8_t LdoRefSel;
277
278 uint8_t Reserved1[2];
279
280 uint16_t FanStartTemperature;
281 uint16_t FanStopTemperature;
282
283 uint16_t MaxVoltage;
284 uint16_t Reserved2;
285 uint32_t Reserved;
286
287 SMU75_Discrete_GraphicsLevel GraphicsLevel [SMU75_MAX_LEVELS_GRAPHICS];
288 SMU75_Discrete_MemoryLevel MemoryACPILevel;
289 SMU75_Discrete_MemoryLevel MemoryLevel [SMU75_MAX_LEVELS_MEMORY];
290 SMU75_Discrete_LinkLevel LinkLevel [SMU75_MAX_LEVELS_LINK];
291 SMU75_Discrete_ACPILevel ACPILevel;
292 SMU75_Discrete_UvdLevel UvdLevel [SMU75_MAX_LEVELS_UVD];
293 SMU75_Discrete_ExtClkLevel VceLevel [SMU75_MAX_LEVELS_VCE];
294 SMU75_Discrete_ExtClkLevel AcpLevel [SMU75_MAX_LEVELS_ACP];
295 SMU75_Discrete_ExtClkLevel SamuLevel [SMU75_MAX_LEVELS_SAMU];
296 SMU75_Discrete_Ulv Ulv;
297
298 uint8_t DisplayWatermark [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS];
299
300 uint32_t SclkStepSize;
301 uint32_t Smio [SMU75_MAX_ENTRIES_SMIO];
302
303 uint8_t UvdBootLevel;
304 uint8_t VceBootLevel;
305 uint8_t AcpBootLevel;
306 uint8_t SamuBootLevel;
307
308 uint8_t GraphicsBootLevel;
309 uint8_t GraphicsVoltageChangeEnable;
310 uint8_t GraphicsThermThrottleEnable;
311 uint8_t GraphicsInterval;
312
313 uint8_t VoltageInterval;
314 uint8_t ThermalInterval;
315 uint16_t TemperatureLimitHigh;
316
317 uint16_t TemperatureLimitLow;
318 uint8_t MemoryBootLevel;
319 uint8_t MemoryVoltageChangeEnable;
320
321 uint16_t BootMVdd;
322 uint8_t MemoryInterval;
323 uint8_t MemoryThermThrottleEnable;
324
325 uint16_t VoltageResponseTime;
326 uint16_t PhaseResponseTime;
327
328 uint8_t PCIeBootLinkLevel;
329 uint8_t PCIeGenInterval;
330 uint8_t DTEInterval;
331 uint8_t DTEMode;
332
333 uint8_t SVI2Enable;
334 uint8_t VRHotGpio;
335 uint8_t AcDcGpio;
336 uint8_t ThermGpio;
337
338 uint16_t PPM_PkgPwrLimit;
339 uint16_t PPM_TemperatureLimit;
340
341 uint16_t DefaultTdp;
342 uint16_t TargetTdp;
343
344 uint16_t FpsHighThreshold;
345 uint16_t FpsLowThreshold;
346
347 uint16_t BAPMTI_R [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
348 uint16_t BAPMTI_RC [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
349
350 uint16_t TemperatureLimitEdge;
351 uint16_t TemperatureLimitHotspot;
352
353 uint16_t BootVddc;
354 uint16_t BootVddci;
355
356 uint16_t FanGainEdge;
357 uint16_t FanGainHotspot;
358
359 uint32_t LowSclkInterruptThreshold;
360 uint32_t VddGfxReChkWait;
361
362 uint8_t ClockStretcherAmount;
363 uint8_t Sclk_CKS_masterEn0_7;
364 uint8_t Sclk_CKS_masterEn8_15;
365 uint8_t DPMFreezeAndForced;
366
367 uint8_t Sclk_voltageOffset[8];
368
369 SMU_ClockStretcherDataTable ClockStretcherDataTable;
370 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
371
372 uint32_t CurrSclkPllRange;
373 sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
374
375 GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
376 SMU_QuadraticCoeffs AVFSGB_FUSE_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
377 };
378
379 typedef struct SMU75_Discrete_DpmTable SMU75_Discrete_DpmTable;
380
381 struct SMU75_Discrete_FanTable {
382 uint16_t FdoMode;
383 int16_t TempMin;
384 int16_t TempMed;
385 int16_t TempMax;
386 int16_t Slope1;
387 int16_t Slope2;
388 int16_t FdoMin;
389 int16_t HystUp;
390 int16_t HystDown;
391 int16_t HystSlope;
392 int16_t TempRespLim;
393 int16_t TempCurr;
394 int16_t SlopeCurr;
395 int16_t PwmCurr;
396 uint32_t RefreshPeriod;
397 int16_t FdoMax;
398 uint8_t TempSrc;
399 int8_t Padding;
400 };
401
402 typedef struct SMU75_Discrete_FanTable SMU75_Discrete_FanTable;
403
404 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
405 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
406
407
408
409 struct SMU7_MclkDpmScoreboard {
410 uint32_t PercentageBusy;
411
412 int32_t PIDError;
413 int32_t PIDIntegral;
414 int32_t PIDOutput;
415
416 uint32_t SigmaDeltaAccum;
417 uint32_t SigmaDeltaOutput;
418 uint32_t SigmaDeltaLevel;
419
420 uint32_t UtilizationSetpoint;
421
422 uint8_t TdpClampMode;
423 uint8_t TdcClampMode;
424 uint8_t ThermClampMode;
425 uint8_t VoltageBusy;
426
427 int8_t CurrLevel;
428 int8_t TargLevel;
429 uint8_t LevelChangeInProgress;
430 uint8_t UpHyst;
431
432 uint8_t DownHyst;
433 uint8_t VoltageDownHyst;
434 uint8_t DpmEnable;
435 uint8_t DpmRunning;
436
437 uint8_t DpmForce;
438 uint8_t DpmForceLevel;
439 uint8_t padding2;
440 uint8_t McArbIndex;
441
442 uint32_t MinimumPerfMclk;
443
444 uint8_t AcpiReq;
445 uint8_t AcpiAck;
446 uint8_t MclkSwitchInProgress;
447 uint8_t MclkSwitchCritical;
448
449 uint8_t IgnoreVBlank;
450 uint8_t TargetMclkIndex;
451 uint8_t TargetMvddIndex;
452 uint8_t MclkSwitchResult;
453
454 uint16_t VbiFailureCount;
455 uint8_t VbiWaitCounter;
456 uint8_t EnabledLevelsChange;
457
458 uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_MEMORY];
459 uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_MEMORY];
460
461 void (*TargetStateCalculator)(uint8_t);
462 void (*SavedTargetStateCalculator)(uint8_t);
463
464 uint16_t AutoDpmInterval;
465 uint16_t AutoDpmRange;
466
467 uint16_t VbiTimeoutCount;
468 uint16_t MclkSwitchingTime;
469
470 uint8_t fastSwitch;
471 uint8_t Save_PIC_VDDGFX_EXIT;
472 uint8_t Save_PIC_VDDGFX_ENTER;
473 uint8_t VbiTimeout;
474
475 uint32_t HbmTempRegBackup;
476 };
477
478 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
479
480 struct SMU7_UlvScoreboard {
481 uint8_t EnterUlv;
482 uint8_t ExitUlv;
483 uint8_t UlvActive;
484 uint8_t WaitingForUlv;
485 uint8_t UlvEnable;
486 uint8_t UlvRunning;
487 uint8_t UlvMasterEnable;
488 uint8_t padding;
489 uint32_t UlvAbortedCount;
490 uint32_t UlvTimeStamp;
491 };
492
493 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
494
495 struct VddgfxSavedRegisters {
496 uint32_t GPU_DBG[3];
497 uint32_t MEC_BaseAddress_Hi;
498 uint32_t MEC_BaseAddress_Lo;
499 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
500 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
501 uint32_t CP_INT_CNTL;
502 };
503
504 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
505
506 struct SMU7_VddGfxScoreboard {
507 uint8_t VddGfxEnable;
508 uint8_t VddGfxActive;
509 uint8_t VPUResetOccured;
510 uint8_t padding;
511
512 uint32_t VddGfxEnteredCount;
513 uint32_t VddGfxAbortedCount;
514
515 uint32_t VddGfxVid;
516
517 VddgfxSavedRegisters SavedRegisters;
518 };
519
520 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
521
522 struct SMU7_TdcLimitScoreboard {
523 uint8_t Enable;
524 uint8_t Running;
525 uint16_t Alpha;
526 uint32_t FilteredIddc;
527 uint32_t IddcLimit;
528 uint32_t IddcHyst;
529 SMU7_HystController_Data HystControllerData;
530 };
531
532 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
533
534 struct SMU7_PkgPwrLimitScoreboard {
535 uint8_t Enable;
536 uint8_t Running;
537 uint16_t Alpha;
538 uint32_t FilteredPkgPwr;
539 uint32_t Limit;
540 uint32_t Hyst;
541 uint32_t LimitFromDriver;
542 uint8_t PowerSharingEnabled;
543 uint8_t PowerSharingCounter;
544 uint8_t PowerSharingINTEnabled;
545 uint8_t GFXActivityCounterEnabled;
546 uint32_t EnergyCount;
547 uint32_t PSACTCount;
548 uint8_t RollOverRequired;
549 uint8_t RollOverCount;
550 uint8_t padding[2];
551 SMU7_HystController_Data HystControllerData;
552 };
553
554 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
555
556 struct SMU7_BapmScoreboard {
557 uint32_t source_powers[SMU75_DTE_SOURCES];
558 uint32_t source_powers_last[SMU75_DTE_SOURCES];
559 int32_t entity_temperatures[SMU75_NUM_GPU_TES];
560 int32_t initial_entity_temperatures[SMU75_NUM_GPU_TES];
561 int32_t Limit;
562 int32_t Hyst;
563 int32_t therm_influence_coeff_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS * 2];
564 int32_t therm_node_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
565 uint16_t ConfigTDPPowerScalar;
566 uint16_t FanSpeedPowerScalar;
567 uint16_t OverDrivePowerScalar;
568 uint16_t OverDriveLimitScalar;
569 uint16_t FinalPowerScalar;
570 uint8_t VariantID;
571 uint8_t spare997;
572
573 SMU7_HystController_Data HystControllerData;
574
575 int32_t temperature_gradient_slope;
576 int32_t temperature_gradient;
577 uint32_t measured_temperature;
578 };
579
580
581 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
582
583 struct SMU7_AcpiScoreboard {
584 uint32_t SavedInterruptMask[2];
585 uint8_t LastACPIRequest;
586 uint8_t CgBifResp;
587 uint8_t RequestType;
588 uint8_t Padding;
589 SMU75_Discrete_ACPILevel D0Level;
590 };
591
592 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
593
594 struct SMU75_Discrete_PmFuses {
595 uint8_t BapmVddCVidHiSidd[8];
596
597 uint8_t BapmVddCVidLoSidd[8];
598
599 uint8_t VddCVid[8];
600
601 uint8_t SviLoadLineEn;
602 uint8_t SviLoadLineVddC;
603 uint8_t SviLoadLineTrimVddC;
604 uint8_t SviLoadLineOffsetVddC;
605
606 uint16_t TDC_VDDC_PkgLimit;
607 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
608 uint8_t TDC_MAWt;
609
610 uint8_t TdcWaterfallCtl;
611 uint8_t LPMLTemperatureMin;
612 uint8_t LPMLTemperatureMax;
613 uint8_t Reserved;
614
615 uint8_t LPMLTemperatureScaler[16];
616
617 int16_t FuzzyFan_ErrorSetDelta;
618 int16_t FuzzyFan_ErrorRateSetDelta;
619 int16_t FuzzyFan_PwmSetDelta;
620 uint16_t Reserved6;
621
622 uint8_t GnbLPML[16];
623
624 uint8_t GnbLPMLMaxVid;
625 uint8_t GnbLPMLMinVid;
626 uint8_t Reserved1[2];
627
628 uint16_t BapmVddCBaseLeakageHiSidd;
629 uint16_t BapmVddCBaseLeakageLoSidd;
630
631 uint16_t VFT_Temp[3];
632 uint8_t Version;
633 uint8_t padding;
634
635 SMU_QuadraticCoeffs VFT_ATE[3];
636
637 SMU_QuadraticCoeffs AVFS_GB;
638 SMU_QuadraticCoeffs ATE_ACBTC_GB;
639
640 SMU_QuadraticCoeffs P2V;
641
642 uint32_t PsmCharzFreq;
643
644 uint16_t InversionVoltage;
645 uint16_t PsmCharzTemp;
646
647 uint32_t EnabledAvfsModules;
648
649 SMU_QuadraticCoeffs BtcGbv_CksOff;
650 };
651
652 typedef struct SMU75_Discrete_PmFuses SMU75_Discrete_PmFuses;
653
654 struct SMU7_Discrete_Log_Header_Table {
655 uint32_t version;
656 uint32_t asic_id;
657 uint16_t flags;
658 uint16_t entry_size;
659 uint32_t total_size;
660 uint32_t num_of_entries;
661 uint8_t type;
662 uint8_t mode;
663 uint8_t filler_0[2];
664 uint32_t filler_1[2];
665 };
666
667 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
668
669 struct SMU7_Discrete_Log_Cntl {
670 uint8_t Enabled;
671 uint8_t Type;
672 uint8_t padding[2];
673 uint32_t BufferSize;
674 uint32_t SamplesLogged;
675 uint32_t SampleSize;
676 uint32_t AddrL;
677 uint32_t AddrH;
678 };
679
680 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
681
682 #if defined SMU__DGPU_ONLY
683 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
684 #endif
685
686
687 struct SMU7_Discrete_Cac_Collection_Table {
688 uint32_t temperature;
689 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
690 };
691
692 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
693
694 struct SMU7_Discrete_Cac_Verification_Table {
695 uint32_t VddcTotalPower;
696 uint32_t VddcLeakagePower;
697 uint32_t VddcConstantPower;
698 uint32_t VddcGfxDynamicPower;
699 uint32_t VddcUvdDynamicPower;
700 uint32_t VddcVceDynamicPower;
701 uint32_t VddcAcpDynamicPower;
702 uint32_t VddcPcieDynamicPower;
703 uint32_t VddcDceDynamicPower;
704 uint32_t VddcCurrent;
705 uint32_t VddcVoltage;
706 uint32_t VddciTotalPower;
707 uint32_t VddciLeakagePower;
708 uint32_t VddciConstantPower;
709 uint32_t VddciDynamicPower;
710 uint32_t Vddr1TotalPower;
711 uint32_t Vddr1LeakagePower;
712 uint32_t Vddr1ConstantPower;
713 uint32_t Vddr1DynamicPower;
714 uint32_t spare[4];
715 uint32_t temperature;
716 };
717
718 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
719
720 struct SMU7_Discrete_Pm_Status_Table {
721 int32_t T_meas_max[SMU75_THERMAL_INPUT_LOOP_COUNT];
722 int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
723
724 uint32_t I_calc_max;
725 uint32_t I_calc_acc;
726 uint32_t P_meas_acc;
727 uint32_t V_meas_load_acc;
728 uint32_t I_meas_acc;
729 uint32_t P_meas_acc_vddci;
730 uint32_t V_meas_load_acc_vddci;
731 uint32_t I_meas_acc_vddci;
732
733 uint16_t Sclk_dpm_residency[8];
734 uint16_t Uvd_dpm_residency[8];
735 uint16_t Vce_dpm_residency[8];
736 uint16_t Mclk_dpm_residency[4];
737
738 uint32_t P_roc_acc;
739 uint32_t PkgPwr_max;
740 uint32_t PkgPwr_acc;
741 uint32_t MclkSwitchingTime_max;
742 uint32_t MclkSwitchingTime_acc;
743 uint32_t FanPwm_acc;
744 uint32_t FanRpm_acc;
745 uint32_t Gfx_busy_acc;
746 uint32_t Mc_busy_acc;
747 uint32_t Fps_acc;
748
749 uint32_t AccCnt;
750 };
751
752 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
753
754 struct SMU7_Discrete_AutoWattMan_Status_Table {
755 int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
756 uint16_t Sclk_dpm_residency[8];
757 uint16_t Mclk_dpm_residency[4];
758 uint32_t TgpPwr_acc;
759 uint32_t Gfx_busy_acc;
760 uint32_t Mc_busy_acc;
761 uint32_t AccCnt;
762 };
763
764 typedef struct SMU7_Discrete_AutoWattMan_Status_Table SMU7_Discrete_AutoWattMan_Status_Table;
765
766 #define SMU7_MAX_GFX_CU_COUNT 24
767 #define SMU7_MIN_GFX_CU_COUNT 8
768 #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT 0
769 #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT)
770 #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT 16
771 #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_MASK (0xFFFF << SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT)
772
773 struct SMU7_GfxCuPgScoreboard {
774 uint8_t Enabled;
775 uint8_t WaterfallUp;
776 uint8_t WaterfallDown;
777 uint8_t WaterfallLimit;
778 uint8_t CurrMaxCu;
779 uint8_t TargMaxCu;
780 uint8_t ClampMode;
781 uint8_t Active;
782 uint8_t MaxSupportedCu;
783 uint8_t MinSupportedCu;
784 uint8_t PendingGfxCuHostInterrupt;
785 uint8_t LastFilteredMaxCuInteger;
786 uint16_t FilteredMaxCu;
787 uint16_t FilteredMaxCuAlpha;
788 uint16_t FilterResetCount;
789 uint16_t FilterResetCountLimit;
790 uint8_t ForceCu;
791 uint8_t ForceCuCount;
792 uint8_t AcModeMaxCu;
793 uint8_t DcModeMaxCu;
794 };
795
796 typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
797
798 #define SMU7_SCLK_CAC 0x561
799 #define SMU7_MCLK_CAC 0xF9
800 #define SMU7_VCLK_CAC 0x2DE
801 #define SMU7_DCLK_CAC 0x2DE
802 #define SMU7_ECLK_CAC 0x25E
803 #define SMU7_ACLK_CAC 0x25E
804 #define SMU7_SAMCLK_CAC 0x25E
805 #define SMU7_DISPCLK_CAC 0x100
806 #define SMU7_CAC_CONSTANT 0x2EE3430
807 #define SMU7_CAC_CONSTANT_SHIFT 18
808
809 #define SMU7_VDDCI_MCLK_CONST 1765
810 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16
811 #define SMU7_VDDCI_VDDCI_CONST 50958
812 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
813 #define SMU7_VDDCI_CONST 11781
814 #define SMU7_VDDCI_STROBE_PWR 1331
815
816 #define SMU7_VDDR1_CONST 693
817 #define SMU7_VDDR1_CAC_WEIGHT 20
818 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
819 #define SMU7_VDDR1_STROBE_PWR 512
820
821 #define SMU7_AREA_COEFF_UVD 0xA78
822 #define SMU7_AREA_COEFF_VCE 0x190A
823 #define SMU7_AREA_COEFF_ACP 0x22D1
824 #define SMU7_AREA_COEFF_SAMU 0x534
825
826 #define SMU7_THERM_OUT_MODE_DISABLE 0x0
827 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
828 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
829
830 #define SQ_Enable_MASK 0x1
831 #define SQ_IR_MASK 0x2
832 #define SQ_PCC_MASK 0x4
833 #define SQ_EDC_MASK 0x8
834
835 #define TCP_Enable_MASK 0x100
836 #define TCP_IR_MASK 0x200
837 #define TCP_PCC_MASK 0x400
838 #define TCP_EDC_MASK 0x800
839
840 #define TD_Enable_MASK 0x10000
841 #define TD_IR_MASK 0x20000
842 #define TD_PCC_MASK 0x40000
843 #define TD_EDC_MASK 0x80000
844
845 #define DB_Enable_MASK 0x1000000
846 #define DB_IR_MASK 0x2000000
847 #define DB_PCC_MASK 0x4000000
848 #define DB_EDC_MASK 0x8000000
849
850 #define SQ_Enable_SHIFT 0
851 #define SQ_IR_SHIFT 1
852 #define SQ_PCC_SHIFT 2
853 #define SQ_EDC_SHIFT 3
854
855 #define TCP_Enable_SHIFT 8
856 #define TCP_IR_SHIFT 9
857 #define TCP_PCC_SHIFT 10
858 #define TCP_EDC_SHIFT 11
859
860 #define TD_Enable_SHIFT 16
861 #define TD_IR_SHIFT 17
862 #define TD_PCC_SHIFT 18
863 #define TD_EDC_SHIFT 19
864
865 #define DB_Enable_SHIFT 24
866 #define DB_IR_SHIFT 25
867 #define DB_PCC_SHIFT 26
868 #define DB_EDC_SHIFT 27
869
870 #define PMFUSES_AVFSSIZE 104
871
872 #define BTCGB0_Vdroop_Enable_MASK 0x1
873 #define BTCGB1_Vdroop_Enable_MASK 0x2
874 #define AVFSGB0_Vdroop_Enable_MASK 0x4
875 #define AVFSGB1_Vdroop_Enable_MASK 0x8
876
877 #define BTCGB0_Vdroop_Enable_SHIFT 0
878 #define BTCGB1_Vdroop_Enable_SHIFT 1
879 #define AVFSGB0_Vdroop_Enable_SHIFT 2
880 #define AVFSGB1_Vdroop_Enable_SHIFT 3
881
882 #pragma pack(pop)
883
884
885 #endif
886