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22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
24
25 #include "amdgpu.h"
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
28 #include "dm_pp_smu.h"
29 #include "smu_types.h"
30
31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
34
35 struct smu_hw_power_state {
36 unsigned int magic;
37 };
38
39 struct smu_power_state;
40
41 enum smu_state_ui_label {
42 SMU_STATE_UI_LABEL_NONE,
43 SMU_STATE_UI_LABEL_BATTERY,
44 SMU_STATE_UI_TABEL_MIDDLE_LOW,
45 SMU_STATE_UI_LABEL_BALLANCED,
46 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
47 SMU_STATE_UI_LABEL_PERFORMANCE,
48 SMU_STATE_UI_LABEL_BACO,
49 };
50
51 enum smu_state_classification_flag {
52 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
53 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
54 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
55 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
56 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
57 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
58 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
59 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
60 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
61 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
62 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
63 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
64 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
65 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
67 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
68 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
69 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
70 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
71 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
72 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
73 };
74
75 struct smu_state_classification_block {
76 enum smu_state_ui_label ui_label;
77 enum smu_state_classification_flag flags;
78 int bios_index;
79 bool temporary_state;
80 bool to_be_deleted;
81 };
82
83 struct smu_state_pcie_block {
84 unsigned int lanes;
85 };
86
87 enum smu_refreshrate_source {
88 SMU_REFRESHRATE_SOURCE_EDID,
89 SMU_REFRESHRATE_SOURCE_EXPLICIT
90 };
91
92 struct smu_state_display_block {
93 bool disable_frame_modulation;
94 bool limit_refreshrate;
95 enum smu_refreshrate_source refreshrate_source;
96 int explicit_refreshrate;
97 int edid_refreshrate_index;
98 bool enable_vari_bright;
99 };
100
101 struct smu_state_memroy_block {
102 bool dll_off;
103 uint8_t m3arb;
104 uint8_t unused[3];
105 };
106
107 struct smu_state_software_algorithm_block {
108 bool disable_load_balancing;
109 bool enable_sleep_for_timestamps;
110 };
111
112 struct smu_temperature_range {
113 int min;
114 int max;
115 int edge_emergency_max;
116 int hotspot_min;
117 int hotspot_crit_max;
118 int hotspot_emergency_max;
119 int mem_min;
120 int mem_crit_max;
121 int mem_emergency_max;
122 };
123
124 struct smu_state_validation_block {
125 bool single_display_only;
126 bool disallow_on_dc;
127 uint8_t supported_power_levels;
128 };
129
130 struct smu_uvd_clocks {
131 uint32_t vclk;
132 uint32_t dclk;
133 };
134
135
136
137
138 struct smu_power_state {
139 uint32_t id;
140 struct list_head ordered_list;
141 struct list_head all_states_list;
142
143 struct smu_state_classification_block classification;
144 struct smu_state_validation_block validation;
145 struct smu_state_pcie_block pcie;
146 struct smu_state_display_block display;
147 struct smu_state_memroy_block memory;
148 struct smu_temperature_range temperatures;
149 struct smu_state_software_algorithm_block software;
150 struct smu_uvd_clocks uvd_clocks;
151 struct smu_hw_power_state hardware;
152 };
153
154 enum smu_power_src_type
155 {
156 SMU_POWER_SOURCE_AC,
157 SMU_POWER_SOURCE_DC,
158 SMU_POWER_SOURCE_COUNT,
159 };
160
161 enum smu_memory_pool_size
162 {
163 SMU_MEMORY_POOL_SIZE_ZERO = 0,
164 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
165 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
166 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
167 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
168 };
169
170 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
171 do { \
172 tables[table_id].size = s; \
173 tables[table_id].align = a; \
174 tables[table_id].domain = d; \
175 } while (0)
176
177 struct smu_table {
178 uint64_t size;
179 uint32_t align;
180 uint8_t domain;
181 uint64_t mc_address;
182 void *cpu_addr;
183 struct amdgpu_bo *bo;
184 };
185
186 enum smu_perf_level_designation {
187 PERF_LEVEL_ACTIVITY,
188 PERF_LEVEL_POWER_CONTAINMENT,
189 };
190
191 struct smu_performance_level {
192 uint32_t core_clock;
193 uint32_t memory_clock;
194 uint32_t vddc;
195 uint32_t vddci;
196 uint32_t non_local_mem_freq;
197 uint32_t non_local_mem_width;
198 };
199
200 struct smu_clock_info {
201 uint32_t min_mem_clk;
202 uint32_t max_mem_clk;
203 uint32_t min_eng_clk;
204 uint32_t max_eng_clk;
205 uint32_t min_bus_bandwidth;
206 uint32_t max_bus_bandwidth;
207 };
208
209 struct smu_bios_boot_up_values
210 {
211 uint32_t revision;
212 uint32_t gfxclk;
213 uint32_t uclk;
214 uint32_t socclk;
215 uint32_t dcefclk;
216 uint32_t eclk;
217 uint32_t vclk;
218 uint32_t dclk;
219 uint16_t vddc;
220 uint16_t vddci;
221 uint16_t mvddc;
222 uint16_t vdd_gfx;
223 uint8_t cooling_id;
224 uint32_t pp_table_id;
225 uint32_t format_revision;
226 uint32_t content_revision;
227 uint32_t fclk;
228 };
229
230 enum smu_table_id
231 {
232 SMU_TABLE_PPTABLE = 0,
233 SMU_TABLE_WATERMARKS,
234 SMU_TABLE_CUSTOM_DPM,
235 SMU_TABLE_DPMCLOCKS,
236 SMU_TABLE_AVFS,
237 SMU_TABLE_AVFS_PSM_DEBUG,
238 SMU_TABLE_AVFS_FUSE_OVERRIDE,
239 SMU_TABLE_PMSTATUSLOG,
240 SMU_TABLE_SMU_METRICS,
241 SMU_TABLE_DRIVER_SMU_CONFIG,
242 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
243 SMU_TABLE_OVERDRIVE,
244 SMU_TABLE_I2C_COMMANDS,
245 SMU_TABLE_PACE,
246 SMU_TABLE_COUNT,
247 };
248
249 struct smu_table_context
250 {
251 void *power_play_table;
252 uint32_t power_play_table_size;
253 void *hardcode_pptable;
254 unsigned long metrics_time;
255 void *metrics_table;
256 void *clocks_table;
257
258 void *max_sustainable_clocks;
259 struct smu_bios_boot_up_values boot_values;
260 void *driver_pptable;
261 struct smu_table *tables;
262 uint32_t table_count;
263 struct smu_table memory_pool;
264 uint8_t thermal_controller_type;
265 uint16_t TDPODLimit;
266
267 void *overdrive_table;
268 };
269
270 struct smu_dpm_context {
271 uint32_t dpm_context_size;
272 void *dpm_context;
273 void *golden_dpm_context;
274 bool enable_umd_pstate;
275 enum amd_dpm_forced_level dpm_level;
276 enum amd_dpm_forced_level saved_dpm_level;
277 enum amd_dpm_forced_level requested_dpm_level;
278 struct smu_power_state *dpm_request_power_state;
279 struct smu_power_state *dpm_current_power_state;
280 struct mclock_latency_table *mclk_latency_table;
281 };
282
283 struct smu_power_gate {
284 bool uvd_gated;
285 bool vce_gated;
286 bool vcn_gated;
287 };
288
289 struct smu_power_context {
290 void *power_context;
291 uint32_t power_context_size;
292 struct smu_power_gate power_gate;
293 };
294
295
296 #define SMU_FEATURE_MAX (64)
297 struct smu_feature
298 {
299 uint32_t feature_num;
300 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
301 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
302 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
303 struct mutex mutex;
304 };
305
306 struct smu_clocks {
307 uint32_t engine_clock;
308 uint32_t memory_clock;
309 uint32_t bus_bandwidth;
310 uint32_t engine_clock_in_sr;
311 uint32_t dcef_clock;
312 uint32_t dcef_clock_in_sr;
313 };
314
315 #define MAX_REGULAR_DPM_NUM 16
316 struct mclk_latency_entries {
317 uint32_t frequency;
318 uint32_t latency;
319 };
320 struct mclock_latency_table {
321 uint32_t count;
322 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
323 };
324
325 enum smu_baco_state
326 {
327 SMU_BACO_STATE_ENTER = 0,
328 SMU_BACO_STATE_EXIT,
329 };
330
331 struct smu_baco_context
332 {
333 struct mutex mutex;
334 uint32_t state;
335 bool platform_support;
336 };
337
338 #define WORKLOAD_POLICY_MAX 7
339 struct smu_context
340 {
341 struct amdgpu_device *adev;
342 struct amdgpu_irq_src *irq_source;
343
344 const struct smu_funcs *funcs;
345 const struct pptable_funcs *ppt_funcs;
346 struct mutex mutex;
347 struct mutex sensor_lock;
348 struct mutex metrics_lock;
349 uint64_t pool_size;
350
351 struct smu_table_context smu_table;
352 struct smu_dpm_context smu_dpm;
353 struct smu_power_context smu_power;
354 struct smu_feature smu_feature;
355 struct amd_pp_display_configuration *display_config;
356 struct smu_baco_context smu_baco;
357 void *od_settings;
358
359 uint32_t pstate_sclk;
360 uint32_t pstate_mclk;
361
362 bool od_enabled;
363 uint32_t power_limit;
364 uint32_t default_power_limit;
365
366
367 uint32_t ppt_offset_bytes;
368 uint32_t ppt_size_bytes;
369 uint8_t *ppt_start_addr;
370
371 bool support_power_containment;
372 bool disable_watermark;
373
374 #define WATERMARKS_EXIST (1 << 0)
375 #define WATERMARKS_LOADED (1 << 1)
376 uint32_t watermarks_bitmap;
377 uint32_t hard_min_uclk_req_from_dal;
378 bool disable_uclk_switch;
379
380 uint32_t workload_mask;
381 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
382 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
383 uint32_t power_profile_mode;
384 uint32_t default_power_profile_mode;
385 bool pm_enabled;
386
387 uint32_t smc_if_version;
388
389 };
390
391 struct pptable_funcs {
392 int (*alloc_dpm_context)(struct smu_context *smu);
393 int (*store_powerplay_table)(struct smu_context *smu);
394 int (*check_powerplay_table)(struct smu_context *smu);
395 int (*append_powerplay_table)(struct smu_context *smu);
396 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
397 int (*get_smu_clk_index)(struct smu_context *smu, uint32_t index);
398 int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
399 int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
400 int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
401 int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
402 int (*run_afll_btc)(struct smu_context *smu);
403 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
404 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
405 int (*set_default_dpm_table)(struct smu_context *smu);
406 int (*set_power_state)(struct smu_context *smu);
407 int (*populate_umd_state_clk)(struct smu_context *smu);
408 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
409 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
410 int (*set_default_od8_settings)(struct smu_context *smu);
411 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
412 int (*set_od_percentage)(struct smu_context *smu,
413 enum smu_clk_type clk_type,
414 uint32_t value);
415 int (*od_edit_dpm_table)(struct smu_context *smu,
416 enum PP_OD_DPM_TABLE_COMMAND type,
417 long *input, uint32_t size);
418 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
419 enum smu_clk_type clk_type,
420 struct
421 pp_clock_levels_with_latency
422 *clocks);
423 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
424 enum amd_pp_clock_type type,
425 struct
426 pp_clock_levels_with_voltage
427 *clocks);
428 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
429 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
430 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
431 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
432 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
433 void *data, uint32_t *size);
434 int (*pre_display_config_changed)(struct smu_context *smu);
435 int (*display_config_changed)(struct smu_context *smu);
436 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
437 int (*notify_smc_dispaly_config)(struct smu_context *smu);
438 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
439 int (*unforce_dpm_levels)(struct smu_context *smu);
440 int (*get_profiling_clk_mask)(struct smu_context *smu,
441 enum amd_dpm_forced_level level,
442 uint32_t *sclk_mask,
443 uint32_t *mclk_mask,
444 uint32_t *soc_mask);
445 int (*set_cpu_power_state)(struct smu_context *smu);
446 bool (*is_dpm_running)(struct smu_context *smu);
447 int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
448 int (*set_thermal_fan_table)(struct smu_context *smu);
449 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
450 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
451 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
452 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
453 int (*get_current_clk_freq_by_table)(struct smu_context *smu,
454 enum smu_clk_type clk_type,
455 uint32_t *value);
456 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
457 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
458 int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
459 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
460 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
461 void (*dump_pptable)(struct smu_context *smu);
462 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
463 int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max);
464 };
465
466 struct smu_funcs
467 {
468 int (*init_microcode)(struct smu_context *smu);
469 int (*init_smc_tables)(struct smu_context *smu);
470 int (*fini_smc_tables)(struct smu_context *smu);
471 int (*init_power)(struct smu_context *smu);
472 int (*fini_power)(struct smu_context *smu);
473 int (*load_microcode)(struct smu_context *smu);
474 int (*check_fw_status)(struct smu_context *smu);
475 int (*setup_pptable)(struct smu_context *smu);
476 int (*get_vbios_bootup_values)(struct smu_context *smu);
477 int (*get_clk_info_from_vbios)(struct smu_context *smu);
478 int (*check_pptable)(struct smu_context *smu);
479 int (*parse_pptable)(struct smu_context *smu);
480 int (*populate_smc_tables)(struct smu_context *smu);
481 int (*check_fw_version)(struct smu_context *smu);
482 int (*powergate_sdma)(struct smu_context *smu, bool gate);
483 int (*powergate_vcn)(struct smu_context *smu, bool gate);
484 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
485 int (*write_pptable)(struct smu_context *smu);
486 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
487 int (*set_tool_table_location)(struct smu_context *smu);
488 int (*notify_memory_pool_location)(struct smu_context *smu);
489 int (*write_watermarks_table)(struct smu_context *smu);
490 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
491 int (*system_features_control)(struct smu_context *smu, bool en);
492 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
493 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
494 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
495 int (*init_display_count)(struct smu_context *smu, uint32_t count);
496 int (*set_allowed_mask)(struct smu_context *smu);
497 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
498 int (*notify_display_change)(struct smu_context *smu);
499 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
500 int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
501 int (*init_max_sustainable_clocks)(struct smu_context *smu);
502 int (*start_thermal_control)(struct smu_context *smu);
503 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
504 void *data, uint32_t *size);
505 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
506 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
507 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
508 bool cc6_disable, bool pstate_disable,
509 bool pstate_switch_disable);
510 int (*get_clock_by_type)(struct smu_context *smu,
511 enum amd_pp_clock_type type,
512 struct amd_pp_clocks *clocks);
513 int (*get_max_high_clocks)(struct smu_context *smu,
514 struct amd_pp_simple_clock_info *clocks);
515 int (*display_clock_voltage_request)(struct smu_context *smu, struct
516 pp_display_clock_request
517 *clock_req);
518 int (*get_dal_power_level)(struct smu_context *smu,
519 struct amd_pp_simple_clock_info *clocks);
520 int (*get_perf_level)(struct smu_context *smu,
521 enum smu_perf_level_designation designation,
522 struct smu_performance_level *level);
523 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
524 struct smu_clock_info *clocks);
525 int (*notify_smu_enable_pwe)(struct smu_context *smu);
526 int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
527 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
528 int (*conv_power_profile_to_pplib_workload)(int power_profile);
529 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
530 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
531 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
532 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
533 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
534 int (*gfx_off_control)(struct smu_context *smu, bool enable);
535 int (*register_irq_handler)(struct smu_context *smu);
536 int (*set_azalia_d3_pme)(struct smu_context *smu);
537 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
538 bool (*baco_is_support)(struct smu_context *smu);
539 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
540 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
541 int (*baco_reset)(struct smu_context *smu);
542 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
543 };
544
545 #define smu_init_microcode(smu) \
546 ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
547 #define smu_init_smc_tables(smu) \
548 ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
549 #define smu_fini_smc_tables(smu) \
550 ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
551 #define smu_init_power(smu) \
552 ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
553 #define smu_fini_power(smu) \
554 ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
555 #define smu_load_microcode(smu) \
556 ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
557 #define smu_check_fw_status(smu) \
558 ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
559 #define smu_setup_pptable(smu) \
560 ((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
561 #define smu_powergate_sdma(smu, gate) \
562 ((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
563 #define smu_powergate_vcn(smu, gate) \
564 ((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
565 #define smu_set_gfx_cgpg(smu, enabled) \
566 ((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
567 #define smu_get_vbios_bootup_values(smu) \
568 ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
569 #define smu_get_clk_info_from_vbios(smu) \
570 ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
571 #define smu_check_pptable(smu) \
572 ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
573 #define smu_parse_pptable(smu) \
574 ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
575 #define smu_populate_smc_tables(smu) \
576 ((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
577 #define smu_check_fw_version(smu) \
578 ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
579 #define smu_write_pptable(smu) \
580 ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
581 #define smu_set_min_dcef_deep_sleep(smu) \
582 ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
583 #define smu_set_tool_table_location(smu) \
584 ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
585 #define smu_notify_memory_pool_location(smu) \
586 ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
587 #define smu_gfx_off_control(smu, enable) \
588 ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0)
589
590 #define smu_write_watermarks_table(smu) \
591 ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
592 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
593 ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
594 #define smu_system_features_control(smu, en) \
595 ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
596 #define smu_init_max_sustainable_clocks(smu) \
597 ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
598 #define smu_set_default_od_settings(smu, initialize) \
599 ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
600 #define smu_set_fan_speed_rpm(smu, speed) \
601 ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
602 #define smu_send_smc_msg(smu, msg) \
603 ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
604 #define smu_send_smc_msg_with_param(smu, msg, param) \
605 ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
606 #define smu_read_smc_arg(smu, arg) \
607 ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
608 #define smu_alloc_dpm_context(smu) \
609 ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
610 #define smu_init_display_count(smu, count) \
611 ((smu)->funcs->init_display_count ? (smu)->funcs->init_display_count((smu), (count)) : 0)
612 #define smu_feature_set_allowed_mask(smu) \
613 ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
614 #define smu_feature_get_enabled_mask(smu, mask, num) \
615 ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
616 #define smu_is_dpm_running(smu) \
617 ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
618 #define smu_notify_display_change(smu) \
619 ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
620 #define smu_store_powerplay_table(smu) \
621 ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
622 #define smu_check_powerplay_table(smu) \
623 ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
624 #define smu_append_powerplay_table(smu) \
625 ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
626 #define smu_set_default_dpm_table(smu) \
627 ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
628 #define smu_populate_umd_state_clk(smu) \
629 ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
630 #define smu_set_default_od8_settings(smu) \
631 ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
632 #define smu_get_power_limit(smu, limit, def) \
633 ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
634 #define smu_set_power_limit(smu, limit) \
635 ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
636 #define smu_get_current_clk_freq(smu, clk_id, value) \
637 ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
638 #define smu_print_clk_levels(smu, clk_type, buf) \
639 ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (clk_type), (buf)) : 0)
640 #define smu_force_clk_levels(smu, clk_type, level) \
641 ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (clk_type), (level)) : 0)
642 #define smu_get_od_percentage(smu, type) \
643 ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
644 #define smu_set_od_percentage(smu, type, value) \
645 ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
646 #define smu_od_edit_dpm_table(smu, type, input, size) \
647 ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
648 #define smu_tables_init(smu, tab) \
649 ((smu)->ppt_funcs->tables_init ? (smu)->ppt_funcs->tables_init((smu), (tab)) : 0)
650 #define smu_set_thermal_fan_table(smu) \
651 ((smu)->ppt_funcs->set_thermal_fan_table ? (smu)->ppt_funcs->set_thermal_fan_table((smu)) : 0)
652 #define smu_start_thermal_control(smu) \
653 ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
654 #define smu_read_sensor(smu, sensor, data, size) \
655 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
656 #define smu_smc_read_sensor(smu, sensor, data, size) \
657 ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
658 #define smu_get_power_profile_mode(smu, buf) \
659 ((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
660 #define smu_set_power_profile_mode(smu, param, param_size) \
661 ((smu)->ppt_funcs->set_power_profile_mode ? (smu)->ppt_funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
662 #define smu_pre_display_config_changed(smu) \
663 ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
664 #define smu_display_config_changed(smu) \
665 ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
666 #define smu_apply_clocks_adjust_rules(smu) \
667 ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
668 #define smu_notify_smc_dispaly_config(smu) \
669 ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
670 #define smu_force_dpm_limit_value(smu, highest) \
671 ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
672 #define smu_unforce_dpm_levels(smu) \
673 ((smu)->ppt_funcs->unforce_dpm_levels ? (smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
674 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
675 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
676 #define smu_set_cpu_power_state(smu) \
677 ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
678 #define smu_get_fan_control_mode(smu) \
679 ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
680 #define smu_set_fan_control_mode(smu, value) \
681 ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
682 #define smu_get_fan_speed_percent(smu, speed) \
683 ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0)
684 #define smu_set_fan_speed_percent(smu, speed) \
685 ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
686 #define smu_get_fan_speed_rpm(smu, speed) \
687 ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0)
688
689 #define smu_msg_get_index(smu, msg) \
690 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
691 #define smu_clk_get_index(smu, msg) \
692 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_clk_index? (smu)->ppt_funcs->get_smu_clk_index((smu), (msg)) : -EINVAL) : -EINVAL)
693 #define smu_feature_get_index(smu, msg) \
694 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_feature_index? (smu)->ppt_funcs->get_smu_feature_index((smu), (msg)) : -EINVAL) : -EINVAL)
695 #define smu_table_get_index(smu, tab) \
696 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
697 #define smu_power_get_index(smu, src) \
698 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
699 #define smu_workload_get_type(smu, profile) \
700 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
701 #define smu_run_afll_btc(smu) \
702 ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
703 #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
704 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
705 #define smu_set_deep_sleep_dcefclk(smu, clk) \
706 ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
707 #define smu_set_active_display_count(smu, count) \
708 ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
709 #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
710 ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
711 #define smu_get_clock_by_type(smu, type, clocks) \
712 ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
713 #define smu_get_max_high_clocks(smu, clocks) \
714 ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
715 #define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \
716 ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0)
717 #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
718 ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
719 #define smu_display_clock_voltage_request(smu, clock_req) \
720 ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
721 #define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
722 ((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
723 #define smu_get_dal_power_level(smu, clocks) \
724 ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
725 #define smu_get_perf_level(smu, designation, level) \
726 ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
727 #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
728 ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
729 #define smu_notify_smu_enable_pwe(smu) \
730 ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
731 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
732 ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
733 #define smu_dpm_set_uvd_enable(smu, enable) \
734 ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
735 #define smu_dpm_set_vce_enable(smu, enable) \
736 ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
737 #define smu_set_xgmi_pstate(smu, pstate) \
738 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
739 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
740 ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
741 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
742 ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
743 #define smu_thermal_temperature_range_update(smu, range, rw) \
744 ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0)
745 #define smu_get_thermal_temperature_range(smu, range) \
746 ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
747 #define smu_register_irq_handler(smu) \
748 ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
749 #define smu_set_azalia_d3_pme(smu) \
750 ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
751 #define smu_get_dpm_ultimate_freq(smu, param, min, max) \
752 ((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
753 #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
754 ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
755 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
756 ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
757 #define smu_baco_is_support(smu) \
758 ((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)
759 #define smu_baco_get_state(smu, state) \
760 ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)
761 #define smu_baco_reset(smu) \
762 ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
763 #define smu_asic_set_performance_level(smu, level) \
764 ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
765 #define smu_dump_pptable(smu) \
766 ((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
767 #define smu_get_dpm_uclk_limited(smu, clock, max) \
768 ((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
769
770
771 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
772 uint16_t *size, uint8_t *frev, uint8_t *crev,
773 uint8_t **addr);
774
775 extern const struct amd_ip_funcs smu_ip_funcs;
776
777 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
778 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
779
780 extern int smu_feature_init_dpm(struct smu_context *smu);
781
782 extern int smu_feature_is_enabled(struct smu_context *smu,
783 enum smu_feature_mask mask);
784 extern int smu_feature_set_enabled(struct smu_context *smu,
785 enum smu_feature_mask mask, bool enable);
786 extern int smu_feature_is_supported(struct smu_context *smu,
787 enum smu_feature_mask mask);
788 extern int smu_feature_set_supported(struct smu_context *smu,
789 enum smu_feature_mask mask, bool enable);
790
791 int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
792 void *table_data, bool drv2smu);
793
794 bool is_support_sw_smu(struct amdgpu_device *adev);
795 bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
796 int smu_reset(struct smu_context *smu);
797 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
798 void *data, uint32_t *size);
799 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
800 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
801 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
802 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
803
804
805 extern int smu_display_configuration_change(struct smu_context *smu, const
806 struct amd_pp_display_configuration
807 *display_config);
808 extern int smu_get_current_clocks(struct smu_context *smu,
809 struct amd_pp_clock_info *clocks);
810 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
811 extern int smu_handle_task(struct smu_context *smu,
812 enum amd_dpm_forced_level level,
813 enum amd_pp_task task_id);
814 int smu_switch_power_profile(struct smu_context *smu,
815 enum PP_SMC_POWER_PROFILE type,
816 bool en);
817 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
818 int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
819 uint16_t level, uint32_t *value);
820 int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
821 uint32_t *value);
822 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
823 uint32_t *min, uint32_t *max);
824 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
825 uint32_t min, uint32_t max);
826 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
827 uint32_t min, uint32_t max);
828 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
829 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
830 int smu_set_display_count(struct smu_context *smu, uint32_t count);
831 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
832 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
833 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
834 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
835 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
836 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
837
838 #endif