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23 #ifndef __ARCTURUS_PPT_H__
24 #define __ARCTURUS_PPT_H__
25
26 #define ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL 0x3
27 #define ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL 0x3
28 #define ARCTURUS_UMD_PSTATE_MCLK_LEVEL 0x2
29
30 #define MAX_DPM_NUMBER 16
31 #define MAX_PCIE_CONF 2
32
33 struct arcturus_dpm_level {
34 bool enabled;
35 uint32_t value;
36 uint32_t param1;
37 };
38
39 struct arcturus_dpm_state {
40 uint32_t soft_min_level;
41 uint32_t soft_max_level;
42 uint32_t hard_min_level;
43 uint32_t hard_max_level;
44 };
45
46 struct arcturus_single_dpm_table {
47 uint32_t count;
48 struct arcturus_dpm_state dpm_state;
49 struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER];
50 };
51
52 struct arcturus_pcie_table {
53 uint16_t count;
54 uint8_t pcie_gen[MAX_PCIE_CONF];
55 uint8_t pcie_lane[MAX_PCIE_CONF];
56 uint32_t lclk[MAX_PCIE_CONF];
57 };
58
59 struct arcturus_dpm_table {
60 struct arcturus_single_dpm_table soc_table;
61 struct arcturus_single_dpm_table gfx_table;
62 struct arcturus_single_dpm_table mem_table;
63 struct arcturus_single_dpm_table eclk_table;
64 struct arcturus_single_dpm_table vclk_table;
65 struct arcturus_single_dpm_table dclk_table;
66 struct arcturus_single_dpm_table fclk_table;
67 struct arcturus_pcie_table pcie_table;
68 };
69
70 extern void arcturus_set_ppt_funcs(struct smu_context *smu);
71
72 #endif