drivers/gpu/drm/gma500/psb

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This source file includes following definitions.
psb_pipestat
mid_pipe_event
mid_pipe_vsync
mid_pipeconf
psb_enable_pipestat
psb_disable_pipestat
mid_enable_pipe_event
mid_disable_pipe_event
mid_pipe_event_handler
psb_vdc_interrupt
psb_sgx_interrupt
psb_irq_handler
psb_irq_preinstall
psb_irq_postinstall
psb_irq_uninstall
psb_irq_turn_on_dpst
psb_irq_enable_dpst
psb_irq_turn_off_dpst
psb_irq_disable_dpst
psb_enable_vblank
psb_disable_vblank
mdfld_enable_te
mdfld_disable_te
psb_get_vblank_counter
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**************************************************************************
   3  * Copyright (c) 2007, Intel Corporation.
   4  * All Rights Reserved.
   5  *
   6  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   7  * develop this driver.
   8  *
   9  **************************************************************************/
  10 
  11 #include <drm/drm_vblank.h>
  12 
  13 #include "mdfld_output.h"
  14 #include "power.h"
  15 #include "psb_drv.h"
  16 #include "psb_intel_reg.h"
  17 #include "psb_irq.h"
  18 #include "psb_reg.h"
  19 
  20 /*
  21  * inline functions
  22  */
  23 
  24 static inline u32
  25 psb_pipestat(int pipe)
  26 {
  27         if (pipe == 0)
  28                 return PIPEASTAT;
  29         if (pipe == 1)
  30                 return PIPEBSTAT;
  31         if (pipe == 2)
  32                 return PIPECSTAT;
  33         BUG();
  34 }
  35 
  36 static inline u32
  37 mid_pipe_event(int pipe)
  38 {
  39         if (pipe == 0)
  40                 return _PSB_PIPEA_EVENT_FLAG;
  41         if (pipe == 1)
  42                 return _MDFLD_PIPEB_EVENT_FLAG;
  43         if (pipe == 2)
  44                 return _MDFLD_PIPEC_EVENT_FLAG;
  45         BUG();
  46 }
  47 
  48 static inline u32
  49 mid_pipe_vsync(int pipe)
  50 {
  51         if (pipe == 0)
  52                 return _PSB_VSYNC_PIPEA_FLAG;
  53         if (pipe == 1)
  54                 return _PSB_VSYNC_PIPEB_FLAG;
  55         if (pipe == 2)
  56                 return _MDFLD_PIPEC_VBLANK_FLAG;
  57         BUG();
  58 }
  59 
  60 static inline u32
  61 mid_pipeconf(int pipe)
  62 {
  63         if (pipe == 0)
  64                 return PIPEACONF;
  65         if (pipe == 1)
  66                 return PIPEBCONF;
  67         if (pipe == 2)
  68                 return PIPECCONF;
  69         BUG();
  70 }
  71 
  72 void
  73 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  74 {
  75         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  76                 u32 reg = psb_pipestat(pipe);
  77                 dev_priv->pipestat[pipe] |= mask;
  78                 /* Enable the interrupt, clear any pending status */
  79                 if (gma_power_begin(dev_priv->dev, false)) {
  80                         u32 writeVal = PSB_RVDC32(reg);
  81                         writeVal |= (mask | (mask >> 16));
  82                         PSB_WVDC32(writeVal, reg);
  83                         (void) PSB_RVDC32(reg);
  84                         gma_power_end(dev_priv->dev);
  85                 }
  86         }
  87 }
  88 
  89 void
  90 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  91 {
  92         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  93                 u32 reg = psb_pipestat(pipe);
  94                 dev_priv->pipestat[pipe] &= ~mask;
  95                 if (gma_power_begin(dev_priv->dev, false)) {
  96                         u32 writeVal = PSB_RVDC32(reg);
  97                         writeVal &= ~mask;
  98                         PSB_WVDC32(writeVal, reg);
  99                         (void) PSB_RVDC32(reg);
 100                         gma_power_end(dev_priv->dev);
 101                 }
 102         }
 103 }
 104 
 105 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 106 {
 107         if (gma_power_begin(dev_priv->dev, false)) {
 108                 u32 pipe_event = mid_pipe_event(pipe);
 109                 dev_priv->vdc_irq_mask |= pipe_event;
 110                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 111                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 112                 gma_power_end(dev_priv->dev);
 113         }
 114 }
 115 
 116 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 117 {
 118         if (dev_priv->pipestat[pipe] == 0) {
 119                 if (gma_power_begin(dev_priv->dev, false)) {
 120                         u32 pipe_event = mid_pipe_event(pipe);
 121                         dev_priv->vdc_irq_mask &= ~pipe_event;
 122                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 123                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 124                         gma_power_end(dev_priv->dev);
 125                 }
 126         }
 127 }
 128 
 129 /**
 130  * Display controller interrupt handler for pipe event.
 131  *
 132  */
 133 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
 134 {
 135         struct drm_psb_private *dev_priv =
 136             (struct drm_psb_private *) dev->dev_private;
 137 
 138         uint32_t pipe_stat_val = 0;
 139         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 140         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 141         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 142         uint32_t pipe_clear;
 143         uint32_t i = 0;
 144 
 145         spin_lock(&dev_priv->irqmask_lock);
 146 
 147         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 148         pipe_stat_val &= pipe_enable | pipe_status;
 149         pipe_stat_val &= pipe_stat_val >> 16;
 150 
 151         spin_unlock(&dev_priv->irqmask_lock);
 152 
 153         /* Clear the 2nd level interrupt status bits
 154          * Sometimes the bits are very sticky so we repeat until they unstick */
 155         for (i = 0; i < 0xffff; i++) {
 156                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 157                 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
 158 
 159                 if (pipe_clear == 0)
 160                         break;
 161         }
 162 
 163         if (pipe_clear)
 164                 dev_err(dev->dev,
 165                 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
 166                 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
 167 
 168         if (pipe_stat_val & PIPE_VBLANK_STATUS)
 169                 drm_handle_vblank(dev, pipe);
 170 
 171         if (pipe_stat_val & PIPE_TE_STATUS)
 172                 drm_handle_vblank(dev, pipe);
 173 }
 174 
 175 /*
 176  * Display controller interrupt handler.
 177  */
 178 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 179 {
 180         if (vdc_stat & _PSB_IRQ_ASLE)
 181                 psb_intel_opregion_asle_intr(dev);
 182 
 183         if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
 184                 mid_pipe_event_handler(dev, 0);
 185 
 186         if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
 187                 mid_pipe_event_handler(dev, 1);
 188 }
 189 
 190 /*
 191  * SGX interrupt handler
 192  */
 193 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
 194 {
 195         struct drm_psb_private *dev_priv = dev->dev_private;
 196         u32 val, addr;
 197         int error = false;
 198 
 199         if (stat_1 & _PSB_CE_TWOD_COMPLETE)
 200                 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
 201 
 202         if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
 203                 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
 204                 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
 205                 if (val) {
 206                         if (val & _PSB_CBI_STAT_PF_N_RW)
 207                                 DRM_ERROR("SGX MMU page fault:");
 208                         else
 209                                 DRM_ERROR("SGX MMU read / write protection fault:");
 210 
 211                         if (val & _PSB_CBI_STAT_FAULT_CACHE)
 212                                 DRM_ERROR("\tCache requestor");
 213                         if (val & _PSB_CBI_STAT_FAULT_TA)
 214                                 DRM_ERROR("\tTA requestor");
 215                         if (val & _PSB_CBI_STAT_FAULT_VDM)
 216                                 DRM_ERROR("\tVDM requestor");
 217                         if (val & _PSB_CBI_STAT_FAULT_2D)
 218                                 DRM_ERROR("\t2D requestor");
 219                         if (val & _PSB_CBI_STAT_FAULT_PBE)
 220                                 DRM_ERROR("\tPBE requestor");
 221                         if (val & _PSB_CBI_STAT_FAULT_TSP)
 222                                 DRM_ERROR("\tTSP requestor");
 223                         if (val & _PSB_CBI_STAT_FAULT_ISP)
 224                                 DRM_ERROR("\tISP requestor");
 225                         if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
 226                                 DRM_ERROR("\tUSSEPDS requestor");
 227                         if (val & _PSB_CBI_STAT_FAULT_HOST)
 228                                 DRM_ERROR("\tHost requestor");
 229 
 230                         DRM_ERROR("\tMMU failing address is 0x%08x.\n",
 231                                   (unsigned int)addr);
 232                         error = true;
 233                 }
 234         }
 235 
 236         /* Clear bits */
 237         PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
 238         PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
 239         PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
 240 }
 241 
 242 irqreturn_t psb_irq_handler(int irq, void *arg)
 243 {
 244         struct drm_device *dev = arg;
 245         struct drm_psb_private *dev_priv = dev->dev_private;
 246         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
 247         u32 sgx_stat_1, sgx_stat_2;
 248         int handled = 0;
 249 
 250         spin_lock(&dev_priv->irqmask_lock);
 251 
 252         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 253 
 254         if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
 255                 dsp_int = 1;
 256 
 257         /* FIXME: Handle Medfield
 258         if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
 259                 dsp_int = 1;
 260         */
 261 
 262         if (vdc_stat & _PSB_IRQ_SGX_FLAG)
 263                 sgx_int = 1;
 264         if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
 265                 hotplug_int = 1;
 266 
 267         vdc_stat &= dev_priv->vdc_irq_mask;
 268         spin_unlock(&dev_priv->irqmask_lock);
 269 
 270         if (dsp_int && gma_power_is_on(dev)) {
 271                 psb_vdc_interrupt(dev, vdc_stat);
 272                 handled = 1;
 273         }
 274 
 275         if (sgx_int) {
 276                 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 277                 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 278                 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
 279                 handled = 1;
 280         }
 281 
 282         /* Note: this bit has other meanings on some devices, so we will
 283            need to address that later if it ever matters */
 284         if (hotplug_int && dev_priv->ops->hotplug) {
 285                 handled = dev_priv->ops->hotplug(dev);
 286                 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 287         }
 288 
 289         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 290         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 291         rmb();
 292 
 293         if (!handled)
 294                 return IRQ_NONE;
 295 
 296         return IRQ_HANDLED;
 297 }
 298 
 299 void psb_irq_preinstall(struct drm_device *dev)
 300 {
 301         struct drm_psb_private *dev_priv =
 302             (struct drm_psb_private *) dev->dev_private;
 303         unsigned long irqflags;
 304 
 305         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 306 
 307         if (gma_power_is_on(dev)) {
 308                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 309                 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
 310                 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 311                 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
 312                 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
 313         }
 314         if (dev->vblank[0].enabled)
 315                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 316         if (dev->vblank[1].enabled)
 317                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 318 
 319         /* FIXME: Handle Medfield irq mask
 320         if (dev->vblank[1].enabled)
 321                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
 322         if (dev->vblank[2].enabled)
 323                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
 324         */
 325 
 326         /* Revisit this area - want per device masks ? */
 327         if (dev_priv->ops->hotplug)
 328                 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
 329         dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
 330 
 331         /* This register is safe even if display island is off */
 332         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 333         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 334 }
 335 
 336 int psb_irq_postinstall(struct drm_device *dev)
 337 {
 338         struct drm_psb_private *dev_priv = dev->dev_private;
 339         unsigned long irqflags;
 340 
 341         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 342 
 343         /* Enable 2D and MMU fault interrupts */
 344         PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
 345         PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
 346         PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
 347 
 348         /* This register is safe even if display island is off */
 349         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 350         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 351 
 352         if (dev->vblank[0].enabled)
 353                 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 354         else
 355                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 356 
 357         if (dev->vblank[1].enabled)
 358                 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 359         else
 360                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 361 
 362         if (dev->vblank[2].enabled)
 363                 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 364         else
 365                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 366 
 367         if (dev_priv->ops->hotplug_enable)
 368                 dev_priv->ops->hotplug_enable(dev, true);
 369 
 370         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 371         return 0;
 372 }
 373 
 374 void psb_irq_uninstall(struct drm_device *dev)
 375 {
 376         struct drm_psb_private *dev_priv = dev->dev_private;
 377         unsigned long irqflags;
 378 
 379         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 380 
 381         if (dev_priv->ops->hotplug_enable)
 382                 dev_priv->ops->hotplug_enable(dev, false);
 383 
 384         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 385 
 386         if (dev->vblank[0].enabled)
 387                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 388 
 389         if (dev->vblank[1].enabled)
 390                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 391 
 392         if (dev->vblank[2].enabled)
 393                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 394 
 395         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 396                                   _PSB_IRQ_MSVDX_FLAG |
 397                                   _LNC_IRQ_TOPAZ_FLAG;
 398 
 399         /* These two registers are safe even if display island is off */
 400         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 401         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 402 
 403         wmb();
 404 
 405         /* This register is safe even if display island is off */
 406         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 407         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 408 }
 409 
 410 void psb_irq_turn_on_dpst(struct drm_device *dev)
 411 {
 412         struct drm_psb_private *dev_priv =
 413                 (struct drm_psb_private *) dev->dev_private;
 414         u32 hist_reg;
 415         u32 pwm_reg;
 416 
 417         if (gma_power_begin(dev, false)) {
 418                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 419                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 420                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 421                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 422 
 423                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 424                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 425                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 426                                                 | PWM_PHASEIN_INT_ENABLE,
 427                                                            PWM_CONTROL_LOGIC);
 428                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 429 
 430                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 431 
 432                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 433                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 434                                                         HISTOGRAM_INT_CONTROL);
 435                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 436                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 437                                                         PWM_CONTROL_LOGIC);
 438 
 439                 gma_power_end(dev);
 440         }
 441 }
 442 
 443 int psb_irq_enable_dpst(struct drm_device *dev)
 444 {
 445         struct drm_psb_private *dev_priv =
 446                 (struct drm_psb_private *) dev->dev_private;
 447         unsigned long irqflags;
 448 
 449         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 450 
 451         /* enable DPST */
 452         mid_enable_pipe_event(dev_priv, 0);
 453         psb_irq_turn_on_dpst(dev);
 454 
 455         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 456         return 0;
 457 }
 458 
 459 void psb_irq_turn_off_dpst(struct drm_device *dev)
 460 {
 461         struct drm_psb_private *dev_priv =
 462             (struct drm_psb_private *) dev->dev_private;
 463         u32 hist_reg;
 464         u32 pwm_reg;
 465 
 466         if (gma_power_begin(dev, false)) {
 467                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 468                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 469 
 470                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 471 
 472                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 473                 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
 474                                                         PWM_CONTROL_LOGIC);
 475                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 476 
 477                 gma_power_end(dev);
 478         }
 479 }
 480 
 481 int psb_irq_disable_dpst(struct drm_device *dev)
 482 {
 483         struct drm_psb_private *dev_priv =
 484             (struct drm_psb_private *) dev->dev_private;
 485         unsigned long irqflags;
 486 
 487         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 488 
 489         mid_disable_pipe_event(dev_priv, 0);
 490         psb_irq_turn_off_dpst(dev);
 491 
 492         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 493 
 494         return 0;
 495 }
 496 
 497 /*
 498  * It is used to enable VBLANK interrupt
 499  */
 500 int psb_enable_vblank(struct drm_device *dev, unsigned int pipe)
 501 {
 502         struct drm_psb_private *dev_priv = dev->dev_private;
 503         unsigned long irqflags;
 504         uint32_t reg_val = 0;
 505         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 506 
 507         /* Medfield is different - we should perhaps extract out vblank
 508            and blacklight etc ops */
 509         if (IS_MFLD(dev))
 510                 return mdfld_enable_te(dev, pipe);
 511 
 512         if (gma_power_begin(dev, false)) {
 513                 reg_val = REG_READ(pipeconf_reg);
 514                 gma_power_end(dev);
 515         }
 516 
 517         if (!(reg_val & PIPEACONF_ENABLE))
 518                 return -EINVAL;
 519 
 520         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 521 
 522         if (pipe == 0)
 523                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 524         else if (pipe == 1)
 525                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 526 
 527         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 528         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 529         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 530 
 531         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 532 
 533         return 0;
 534 }
 535 
 536 /*
 537  * It is used to disable VBLANK interrupt
 538  */
 539 void psb_disable_vblank(struct drm_device *dev, unsigned int pipe)
 540 {
 541         struct drm_psb_private *dev_priv = dev->dev_private;
 542         unsigned long irqflags;
 543 
 544         if (IS_MFLD(dev))
 545                 mdfld_disable_te(dev, pipe);
 546         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 547 
 548         if (pipe == 0)
 549                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
 550         else if (pipe == 1)
 551                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
 552 
 553         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 554         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 555         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 556 
 557         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 558 }
 559 
 560 /*
 561  * It is used to enable TE interrupt
 562  */
 563 int mdfld_enable_te(struct drm_device *dev, int pipe)
 564 {
 565         struct drm_psb_private *dev_priv =
 566                 (struct drm_psb_private *) dev->dev_private;
 567         unsigned long irqflags;
 568         uint32_t reg_val = 0;
 569         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 570 
 571         if (gma_power_begin(dev, false)) {
 572                 reg_val = REG_READ(pipeconf_reg);
 573                 gma_power_end(dev);
 574         }
 575 
 576         if (!(reg_val & PIPEACONF_ENABLE))
 577                 return -EINVAL;
 578 
 579         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 580 
 581         mid_enable_pipe_event(dev_priv, pipe);
 582         psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 583 
 584         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 585 
 586         return 0;
 587 }
 588 
 589 /*
 590  * It is used to disable TE interrupt
 591  */
 592 void mdfld_disable_te(struct drm_device *dev, int pipe)
 593 {
 594         struct drm_psb_private *dev_priv =
 595                 (struct drm_psb_private *) dev->dev_private;
 596         unsigned long irqflags;
 597 
 598         if (!dev_priv->dsr_enable)
 599                 return;
 600 
 601         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 602 
 603         mid_disable_pipe_event(dev_priv, pipe);
 604         psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
 605 
 606         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 607 }
 608 
 609 /* Called from drm generic code, passed a 'crtc', which
 610  * we use as a pipe index
 611  */
 612 u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 613 {
 614         uint32_t high_frame = PIPEAFRAMEHIGH;
 615         uint32_t low_frame = PIPEAFRAMEPIXEL;
 616         uint32_t pipeconf_reg = PIPEACONF;
 617         uint32_t reg_val = 0;
 618         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 619 
 620         switch (pipe) {
 621         case 0:
 622                 break;
 623         case 1:
 624                 high_frame = PIPEBFRAMEHIGH;
 625                 low_frame = PIPEBFRAMEPIXEL;
 626                 pipeconf_reg = PIPEBCONF;
 627                 break;
 628         case 2:
 629                 high_frame = PIPECFRAMEHIGH;
 630                 low_frame = PIPECFRAMEPIXEL;
 631                 pipeconf_reg = PIPECCONF;
 632                 break;
 633         default:
 634                 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
 635                 return 0;
 636         }
 637 
 638         if (!gma_power_begin(dev, false))
 639                 return 0;
 640 
 641         reg_val = REG_READ(pipeconf_reg);
 642 
 643         if (!(reg_val & PIPEACONF_ENABLE)) {
 644                 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
 645                                                                 pipe);
 646                 goto psb_get_vblank_counter_exit;
 647         }
 648 
 649         /*
 650          * High & low register fields aren't synchronized, so make sure
 651          * we get a low value that's stable across two reads of the high
 652          * register.
 653          */
 654         do {
 655                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 656                          PIPE_FRAME_HIGH_SHIFT);
 657                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 658                         PIPE_FRAME_LOW_SHIFT);
 659                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 660                          PIPE_FRAME_HIGH_SHIFT);
 661         } while (high1 != high2);
 662 
 663         count = (high1 << 8) | low;
 664 
 665 psb_get_vblank_counter_exit:
 666 
 667         gma_power_end(dev);
 668 
 669         return count;
 670 }
 671
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/gma500/psb_irq.c

DEFINITIONS
