drivers/gpu/drm/gma500/intel

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This source file includes following definitions.
to_intel_gmbus
gma_intel_i2c_reset
intel_i2c_quirk_set
get_reserved
get_clock
get_data
set_clock
set_data
intel_gpio_create
intel_i2c_quirk_xfer
gmbus_xfer
gmbus_func
gma_intel_setup_gmbus
gma_intel_gmbus_set_speed
gma_intel_gmbus_force_bit
gma_intel_teardown_gmbus
   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 
  30 #include <linux/delay.h>
  31 #include <linux/i2c-algo-bit.h>
  32 #include <linux/i2c.h>
  33 #include <linux/module.h>
  34 
  35 #include "psb_drv.h"
  36 #include "psb_intel_drv.h"
  37 #include "psb_intel_reg.h"
  38 
  39 #define _wait_for(COND, MS, W) ({ \
  40         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);       \
  41         int ret__ = 0;                                                  \
  42         while (! (COND)) {                                              \
  43                 if (time_after(jiffies, timeout__)) {                   \
  44                         ret__ = -ETIMEDOUT;                             \
  45                         break;                                          \
  46                 }                                                       \
  47                 if (W && !(in_atomic() || in_dbg_master())) msleep(W);  \
  48         }                                                               \
  49         ret__;                                                          \
  50 })
  51 
  52 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  53 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  54 
  55 #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
  56 #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
  57 
  58 /* Intel GPIO access functions */
  59 
  60 #define I2C_RISEFALL_TIME 20
  61 
  62 static inline struct intel_gmbus *
  63 to_intel_gmbus(struct i2c_adapter *i2c)
  64 {
  65         return container_of(i2c, struct intel_gmbus, adapter);
  66 }
  67 
  68 struct intel_gpio {
  69         struct i2c_adapter adapter;
  70         struct i2c_algo_bit_data algo;
  71         struct drm_psb_private *dev_priv;
  72         u32 reg;
  73 };
  74 
  75 void
  76 gma_intel_i2c_reset(struct drm_device *dev)
  77 {
  78         struct drm_psb_private *dev_priv = dev->dev_private;
  79         GMBUS_REG_WRITE(GMBUS0, 0);
  80 }
  81 
  82 static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
  83 {
  84         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  85         /* FIXME: We are never Pineview, right?
  86 
  87         u32 val;
  88 
  89         if (!IS_PINEVIEW(dev_priv->dev))
  90                 return;
  91 
  92         val = REG_READ(DSPCLK_GATE_D);
  93         if (enable)
  94                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  95         else
  96                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  97         REG_WRITE(DSPCLK_GATE_D, val);
  98 
  99         return;
 100         */
 101 }
 102 
 103 static u32 get_reserved(struct intel_gpio *gpio)
 104 {
 105         struct drm_psb_private *dev_priv = gpio->dev_priv;
 106         u32 reserved = 0;
 107 
 108         /* On most chips, these bits must be preserved in software. */
 109         reserved = GMBUS_REG_READ(gpio->reg) &
 110                                      (GPIO_DATA_PULLUP_DISABLE |
 111                                       GPIO_CLOCK_PULLUP_DISABLE);
 112 
 113         return reserved;
 114 }
 115 
 116 static int get_clock(void *data)
 117 {
 118         struct intel_gpio *gpio = data;
 119         struct drm_psb_private *dev_priv = gpio->dev_priv;
 120         u32 reserved = get_reserved(gpio);
 121         GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
 122         GMBUS_REG_WRITE(gpio->reg, reserved);
 123         return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
 124 }
 125 
 126 static int get_data(void *data)
 127 {
 128         struct intel_gpio *gpio = data;
 129         struct drm_psb_private *dev_priv = gpio->dev_priv;
 130         u32 reserved = get_reserved(gpio);
 131         GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
 132         GMBUS_REG_WRITE(gpio->reg, reserved);
 133         return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
 134 }
 135 
 136 static void set_clock(void *data, int state_high)
 137 {
 138         struct intel_gpio *gpio = data;
 139         struct drm_psb_private *dev_priv = gpio->dev_priv;
 140         u32 reserved = get_reserved(gpio);
 141         u32 clock_bits;
 142 
 143         if (state_high)
 144                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 145         else
 146                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 147                         GPIO_CLOCK_VAL_MASK;
 148 
 149         GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
 150         GMBUS_REG_READ(gpio->reg); /* Posting */
 151 }
 152 
 153 static void set_data(void *data, int state_high)
 154 {
 155         struct intel_gpio *gpio = data;
 156         struct drm_psb_private *dev_priv = gpio->dev_priv;
 157         u32 reserved = get_reserved(gpio);
 158         u32 data_bits;
 159 
 160         if (state_high)
 161                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 162         else
 163                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 164                         GPIO_DATA_VAL_MASK;
 165 
 166         GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
 167         GMBUS_REG_READ(gpio->reg);
 168 }
 169 
 170 static struct i2c_adapter *
 171 intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
 172 {
 173         static const int map_pin_to_reg[] = {
 174                 0,
 175                 GPIOB,
 176                 GPIOA,
 177                 GPIOC,
 178                 GPIOD,
 179                 GPIOE,
 180                 0,
 181                 GPIOF,
 182         };
 183         struct intel_gpio *gpio;
 184 
 185         if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
 186                 return NULL;
 187 
 188         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
 189         if (gpio == NULL)
 190                 return NULL;
 191 
 192         gpio->reg = map_pin_to_reg[pin];
 193         gpio->dev_priv = dev_priv;
 194 
 195         snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
 196                  "gma500 GPIO%c", "?BACDE?F"[pin]);
 197         gpio->adapter.owner = THIS_MODULE;
 198         gpio->adapter.algo_data = &gpio->algo;
 199         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
 200         gpio->algo.setsda = set_data;
 201         gpio->algo.setscl = set_clock;
 202         gpio->algo.getsda = get_data;
 203         gpio->algo.getscl = get_clock;
 204         gpio->algo.udelay = I2C_RISEFALL_TIME;
 205         gpio->algo.timeout = usecs_to_jiffies(2200);
 206         gpio->algo.data = gpio;
 207 
 208         if (i2c_bit_add_bus(&gpio->adapter))
 209                 goto out_free;
 210 
 211         return &gpio->adapter;
 212 
 213 out_free:
 214         kfree(gpio);
 215         return NULL;
 216 }
 217 
 218 static int
 219 intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
 220                      struct i2c_adapter *adapter,
 221                      struct i2c_msg *msgs,
 222                      int num)
 223 {
 224         struct intel_gpio *gpio = container_of(adapter,
 225                                                struct intel_gpio,
 226                                                adapter);
 227         int ret;
 228 
 229         gma_intel_i2c_reset(dev_priv->dev);
 230 
 231         intel_i2c_quirk_set(dev_priv, true);
 232         set_data(gpio, 1);
 233         set_clock(gpio, 1);
 234         udelay(I2C_RISEFALL_TIME);
 235 
 236         ret = adapter->algo->master_xfer(adapter, msgs, num);
 237 
 238         set_data(gpio, 1);
 239         set_clock(gpio, 1);
 240         intel_i2c_quirk_set(dev_priv, false);
 241 
 242         return ret;
 243 }
 244 
 245 static int
 246 gmbus_xfer(struct i2c_adapter *adapter,
 247            struct i2c_msg *msgs,
 248            int num)
 249 {
 250         struct intel_gmbus *bus = container_of(adapter,
 251                                                struct intel_gmbus,
 252                                                adapter);
 253         struct drm_psb_private *dev_priv = adapter->algo_data;
 254         int i, reg_offset;
 255 
 256         if (bus->force_bit)
 257                 return intel_i2c_quirk_xfer(dev_priv,
 258                                             bus->force_bit, msgs, num);
 259 
 260         reg_offset = 0;
 261 
 262         GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
 263 
 264         for (i = 0; i < num; i++) {
 265                 u16 len = msgs[i].len;
 266                 u8 *buf = msgs[i].buf;
 267 
 268                 if (msgs[i].flags & I2C_M_RD) {
 269                         GMBUS_REG_WRITE(GMBUS1 + reg_offset,
 270                                         GMBUS_CYCLE_WAIT |
 271                                         (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
 272                                         (len << GMBUS_BYTE_COUNT_SHIFT) |
 273                                         (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 274                                         GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 275                         GMBUS_REG_READ(GMBUS2+reg_offset);
 276                         do {
 277                                 u32 val, loop = 0;
 278 
 279                                 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
 280                                              (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 281                                         goto timeout;
 282                                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 283                                         goto clear_err;
 284 
 285                                 val = GMBUS_REG_READ(GMBUS3 + reg_offset);
 286                                 do {
 287                                         *buf++ = val & 0xff;
 288                                         val >>= 8;
 289                                 } while (--len && ++loop < 4);
 290                         } while (len);
 291                 } else {
 292                         u32 val, loop;
 293 
 294                         val = loop = 0;
 295                         do {
 296                                 val |= *buf++ << (8 * loop);
 297                         } while (--len && ++loop < 4);
 298 
 299                         GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
 300                         GMBUS_REG_WRITE(GMBUS1 + reg_offset,
 301                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
 302                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 303                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 304                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 305                         GMBUS_REG_READ(GMBUS2+reg_offset);
 306 
 307                         while (len) {
 308                                 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
 309                                              (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 310                                         goto timeout;
 311                                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
 312                                     GMBUS_SATOER)
 313                                         goto clear_err;
 314 
 315                                 val = loop = 0;
 316                                 do {
 317                                         val |= *buf++ << (8 * loop);
 318                                 } while (--len && ++loop < 4);
 319 
 320                                 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
 321                                 GMBUS_REG_READ(GMBUS2+reg_offset);
 322                         }
 323                 }
 324 
 325                 if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
 326                         goto timeout;
 327                 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 328                         goto clear_err;
 329         }
 330 
 331         goto done;
 332 
 333 clear_err:
 334         /* Toggle the Software Clear Interrupt bit. This has the effect
 335          * of resetting the GMBUS controller and so clearing the
 336          * BUS_ERROR raised by the slave's NAK.
 337          */
 338         GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 339         GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
 340 
 341 done:
 342         /* Mark the GMBUS interface as disabled. We will re-enable it at the
 343          * start of the next xfer, till then let it sleep.
 344          */
 345         GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
 346         return i;
 347 
 348 timeout:
 349         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 350                  bus->reg0 & 0xff, bus->adapter.name);
 351         GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
 352 
 353         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 354         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
 355         if (!bus->force_bit)
 356                 return -ENOMEM;
 357 
 358         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
 359 }
 360 
 361 static u32 gmbus_func(struct i2c_adapter *adapter)
 362 {
 363         struct intel_gmbus *bus = container_of(adapter,
 364                                                struct intel_gmbus,
 365                                                adapter);
 366 
 367         if (bus->force_bit)
 368                 bus->force_bit->algo->functionality(bus->force_bit);
 369 
 370         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 371                 /* I2C_FUNC_10BIT_ADDR | */
 372                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 373                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 374 }
 375 
 376 static const struct i2c_algorithm gmbus_algorithm = {
 377         .master_xfer    = gmbus_xfer,
 378         .functionality  = gmbus_func
 379 };
 380 
 381 /**
 382  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 383  * @dev: DRM device
 384  */
 385 int gma_intel_setup_gmbus(struct drm_device *dev)
 386 {
 387         static const char *names[GMBUS_NUM_PORTS] = {
 388                 "disabled",
 389                 "ssc",
 390                 "vga",
 391                 "panel",
 392                 "dpc",
 393                 "dpb",
 394                 "reserved",
 395                 "dpd",
 396         };
 397         struct drm_psb_private *dev_priv = dev->dev_private;
 398         int ret, i;
 399 
 400         dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
 401                                   GFP_KERNEL);
 402         if (dev_priv->gmbus == NULL)
 403                 return -ENOMEM;
 404 
 405         if (IS_MRST(dev))
 406                 dev_priv->gmbus_reg = dev_priv->aux_reg;
 407         else
 408                 dev_priv->gmbus_reg = dev_priv->vdc_reg;
 409 
 410         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 411                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 412 
 413                 bus->adapter.owner = THIS_MODULE;
 414                 bus->adapter.class = I2C_CLASS_DDC;
 415                 snprintf(bus->adapter.name,
 416                          sizeof(bus->adapter.name),
 417                          "gma500 gmbus %s",
 418                          names[i]);
 419 
 420                 bus->adapter.dev.parent = &dev->pdev->dev;
 421                 bus->adapter.algo_data  = dev_priv;
 422 
 423                 bus->adapter.algo = &gmbus_algorithm;
 424                 ret = i2c_add_adapter(&bus->adapter);
 425                 if (ret)
 426                         goto err;
 427 
 428                 /* By default use a conservative clock rate */
 429                 bus->reg0 = i | GMBUS_RATE_100KHZ;
 430 
 431                 /* XXX force bit banging until GMBUS is fully debugged */
 432                 bus->force_bit = intel_gpio_create(dev_priv, i);
 433         }
 434 
 435         gma_intel_i2c_reset(dev_priv->dev);
 436 
 437         return 0;
 438 
 439 err:
 440         while (i--) {
 441                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 442                 i2c_del_adapter(&bus->adapter);
 443         }
 444         kfree(dev_priv->gmbus);
 445         dev_priv->gmbus = NULL;
 446         return ret;
 447 }
 448 
 449 void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 450 {
 451         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 452 
 453         /* speed:
 454          * 0x0 = 100 KHz
 455          * 0x1 = 50 KHz
 456          * 0x2 = 400 KHz
 457          * 0x3 = 1000 Khz
 458          */
 459         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
 460 }
 461 
 462 void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 463 {
 464         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 465 
 466         if (force_bit) {
 467                 if (bus->force_bit == NULL) {
 468                         struct drm_psb_private *dev_priv = adapter->algo_data;
 469                         bus->force_bit = intel_gpio_create(dev_priv,
 470                                                            bus->reg0 & 0xff);
 471                 }
 472         } else {
 473                 if (bus->force_bit) {
 474                         i2c_del_adapter(bus->force_bit);
 475                         kfree(bus->force_bit);
 476                         bus->force_bit = NULL;
 477                 }
 478         }
 479 }
 480 
 481 void gma_intel_teardown_gmbus(struct drm_device *dev)
 482 {
 483         struct drm_psb_private *dev_priv = dev->dev_private;
 484         int i;
 485 
 486         if (dev_priv->gmbus == NULL)
 487                 return;
 488 
 489         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 490                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 491                 if (bus->force_bit) {
 492                         i2c_del_adapter(bus->force_bit);
 493                         kfree(bus->force_bit);
 494                 }
 495                 i2c_del_adapter(&bus->adapter);
 496         }
 497 
 498         dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
 499         kfree(dev_priv->gmbus);
 500         dev_priv->gmbus = NULL;
 501 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/gma500/intel_gmbus.c

DEFINITIONS
