1
2
3
4
5
6
7 #ifndef TEGRA_HDMI_H
8 #define TEGRA_HDMI_H 1
9
10
11 #define HDMI_CTXSW 0x00
12
13 #define HDMI_NV_PDISP_SOR_STATE0 0x01
14 #define SOR_STATE_UPDATE (1 << 0)
15
16 #define HDMI_NV_PDISP_SOR_STATE1 0x02
17 #define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
18 #define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
19 #define SOR_STATE_ATTACHED (1 << 3)
20
21 #define HDMI_NV_PDISP_SOR_STATE2 0x03
22 #define SOR_STATE_ASY_OWNER_NONE (0 << 0)
23 #define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
24 #define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
25 #define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
26 #define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
27 #define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
28 #define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
29 #define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
30 #define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
31 #define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
32 #define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
33 #define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
34 #define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
35 #define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
36 #define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
37 #define SOR_STATE_ASY_DEPOL_POS (0 << 14)
38 #define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
39
40 #define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
41 #define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
42 #define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
43 #define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
44 #define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
45 #define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
46 #define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
47 #define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
48 #define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
49 #define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
50 #define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
51 #define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
52 #define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
53 #define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
54 #define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
55 #define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
56 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
57 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
58 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
59 #define HDMI_NV_PDISP_RG_HDCP_RI 0x17
60 #define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
61 #define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
62 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
63 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
64 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
65 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
66
67 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
68 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
69 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
70 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
71 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
72 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
73 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
74 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
75 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
76 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
77 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
78 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
79
80 #define INFOFRAME_CTRL_ENABLE (1 << 0)
81
82 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
83 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
84 #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
85
86 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
87 #define GENERIC_CTRL_ENABLE (1 << 0)
88 #define GENERIC_CTRL_OTHER (1 << 4)
89 #define GENERIC_CTRL_SINGLE (1 << 8)
90 #define GENERIC_CTRL_HBLANK (1 << 12)
91 #define GENERIC_CTRL_AUDIO (1 << 16)
92
93 #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
94 #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
95 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
96 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
97 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f
98 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30
99 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31
100 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32
101 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33
102 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34
103
104 #define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35
105 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36
106 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37
107 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38
108 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39
109 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a
110 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b
111 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c
112 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d
113 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e
114 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f
115 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40
116 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41
117 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42
118 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43
119
120 #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
121 #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
122 #define ACR_ENABLE (1 << 31)
123
124 #define HDMI_NV_PDISP_HDMI_CTRL 0x44
125 #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
126 #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
127 #define HDMI_CTRL_ENABLE (1 << 30)
128
129 #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45
130 #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46
131 #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
132 #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
133 #define VSYNC_WINDOW_ENABLE (1 << 31)
134
135 #define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47
136 #define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48
137 #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49
138 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a
139 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b
140 #define HDMI_NV_PDISP_HDMI_EMU0 0x4c
141 #define HDMI_NV_PDISP_HDMI_EMU1 0x4d
142 #define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e
143
144 #define HDMI_NV_PDISP_HDMI_SPARE 0x4f
145 #define SPARE_HW_CTS (1 << 0)
146 #define SPARE_FORCE_SW_CTS (1 << 1)
147 #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
148
149 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50
150 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51
151 #define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL 0x53
152 #define HDMI_NV_PDISP_SOR_CAP 0x54
153 #define HDMI_NV_PDISP_SOR_PWR 0x55
154 #define SOR_PWR_NORMAL_STATE_PD (0 << 0)
155 #define SOR_PWR_NORMAL_STATE_PU (1 << 0)
156 #define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
157 #define SOR_PWR_NORMAL_START_ALT (1 << 1)
158 #define SOR_PWR_SAFE_STATE_PD (0 << 16)
159 #define SOR_PWR_SAFE_STATE_PU (1 << 16)
160 #define SOR_PWR_SETTING_NEW_DONE (0 << 31)
161 #define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
162 #define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
163
164 #define HDMI_NV_PDISP_SOR_TEST 0x56
165 #define HDMI_NV_PDISP_SOR_PLL0 0x57
166 #define SOR_PLL_PWR (1 << 0)
167 #define SOR_PLL_PDBG (1 << 1)
168 #define SOR_PLL_VCAPD (1 << 2)
169 #define SOR_PLL_PDPORT (1 << 3)
170 #define SOR_PLL_RESISTORSEL (1 << 4)
171 #define SOR_PLL_PULLDOWN (1 << 5)
172 #define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
173 #define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
174 #define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
175 #define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
176 #define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
177
178 #define HDMI_NV_PDISP_SOR_PLL1 0x58
179 #define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
180 #define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
181 #define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
182 #define SOR_PLL_PE_EN (1 << 28)
183 #define SOR_PLL_HALF_FULL_PE (1 << 29)
184 #define SOR_PLL_S_D_PIN_PE (1 << 30)
185
186 #define HDMI_NV_PDISP_SOR_PLL2 0x59
187
188 #define HDMI_NV_PDISP_SOR_CSTM 0x5a
189 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
190 #define SOR_CSTM_PLLDIV (1 << 21)
191 #define SOR_CSTM_LVDS_ENABLE (1 << 16)
192 #define SOR_CSTM_MODE_LVDS (0 << 12)
193 #define SOR_CSTM_MODE_TMDS (1 << 12)
194 #define SOR_CSTM_MODE_MASK (3 << 12)
195
196 #define HDMI_NV_PDISP_SOR_LVDS 0x5b
197 #define HDMI_NV_PDISP_SOR_CRCA 0x5c
198 #define HDMI_NV_PDISP_SOR_CRCB 0x5d
199 #define HDMI_NV_PDISP_SOR_BLANK 0x5e
200 #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f
201 #define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)
202 #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
203 #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
204 #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
205 #define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
206 #define SOR_SEQ_STATUS (1 << 28)
207 #define SOR_SEQ_SWITCH (1 << 30)
208
209 #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x))
210
211 #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
212 #define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
213 #define SOR_SEQ_INST_HALT (1 << 15)
214 #define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
215 #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
216 #define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
217 #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
218 #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
219
220 #define HDMI_NV_PDISP_SOR_VCRCA0 0x72
221 #define HDMI_NV_PDISP_SOR_VCRCA1 0x73
222 #define HDMI_NV_PDISP_SOR_CCRCA0 0x74
223 #define HDMI_NV_PDISP_SOR_CCRCA1 0x75
224 #define HDMI_NV_PDISP_SOR_EDATAA0 0x76
225 #define HDMI_NV_PDISP_SOR_EDATAA1 0x77
226 #define HDMI_NV_PDISP_SOR_COUNTA0 0x78
227 #define HDMI_NV_PDISP_SOR_COUNTA1 0x79
228 #define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a
229 #define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b
230 #define HDMI_NV_PDISP_SOR_TRIG 0x7c
231 #define HDMI_NV_PDISP_SOR_MSCHECK 0x7d
232
233 #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e
234 #define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
235 #define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
236 #define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
237 #define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
238 #define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0)
239 #define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8)
240 #define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)
241 #define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)
242
243 #define DRIVE_CURRENT_1_500_mA 0x00
244 #define DRIVE_CURRENT_1_875_mA 0x01
245 #define DRIVE_CURRENT_2_250_mA 0x02
246 #define DRIVE_CURRENT_2_625_mA 0x03
247 #define DRIVE_CURRENT_3_000_mA 0x04
248 #define DRIVE_CURRENT_3_375_mA 0x05
249 #define DRIVE_CURRENT_3_750_mA 0x06
250 #define DRIVE_CURRENT_4_125_mA 0x07
251 #define DRIVE_CURRENT_4_500_mA 0x08
252 #define DRIVE_CURRENT_4_875_mA 0x09
253 #define DRIVE_CURRENT_5_250_mA 0x0a
254 #define DRIVE_CURRENT_5_625_mA 0x0b
255 #define DRIVE_CURRENT_6_000_mA 0x0c
256 #define DRIVE_CURRENT_6_375_mA 0x0d
257 #define DRIVE_CURRENT_6_750_mA 0x0e
258 #define DRIVE_CURRENT_7_125_mA 0x0f
259 #define DRIVE_CURRENT_7_500_mA 0x10
260 #define DRIVE_CURRENT_7_875_mA 0x11
261 #define DRIVE_CURRENT_8_250_mA 0x12
262 #define DRIVE_CURRENT_8_625_mA 0x13
263 #define DRIVE_CURRENT_9_000_mA 0x14
264 #define DRIVE_CURRENT_9_375_mA 0x15
265 #define DRIVE_CURRENT_9_750_mA 0x16
266 #define DRIVE_CURRENT_10_125_mA 0x17
267 #define DRIVE_CURRENT_10_500_mA 0x18
268 #define DRIVE_CURRENT_10_875_mA 0x19
269 #define DRIVE_CURRENT_11_250_mA 0x1a
270 #define DRIVE_CURRENT_11_625_mA 0x1b
271 #define DRIVE_CURRENT_12_000_mA 0x1c
272 #define DRIVE_CURRENT_12_375_mA 0x1d
273 #define DRIVE_CURRENT_12_750_mA 0x1e
274 #define DRIVE_CURRENT_13_125_mA 0x1f
275 #define DRIVE_CURRENT_13_500_mA 0x20
276 #define DRIVE_CURRENT_13_875_mA 0x21
277 #define DRIVE_CURRENT_14_250_mA 0x22
278 #define DRIVE_CURRENT_14_625_mA 0x23
279 #define DRIVE_CURRENT_15_000_mA 0x24
280 #define DRIVE_CURRENT_15_375_mA 0x25
281 #define DRIVE_CURRENT_15_750_mA 0x26
282 #define DRIVE_CURRENT_16_125_mA 0x27
283 #define DRIVE_CURRENT_16_500_mA 0x28
284 #define DRIVE_CURRENT_16_875_mA 0x29
285 #define DRIVE_CURRENT_17_250_mA 0x2a
286 #define DRIVE_CURRENT_17_625_mA 0x2b
287 #define DRIVE_CURRENT_18_000_mA 0x2c
288 #define DRIVE_CURRENT_18_375_mA 0x2d
289 #define DRIVE_CURRENT_18_750_mA 0x2e
290 #define DRIVE_CURRENT_19_125_mA 0x2f
291 #define DRIVE_CURRENT_19_500_mA 0x30
292 #define DRIVE_CURRENT_19_875_mA 0x31
293 #define DRIVE_CURRENT_20_250_mA 0x32
294 #define DRIVE_CURRENT_20_625_mA 0x33
295 #define DRIVE_CURRENT_21_000_mA 0x34
296 #define DRIVE_CURRENT_21_375_mA 0x35
297 #define DRIVE_CURRENT_21_750_mA 0x36
298 #define DRIVE_CURRENT_22_125_mA 0x37
299 #define DRIVE_CURRENT_22_500_mA 0x38
300 #define DRIVE_CURRENT_22_875_mA 0x39
301 #define DRIVE_CURRENT_23_250_mA 0x3a
302 #define DRIVE_CURRENT_23_625_mA 0x3b
303 #define DRIVE_CURRENT_24_000_mA 0x3c
304 #define DRIVE_CURRENT_24_375_mA 0x3d
305 #define DRIVE_CURRENT_24_750_mA 0x3e
306
307 #define DRIVE_CURRENT_0_000_mA_T114 0x00
308 #define DRIVE_CURRENT_0_400_mA_T114 0x01
309 #define DRIVE_CURRENT_0_800_mA_T114 0x02
310 #define DRIVE_CURRENT_1_200_mA_T114 0x03
311 #define DRIVE_CURRENT_1_600_mA_T114 0x04
312 #define DRIVE_CURRENT_2_000_mA_T114 0x05
313 #define DRIVE_CURRENT_2_400_mA_T114 0x06
314 #define DRIVE_CURRENT_2_800_mA_T114 0x07
315 #define DRIVE_CURRENT_3_200_mA_T114 0x08
316 #define DRIVE_CURRENT_3_600_mA_T114 0x09
317 #define DRIVE_CURRENT_4_000_mA_T114 0x0a
318 #define DRIVE_CURRENT_4_400_mA_T114 0x0b
319 #define DRIVE_CURRENT_4_800_mA_T114 0x0c
320 #define DRIVE_CURRENT_5_200_mA_T114 0x0d
321 #define DRIVE_CURRENT_5_600_mA_T114 0x0e
322 #define DRIVE_CURRENT_6_000_mA_T114 0x0f
323 #define DRIVE_CURRENT_6_400_mA_T114 0x10
324 #define DRIVE_CURRENT_6_800_mA_T114 0x11
325 #define DRIVE_CURRENT_7_200_mA_T114 0x12
326 #define DRIVE_CURRENT_7_600_mA_T114 0x13
327 #define DRIVE_CURRENT_8_000_mA_T114 0x14
328 #define DRIVE_CURRENT_8_400_mA_T114 0x15
329 #define DRIVE_CURRENT_8_800_mA_T114 0x16
330 #define DRIVE_CURRENT_9_200_mA_T114 0x17
331 #define DRIVE_CURRENT_9_600_mA_T114 0x18
332 #define DRIVE_CURRENT_10_000_mA_T114 0x19
333 #define DRIVE_CURRENT_10_400_mA_T114 0x1a
334 #define DRIVE_CURRENT_10_800_mA_T114 0x1b
335 #define DRIVE_CURRENT_11_200_mA_T114 0x1c
336 #define DRIVE_CURRENT_11_600_mA_T114 0x1d
337 #define DRIVE_CURRENT_12_000_mA_T114 0x1e
338 #define DRIVE_CURRENT_12_400_mA_T114 0x1f
339 #define DRIVE_CURRENT_12_800_mA_T114 0x20
340 #define DRIVE_CURRENT_13_200_mA_T114 0x21
341 #define DRIVE_CURRENT_13_600_mA_T114 0x22
342 #define DRIVE_CURRENT_14_000_mA_T114 0x23
343 #define DRIVE_CURRENT_14_400_mA_T114 0x24
344 #define DRIVE_CURRENT_14_800_mA_T114 0x25
345 #define DRIVE_CURRENT_15_200_mA_T114 0x26
346 #define DRIVE_CURRENT_15_600_mA_T114 0x27
347 #define DRIVE_CURRENT_16_000_mA_T114 0x28
348 #define DRIVE_CURRENT_16_400_mA_T114 0x29
349 #define DRIVE_CURRENT_16_800_mA_T114 0x2a
350 #define DRIVE_CURRENT_17_200_mA_T114 0x2b
351 #define DRIVE_CURRENT_17_600_mA_T114 0x2c
352 #define DRIVE_CURRENT_18_000_mA_T114 0x2d
353 #define DRIVE_CURRENT_18_400_mA_T114 0x2e
354 #define DRIVE_CURRENT_18_800_mA_T114 0x2f
355 #define DRIVE_CURRENT_19_200_mA_T114 0x30
356 #define DRIVE_CURRENT_19_600_mA_T114 0x31
357 #define DRIVE_CURRENT_20_000_mA_T114 0x32
358 #define DRIVE_CURRENT_20_400_mA_T114 0x33
359 #define DRIVE_CURRENT_20_800_mA_T114 0x34
360 #define DRIVE_CURRENT_21_200_mA_T114 0x35
361 #define DRIVE_CURRENT_21_600_mA_T114 0x36
362 #define DRIVE_CURRENT_22_000_mA_T114 0x37
363 #define DRIVE_CURRENT_22_400_mA_T114 0x38
364 #define DRIVE_CURRENT_22_800_mA_T114 0x39
365 #define DRIVE_CURRENT_23_200_mA_T114 0x3a
366 #define DRIVE_CURRENT_23_600_mA_T114 0x3b
367 #define DRIVE_CURRENT_24_000_mA_T114 0x3c
368 #define DRIVE_CURRENT_24_400_mA_T114 0x3d
369 #define DRIVE_CURRENT_24_800_mA_T114 0x3e
370 #define DRIVE_CURRENT_25_200_mA_T114 0x3f
371 #define DRIVE_CURRENT_25_400_mA_T114 0x40
372 #define DRIVE_CURRENT_25_800_mA_T114 0x41
373 #define DRIVE_CURRENT_26_200_mA_T114 0x42
374 #define DRIVE_CURRENT_26_600_mA_T114 0x43
375 #define DRIVE_CURRENT_27_000_mA_T114 0x44
376 #define DRIVE_CURRENT_27_400_mA_T114 0x45
377 #define DRIVE_CURRENT_27_800_mA_T114 0x46
378 #define DRIVE_CURRENT_28_200_mA_T114 0x47
379
380 #define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
381 #define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
382 #define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
383
384 #define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))
385 #define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
386 #define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
387
388 #define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89
389 #define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a
390 #define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b
391 #define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
392 #define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
393 #define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
394 #define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
395 #define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
396
397 #define HDMI_NV_PDISP_AUDIO_N 0x8c
398 #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
399 #define AUDIO_N_RESETF (1 << 20)
400 #define AUDIO_N_GENERATE_NORMAL (0 << 24)
401 #define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
402
403 #define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94
404 #define HDMI_NV_PDISP_SOR_REFCLK 0x95
405 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
406 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
407
408 #define HDMI_NV_PDISP_CRC_CONTROL 0x96
409 #define HDMI_NV_PDISP_INPUT_CONTROL 0x97
410 #define HDMI_SRC_DISPLAYA (0 << 0)
411 #define HDMI_SRC_DISPLAYB (1 << 0)
412 #define ARM_VIDEO_RANGE_FULL (0 << 1)
413 #define ARM_VIDEO_RANGE_LIMITED (1 << 1)
414
415 #define HDMI_NV_PDISP_SCRATCH 0x98
416 #define HDMI_NV_PDISP_PE_CURRENT 0x99
417 #define PE_CURRENT0(x) (((x) & 0xf) << 0)
418 #define PE_CURRENT1(x) (((x) & 0xf) << 8)
419 #define PE_CURRENT2(x) (((x) & 0xf) << 16)
420 #define PE_CURRENT3(x) (((x) & 0xf) << 24)
421
422 #define PE_CURRENT_0_0_mA 0x0
423 #define PE_CURRENT_0_5_mA 0x1
424 #define PE_CURRENT_1_0_mA 0x2
425 #define PE_CURRENT_1_5_mA 0x3
426 #define PE_CURRENT_2_0_mA 0x4
427 #define PE_CURRENT_2_5_mA 0x5
428 #define PE_CURRENT_3_0_mA 0x6
429 #define PE_CURRENT_3_5_mA 0x7
430 #define PE_CURRENT_4_0_mA 0x8
431 #define PE_CURRENT_4_5_mA 0x9
432 #define PE_CURRENT_5_0_mA 0xa
433 #define PE_CURRENT_5_5_mA 0xb
434 #define PE_CURRENT_6_0_mA 0xc
435 #define PE_CURRENT_6_5_mA 0xd
436 #define PE_CURRENT_7_0_mA 0xe
437 #define PE_CURRENT_7_5_mA 0xf
438
439 #define PE_CURRENT_0_mA_T114 0x0
440 #define PE_CURRENT_1_mA_T114 0x1
441 #define PE_CURRENT_2_mA_T114 0x2
442 #define PE_CURRENT_3_mA_T114 0x3
443 #define PE_CURRENT_4_mA_T114 0x4
444 #define PE_CURRENT_5_mA_T114 0x5
445 #define PE_CURRENT_6_mA_T114 0x6
446 #define PE_CURRENT_7_mA_T114 0x7
447 #define PE_CURRENT_8_mA_T114 0x8
448 #define PE_CURRENT_9_mA_T114 0x9
449 #define PE_CURRENT_10_mA_T114 0xa
450 #define PE_CURRENT_11_mA_T114 0xb
451 #define PE_CURRENT_12_mA_T114 0xc
452 #define PE_CURRENT_13_mA_T114 0xd
453 #define PE_CURRENT_14_mA_T114 0xe
454 #define PE_CURRENT_15_mA_T114 0xf
455
456 #define HDMI_NV_PDISP_KEY_CTRL 0x9a
457 #define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
458 #define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
459 #define HDMI_NV_PDISP_KEY_DEBUG2 0x9d
460 #define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e
461 #define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f
462 #define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0
463 #define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1
464 #define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2
465 #define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
466
467 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac
468 #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
469 #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
470 #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
471 #define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
472 #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0xae
473 #define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27)
474 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0xba
475 #define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)
476 #define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
477 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0xbb
478 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc
479 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd
480 #define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1)
481 #define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0)
482
483 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf
484 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0
485 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0xc1
486 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0xc2
487 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0xc3
488 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0xc4
489 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5
490 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
491
492 #define HDMI_NV_PDISP_INT_STATUS 0xcc
493 #define INT_SCRATCH (1 << 3)
494 #define INT_CP_REQUEST (1 << 2)
495 #define INT_CODEC_SCRATCH1 (1 << 1)
496 #define INT_CODEC_SCRATCH0 (1 << 0)
497 #define HDMI_NV_PDISP_INT_MASK 0xcd
498 #define HDMI_NV_PDISP_INT_ENABLE 0xce
499
500 #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1
501 #define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)
502 #define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)
503 #define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)
504 #define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)
505
506 #define PEAK_CURRENT_0_000_mA 0x00
507 #define PEAK_CURRENT_0_200_mA 0x01
508 #define PEAK_CURRENT_0_400_mA 0x02
509 #define PEAK_CURRENT_0_600_mA 0x03
510 #define PEAK_CURRENT_0_800_mA 0x04
511 #define PEAK_CURRENT_1_000_mA 0x05
512 #define PEAK_CURRENT_1_200_mA 0x06
513 #define PEAK_CURRENT_1_400_mA 0x07
514 #define PEAK_CURRENT_1_600_mA 0x08
515 #define PEAK_CURRENT_1_800_mA 0x09
516 #define PEAK_CURRENT_2_000_mA 0x0a
517 #define PEAK_CURRENT_2_200_mA 0x0b
518 #define PEAK_CURRENT_2_400_mA 0x0c
519 #define PEAK_CURRENT_2_600_mA 0x0d
520 #define PEAK_CURRENT_2_800_mA 0x0e
521 #define PEAK_CURRENT_3_000_mA 0x0f
522 #define PEAK_CURRENT_3_200_mA 0x10
523 #define PEAK_CURRENT_3_400_mA 0x11
524 #define PEAK_CURRENT_3_600_mA 0x12
525 #define PEAK_CURRENT_3_800_mA 0x13
526 #define PEAK_CURRENT_4_000_mA 0x14
527 #define PEAK_CURRENT_4_200_mA 0x15
528 #define PEAK_CURRENT_4_400_mA 0x16
529 #define PEAK_CURRENT_4_600_mA 0x17
530 #define PEAK_CURRENT_4_800_mA 0x18
531 #define PEAK_CURRENT_5_000_mA 0x19
532 #define PEAK_CURRENT_5_200_mA 0x1a
533 #define PEAK_CURRENT_5_400_mA 0x1b
534 #define PEAK_CURRENT_5_600_mA 0x1c
535 #define PEAK_CURRENT_5_800_mA 0x1d
536 #define PEAK_CURRENT_6_000_mA 0x1e
537 #define PEAK_CURRENT_6_200_mA 0x1f
538 #define PEAK_CURRENT_6_400_mA 0x20
539 #define PEAK_CURRENT_6_600_mA 0x21
540 #define PEAK_CURRENT_6_800_mA 0x22
541 #define PEAK_CURRENT_7_000_mA 0x23
542 #define PEAK_CURRENT_7_200_mA 0x24
543 #define PEAK_CURRENT_7_400_mA 0x25
544 #define PEAK_CURRENT_7_600_mA 0x26
545 #define PEAK_CURRENT_7_800_mA 0x27
546 #define PEAK_CURRENT_8_000_mA 0x28
547 #define PEAK_CURRENT_8_200_mA 0x29
548 #define PEAK_CURRENT_8_400_mA 0x2a
549 #define PEAK_CURRENT_8_600_mA 0x2b
550 #define PEAK_CURRENT_8_800_mA 0x2c
551 #define PEAK_CURRENT_9_000_mA 0x2d
552 #define PEAK_CURRENT_9_200_mA 0x2e
553 #define PEAK_CURRENT_9_400_mA 0x2f
554
555 #define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2
556
557 #endif