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6 #ifndef DRM_TEGRA_SOR_H
7 #define DRM_TEGRA_SOR_H
8
9 #define SOR_CTXSW 0x00
10
11 #define SOR_SUPER_STATE0 0x01
12
13 #define SOR_SUPER_STATE1 0x02
14 #define SOR_SUPER_STATE_ATTACHED (1 << 3)
15 #define SOR_SUPER_STATE_MODE_NORMAL (1 << 2)
16 #define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0)
17 #define SOR_SUPER_STATE_HEAD_MODE_AWAKE (2 << 0)
18 #define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
19 #define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0)
20
21 #define SOR_STATE0 0x03
22
23 #define SOR_STATE1 0x04
24 #define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
25 #define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17)
26 #define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17)
27 #define SOR_STATE_ASY_PIXELDEPTH_BPP_30_444 (0x6 << 17)
28 #define SOR_STATE_ASY_PIXELDEPTH_BPP_36_444 (0x8 << 17)
29 #define SOR_STATE_ASY_PIXELDEPTH_BPP_48_444 (0x9 << 17)
30 #define SOR_STATE_ASY_VSYNCPOL (1 << 13)
31 #define SOR_STATE_ASY_HSYNCPOL (1 << 12)
32 #define SOR_STATE_ASY_PROTOCOL_MASK (0xf << 8)
33 #define SOR_STATE_ASY_PROTOCOL_CUSTOM (0xf << 8)
34 #define SOR_STATE_ASY_PROTOCOL_DP_A (0x8 << 8)
35 #define SOR_STATE_ASY_PROTOCOL_DP_B (0x9 << 8)
36 #define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
37 #define SOR_STATE_ASY_PROTOCOL_LVDS (0x0 << 8)
38 #define SOR_STATE_ASY_CRC_MODE_MASK (0x3 << 6)
39 #define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6)
40 #define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6)
41 #define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6)
42 #define SOR_STATE_ASY_OWNER_MASK 0xf
43 #define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0)
44
45 #define SOR_HEAD_STATE0(x) (0x05 + (x))
46 #define SOR_HEAD_STATE_RANGECOMPRESS_MASK (0x1 << 3)
47 #define SOR_HEAD_STATE_DYNRANGE_MASK (0x1 << 2)
48 #define SOR_HEAD_STATE_DYNRANGE_VESA (0 << 2)
49 #define SOR_HEAD_STATE_DYNRANGE_CEA (1 << 2)
50 #define SOR_HEAD_STATE_COLORSPACE_MASK (0x3 << 0)
51 #define SOR_HEAD_STATE_COLORSPACE_RGB (0 << 0)
52 #define SOR_HEAD_STATE1(x) (0x07 + (x))
53 #define SOR_HEAD_STATE2(x) (0x09 + (x))
54 #define SOR_HEAD_STATE3(x) (0x0b + (x))
55 #define SOR_HEAD_STATE4(x) (0x0d + (x))
56 #define SOR_HEAD_STATE5(x) (0x0f + (x))
57 #define SOR_CRC_CNTRL 0x11
58 #define SOR_CRC_CNTRL_ENABLE (1 << 0)
59 #define SOR_DP_DEBUG_MVID 0x12
60
61 #define SOR_CLK_CNTRL 0x13
62 #define SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2)
63 #define SOR_CLK_CNTRL_DP_LINK_SPEED(x) (((x) & 0x1f) << 2)
64 #define SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (0x06 << 2)
65 #define SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70 (0x0a << 2)
66 #define SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40 (0x14 << 2)
67 #define SOR_CLK_CNTRL_DP_CLK_SEL_MASK (3 << 0)
68 #define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0 << 0)
69 #define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1 << 0)
70 #define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2 << 0)
71 #define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3 << 0)
72
73 #define SOR_CAP 0x14
74
75 #define SOR_PWR 0x15
76 #define SOR_PWR_TRIGGER (1 << 31)
77 #define SOR_PWR_MODE_SAFE (1 << 28)
78 #define SOR_PWR_NORMAL_STATE_PU (1 << 0)
79
80 #define SOR_TEST 0x16
81 #define SOR_TEST_CRC_POST_SERIALIZE (1 << 23)
82 #define SOR_TEST_ATTACHED (1 << 10)
83 #define SOR_TEST_HEAD_MODE_MASK (3 << 8)
84 #define SOR_TEST_HEAD_MODE_AWAKE (2 << 8)
85
86 #define SOR_PLL0 0x17
87 #define SOR_PLL0_ICHPMP_MASK (0xf << 24)
88 #define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24)
89 #define SOR_PLL0_FILTER_MASK (0xf << 16)
90 #define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16)
91 #define SOR_PLL0_VCOCAP_MASK (0xf << 8)
92 #define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8)
93 #define SOR_PLL0_VCOCAP_RST SOR_PLL0_VCOCAP(3)
94 #define SOR_PLL0_PLLREG_MASK (0x3 << 6)
95 #define SOR_PLL0_PLLREG_LEVEL(x) (((x) & 0x3) << 6)
96 #define SOR_PLL0_PLLREG_LEVEL_V25 SOR_PLL0_PLLREG_LEVEL(0)
97 #define SOR_PLL0_PLLREG_LEVEL_V15 SOR_PLL0_PLLREG_LEVEL(1)
98 #define SOR_PLL0_PLLREG_LEVEL_V35 SOR_PLL0_PLLREG_LEVEL(2)
99 #define SOR_PLL0_PLLREG_LEVEL_V45 SOR_PLL0_PLLREG_LEVEL(3)
100 #define SOR_PLL0_PULLDOWN (1 << 5)
101 #define SOR_PLL0_RESISTOR_EXT (1 << 4)
102 #define SOR_PLL0_VCOPD (1 << 2)
103 #define SOR_PLL0_PWR (1 << 0)
104
105 #define SOR_PLL1 0x18
106
107 #define SOR_PLL1_LOADADJ_MASK (0xf << 20)
108 #define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20)
109 #define SOR_PLL1_TERM_COMPOUT (1 << 15)
110 #define SOR_PLL1_TMDS_TERMADJ_MASK (0xf << 9)
111 #define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
112 #define SOR_PLL1_TMDS_TERM (1 << 8)
113
114 #define SOR_PLL2 0x19
115 #define SOR_PLL2_LVDS_ENABLE (1 << 25)
116 #define SOR_PLL2_SEQ_PLLCAPPD_ENFORCE (1 << 24)
117 #define SOR_PLL2_PORT_POWERDOWN (1 << 23)
118 #define SOR_PLL2_BANDGAP_POWERDOWN (1 << 22)
119 #define SOR_PLL2_POWERDOWN_OVERRIDE (1 << 18)
120 #define SOR_PLL2_SEQ_PLLCAPPD (1 << 17)
121 #define SOR_PLL2_SEQ_PLL_PULLDOWN (1 << 16)
122
123 #define SOR_PLL3 0x1a
124 #define SOR_PLL3_BG_TEMP_COEF_MASK (0xf << 28)
125 #define SOR_PLL3_BG_TEMP_COEF(x) (((x) & 0xf) << 28)
126 #define SOR_PLL3_BG_VREF_LEVEL_MASK (0xf << 24)
127 #define SOR_PLL3_BG_VREF_LEVEL(x) (((x) & 0xf) << 24)
128 #define SOR_PLL3_PLL_VDD_MODE_1V8 (0 << 13)
129 #define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13)
130 #define SOR_PLL3_AVDD10_LEVEL_MASK (0xf << 8)
131 #define SOR_PLL3_AVDD10_LEVEL(x) (((x) & 0xf) << 8)
132 #define SOR_PLL3_AVDD14_LEVEL_MASK (0xf << 4)
133 #define SOR_PLL3_AVDD14_LEVEL(x) (((x) & 0xf) << 4)
134
135 #define SOR_CSTM 0x1b
136 #define SOR_CSTM_ROTCLK_MASK (0xf << 24)
137 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
138 #define SOR_CSTM_LVDS (1 << 16)
139 #define SOR_CSTM_LINK_ACT_B (1 << 15)
140 #define SOR_CSTM_LINK_ACT_A (1 << 14)
141 #define SOR_CSTM_UPPER (1 << 11)
142
143 #define SOR_LVDS 0x1c
144 #define SOR_CRCA 0x1d
145 #define SOR_CRCA_VALID (1 << 0)
146 #define SOR_CRCA_RESET (1 << 0)
147 #define SOR_CRCB 0x1e
148 #define SOR_BLANK 0x1f
149 #define SOR_SEQ_CTL 0x20
150 #define SOR_SEQ_CTL_PD_PC_ALT(x) (((x) & 0xf) << 12)
151 #define SOR_SEQ_CTL_PD_PC(x) (((x) & 0xf) << 8)
152 #define SOR_SEQ_CTL_PU_PC_ALT(x) (((x) & 0xf) << 4)
153 #define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0)
154
155 #define SOR_LANE_SEQ_CTL 0x21
156 #define SOR_LANE_SEQ_CTL_TRIGGER (1 << 31)
157 #define SOR_LANE_SEQ_CTL_STATE_BUSY (1 << 28)
158 #define SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
159 #define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
160 #define SOR_LANE_SEQ_CTL_POWER_STATE_UP (0 << 16)
161 #define SOR_LANE_SEQ_CTL_POWER_STATE_DOWN (1 << 16)
162 #define SOR_LANE_SEQ_CTL_DELAY(x) (((x) & 0xf) << 12)
163
164 #define SOR_SEQ_INST(x) (0x22 + (x))
165 #define SOR_SEQ_INST_PLL_PULLDOWN (1 << 31)
166 #define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)
167 #define SOR_SEQ_INST_ASSERT_PLL_RESET (1 << 29)
168 #define SOR_SEQ_INST_BLANK_V (1 << 28)
169 #define SOR_SEQ_INST_BLANK_H (1 << 27)
170 #define SOR_SEQ_INST_BLANK_DE (1 << 26)
171 #define SOR_SEQ_INST_BLACK_DATA (1 << 25)
172 #define SOR_SEQ_INST_TRISTATE_IOS (1 << 24)
173 #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
174 #define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
175 #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
176 #define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
177 #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
178 #define SOR_SEQ_INST_SEQUENCE_UP (0 << 19)
179 #define SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19)
180 #define SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18)
181 #define SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18)
182 #define SOR_SEQ_INST_PORT_POWERDOWN (1 << 17)
183 #define SOR_SEQ_INST_PLL_POWERDOWN (1 << 16)
184 #define SOR_SEQ_INST_HALT (1 << 15)
185 #define SOR_SEQ_INST_WAIT_US (0 << 12)
186 #define SOR_SEQ_INST_WAIT_MS (1 << 12)
187 #define SOR_SEQ_INST_WAIT_VSYNC (2 << 12)
188 #define SOR_SEQ_INST_WAIT(x) (((x) & 0x3ff) << 0)
189
190 #define SOR_PWM_DIV 0x32
191 #define SOR_PWM_DIV_MASK 0xffffff
192
193 #define SOR_PWM_CTL 0x33
194 #define SOR_PWM_CTL_TRIGGER (1 << 31)
195 #define SOR_PWM_CTL_CLK_SEL (1 << 30)
196 #define SOR_PWM_CTL_DUTY_CYCLE_MASK 0xffffff
197
198 #define SOR_VCRC_A0 0x34
199 #define SOR_VCRC_A1 0x35
200 #define SOR_VCRC_B0 0x36
201 #define SOR_VCRC_B1 0x37
202 #define SOR_CCRC_A0 0x38
203 #define SOR_CCRC_A1 0x39
204 #define SOR_CCRC_B0 0x3a
205 #define SOR_CCRC_B1 0x3b
206 #define SOR_EDATA_A0 0x3c
207 #define SOR_EDATA_A1 0x3d
208 #define SOR_EDATA_B0 0x3e
209 #define SOR_EDATA_B1 0x3f
210 #define SOR_COUNT_A0 0x40
211 #define SOR_COUNT_A1 0x41
212 #define SOR_COUNT_B0 0x42
213 #define SOR_COUNT_B1 0x43
214 #define SOR_DEBUG_A0 0x44
215 #define SOR_DEBUG_A1 0x45
216 #define SOR_DEBUG_B0 0x46
217 #define SOR_DEBUG_B1 0x47
218 #define SOR_TRIG 0x48
219 #define SOR_MSCHECK 0x49
220 #define SOR_XBAR_CTRL 0x4a
221 #define SOR_XBAR_CTRL_LINK1_XSEL(channel, value) ((((value) & 0x7) << ((channel) * 3)) << 17)
222 #define SOR_XBAR_CTRL_LINK0_XSEL(channel, value) ((((value) & 0x7) << ((channel) * 3)) << 2)
223 #define SOR_XBAR_CTRL_LINK_SWAP (1 << 1)
224 #define SOR_XBAR_CTRL_BYPASS (1 << 0)
225 #define SOR_XBAR_POL 0x4b
226
227 #define SOR_DP_LINKCTL0 0x4c
228 #define SOR_DP_LINKCTL_LANE_COUNT_MASK (0x1f << 16)
229 #define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16)
230 #define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14)
231 #define SOR_DP_LINKCTL_TU_SIZE_MASK (0x7f << 2)
232 #define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2)
233 #define SOR_DP_LINKCTL_ENABLE (1 << 0)
234
235 #define SOR_DP_LINKCTL1 0x4d
236
237 #define SOR_LANE_DRIVE_CURRENT0 0x4e
238 #define SOR_LANE_DRIVE_CURRENT1 0x4f
239 #define SOR_LANE4_DRIVE_CURRENT0 0x50
240 #define SOR_LANE4_DRIVE_CURRENT1 0x51
241 #define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24)
242 #define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16)
243 #define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8)
244 #define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0)
245
246 #define SOR_LANE_PREEMPHASIS0 0x52
247 #define SOR_LANE_PREEMPHASIS1 0x53
248 #define SOR_LANE4_PREEMPHASIS0 0x54
249 #define SOR_LANE4_PREEMPHASIS1 0x55
250 #define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24)
251 #define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16)
252 #define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8)
253 #define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0)
254
255 #define SOR_LANE_POSTCURSOR0 0x56
256 #define SOR_LANE_POSTCURSOR1 0x57
257 #define SOR_LANE_POSTCURSOR_LANE3(x) (((x) & 0xff) << 24)
258 #define SOR_LANE_POSTCURSOR_LANE2(x) (((x) & 0xff) << 16)
259 #define SOR_LANE_POSTCURSOR_LANE1(x) (((x) & 0xff) << 8)
260 #define SOR_LANE_POSTCURSOR_LANE0(x) (((x) & 0xff) << 0)
261
262 #define SOR_DP_CONFIG0 0x58
263 #define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31)
264 #define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26)
265 #define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24)
266 #define SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK (0xf << 16)
267 #define SOR_DP_CONFIG_ACTIVE_SYM_FRAC(x) (((x) & 0xf) << 16)
268 #define SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK (0x7f << 8)
269 #define SOR_DP_CONFIG_ACTIVE_SYM_COUNT(x) (((x) & 0x7f) << 8)
270 #define SOR_DP_CONFIG_WATERMARK_MASK (0x3f << 0)
271 #define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0)
272
273 #define SOR_DP_CONFIG1 0x59
274 #define SOR_DP_MN0 0x5a
275 #define SOR_DP_MN1 0x5b
276
277 #define SOR_DP_PADCTL0 0x5c
278 #define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23)
279 #define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22)
280 #define SOR_DP_PADCTL_TX_PU_MASK (0xff << 8)
281 #define SOR_DP_PADCTL_TX_PU(x) (((x) & 0xff) << 8)
282 #define SOR_DP_PADCTL_CM_TXD_3 (1 << 7)
283 #define SOR_DP_PADCTL_CM_TXD_2 (1 << 6)
284 #define SOR_DP_PADCTL_CM_TXD_1 (1 << 5)
285 #define SOR_DP_PADCTL_CM_TXD_0 (1 << 4)
286 #define SOR_DP_PADCTL_PD_TXD_3 (1 << 3)
287 #define SOR_DP_PADCTL_PD_TXD_0 (1 << 2)
288 #define SOR_DP_PADCTL_PD_TXD_1 (1 << 1)
289 #define SOR_DP_PADCTL_PD_TXD_2 (1 << 0)
290
291 #define SOR_DP_PADCTL1 0x5d
292
293 #define SOR_DP_DEBUG0 0x5e
294 #define SOR_DP_DEBUG1 0x5f
295
296 #define SOR_DP_SPARE0 0x60
297 #define SOR_DP_SPARE_DISP_VIDEO_PREAMBLE (1 << 3)
298 #define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2)
299 #define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
300 #define SOR_DP_SPARE_SEQ_ENABLE (1 << 0)
301
302 #define SOR_DP_SPARE1 0x61
303 #define SOR_DP_AUDIO_CTRL 0x62
304
305 #define SOR_DP_AUDIO_HBLANK_SYMBOLS 0x63
306 #define SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x01ffff << 0)
307
308 #define SOR_DP_AUDIO_VBLANK_SYMBOLS 0x64
309 #define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1fffff << 0)
310
311 #define SOR_DP_GENERIC_INFOFRAME_HEADER 0x65
312 #define SOR_DP_GENERIC_INFOFRAME_SUBPACK0 0x66
313 #define SOR_DP_GENERIC_INFOFRAME_SUBPACK1 0x67
314 #define SOR_DP_GENERIC_INFOFRAME_SUBPACK2 0x68
315 #define SOR_DP_GENERIC_INFOFRAME_SUBPACK3 0x69
316 #define SOR_DP_GENERIC_INFOFRAME_SUBPACK4 0x6a
317 #define SOR_DP_GENERIC_INFOFRAME_SUBPACK5 0x6b
318 #define SOR_DP_GENERIC_INFOFRAME_SUBPACK6 0x6c
319
320 #define SOR_DP_TPG 0x6d
321 #define SOR_DP_TPG_CHANNEL_CODING (1 << 6)
322 #define SOR_DP_TPG_SCRAMBLER_MASK (3 << 4)
323 #define SOR_DP_TPG_SCRAMBLER_FIBONACCI (2 << 4)
324 #define SOR_DP_TPG_SCRAMBLER_GALIOS (1 << 4)
325 #define SOR_DP_TPG_SCRAMBLER_NONE (0 << 4)
326 #define SOR_DP_TPG_PATTERN_MASK (0xf << 0)
327 #define SOR_DP_TPG_PATTERN_HBR2 (0x8 << 0)
328 #define SOR_DP_TPG_PATTERN_CSTM (0x7 << 0)
329 #define SOR_DP_TPG_PATTERN_PRBS7 (0x6 << 0)
330 #define SOR_DP_TPG_PATTERN_SBLERRRATE (0x5 << 0)
331 #define SOR_DP_TPG_PATTERN_D102 (0x4 << 0)
332 #define SOR_DP_TPG_PATTERN_TRAIN3 (0x3 << 0)
333 #define SOR_DP_TPG_PATTERN_TRAIN2 (0x2 << 0)
334 #define SOR_DP_TPG_PATTERN_TRAIN1 (0x1 << 0)
335 #define SOR_DP_TPG_PATTERN_NONE (0x0 << 0)
336
337 #define SOR_DP_TPG_CONFIG 0x6e
338 #define SOR_DP_LQ_CSTM0 0x6f
339 #define SOR_DP_LQ_CSTM1 0x70
340 #define SOR_DP_LQ_CSTM2 0x71
341
342 #define SOR_DP_PADCTL2 0x73
343 #define SOR_DP_PADCTL_SPAREPLL_MASK (0xff << 24)
344 #define SOR_DP_PADCTL_SPAREPLL(x) (((x) & 0xff) << 24)
345
346 #define SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a
347 #define SOR_HDMI_AUDIO_INFOFRAME_STATUS 0x9b
348 #define SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c
349
350 #define SOR_HDMI_AVI_INFOFRAME_CTRL 0x9f
351 #define INFOFRAME_CTRL_CHECKSUM_ENABLE (1 << 9)
352 #define INFOFRAME_CTRL_SINGLE (1 << 8)
353 #define INFOFRAME_CTRL_OTHER (1 << 4)
354 #define INFOFRAME_CTRL_ENABLE (1 << 0)
355
356 #define SOR_HDMI_AVI_INFOFRAME_STATUS 0xa0
357 #define INFOFRAME_STATUS_DONE (1 << 0)
358
359 #define SOR_HDMI_AVI_INFOFRAME_HEADER 0xa1
360 #define INFOFRAME_HEADER_LEN(x) (((x) & 0xff) << 16)
361 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
362 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
363
364 #define SOR_HDMI_ACR_CTRL 0xb1
365
366 #define SOR_HDMI_ACR_0320_SUBPACK_LOW 0xb2
367 #define SOR_HDMI_ACR_SUBPACK_LOW_SB1(x) (((x) & 0xff) << 24)
368
369 #define SOR_HDMI_ACR_0320_SUBPACK_HIGH 0xb3
370 #define SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE (1 << 31)
371
372 #define SOR_HDMI_ACR_0441_SUBPACK_LOW 0xb4
373 #define SOR_HDMI_ACR_0441_SUBPACK_HIGH 0xb5
374
375 #define SOR_HDMI_CTRL 0xc0
376 #define SOR_HDMI_CTRL_ENABLE (1 << 30)
377 #define SOR_HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
378 #define SOR_HDMI_CTRL_AUDIO_LAYOUT (1 << 10)
379 #define SOR_HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
380
381 #define SOR_HDMI_SPARE 0xcb
382 #define SOR_HDMI_SPARE_ACR_PRIORITY_HIGH (1 << 31)
383 #define SOR_HDMI_SPARE_CTS_RESET(x) (((x) & 0x7) << 16)
384 #define SOR_HDMI_SPARE_HW_CTS_ENABLE (1 << 0)
385
386 #define SOR_REFCLK 0xe6
387 #define SOR_REFCLK_DIV_INT(x) ((((x) >> 2) & 0xff) << 8)
388 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x3) << 6)
389
390 #define SOR_INPUT_CONTROL 0xe8
391 #define SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED (1 << 1)
392 #define SOR_INPUT_CONTROL_HDMI_SRC_SELECT(x) (((x) & 0x1) << 0)
393
394 #define SOR_AUDIO_CNTRL 0xfc
395 #define SOR_AUDIO_CNTRL_INJECT_NULLSMPL (1 << 29)
396 #define SOR_AUDIO_CNTRL_SOURCE_SELECT(x) (((x) & 0x3) << 20)
397 #define SOURCE_SELECT_MASK 0x3
398 #define SOURCE_SELECT_HDA 0x2
399 #define SOURCE_SELECT_SPDIF 0x1
400 #define SOURCE_SELECT_AUTO 0x0
401 #define SOR_AUDIO_CNTRL_AFIFO_FLUSH (1 << 12)
402
403 #define SOR_AUDIO_SPARE 0xfe
404 #define SOR_AUDIO_SPARE_HBR_ENABLE (1 << 27)
405
406 #define SOR_AUDIO_NVAL_0320 0xff
407 #define SOR_AUDIO_NVAL_0441 0x100
408 #define SOR_AUDIO_NVAL_0882 0x101
409 #define SOR_AUDIO_NVAL_1764 0x102
410 #define SOR_AUDIO_NVAL_0480 0x103
411 #define SOR_AUDIO_NVAL_0960 0x104
412 #define SOR_AUDIO_NVAL_1920 0x105
413
414 #define SOR_AUDIO_HDA_CODEC_SCRATCH0 0x10a
415 #define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)
416 #define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
417
418 #define SOR_AUDIO_HDA_ELD_BUFWR 0x10c
419 #define SOR_AUDIO_HDA_ELD_BUFWR_INDEX(x) (((x) & 0xff) << 8)
420 #define SOR_AUDIO_HDA_ELD_BUFWR_DATA(x) (((x) & 0xff) << 0)
421
422 #define SOR_AUDIO_HDA_PRESENSE 0x10d
423 #define SOR_AUDIO_HDA_PRESENSE_ELDV (1 << 1)
424 #define SOR_AUDIO_HDA_PRESENSE_PD (1 << 0)
425
426 #define SOR_AUDIO_AVAL_0320 0x10f
427 #define SOR_AUDIO_AVAL_0441 0x110
428 #define SOR_AUDIO_AVAL_0882 0x111
429 #define SOR_AUDIO_AVAL_1764 0x112
430 #define SOR_AUDIO_AVAL_0480 0x113
431 #define SOR_AUDIO_AVAL_0960 0x114
432 #define SOR_AUDIO_AVAL_1920 0x115
433
434 #define SOR_INT_STATUS 0x11c
435 #define SOR_INT_CODEC_CP_REQUEST (1 << 2)
436 #define SOR_INT_CODEC_SCRATCH1 (1 << 1)
437 #define SOR_INT_CODEC_SCRATCH0 (1 << 0)
438
439 #define SOR_INT_MASK 0x11d
440 #define SOR_INT_ENABLE 0x11e
441
442 #define SOR_HDMI_VSI_INFOFRAME_CTRL 0x123
443 #define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124
444 #define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
445
446 #define SOR_HDMI_AUDIO_N 0x13c
447 #define SOR_HDMI_AUDIO_N_LOOKUP (1 << 28)
448 #define SOR_HDMI_AUDIO_N_RESET (1 << 20)
449
450 #define SOR_HDMI2_CTRL 0x13e
451 #define SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 (1 << 1)
452 #define SOR_HDMI2_CTRL_SCRAMBLE (1 << 0)
453
454 #endif