root/drivers/gpu/drm/drm_edid.c

DEFINITIONS

1. drm_edid_header_is_valid
2. drm_edid_block_checksum
3. drm_edid_is_zero
4. drm_edid_block_valid
5. drm_edid_is_valid
6. drm_do_probe_ddc_edid
7. connector_bad_edid
8. drm_get_override_edid
9. drm_add_override_edid_modes
10. drm_do_get_edid
11. drm_probe_ddc
12. drm_get_edid
13. drm_get_edid_switcheroo
14. drm_edid_duplicate
15. edid_vendor
16. edid_get_quirks
17. edid_fixup_preferred
18. mode_is_rb
19. drm_mode_find_dmt
20. cea_for_each_detailed_block
21. vtb_for_each_detailed_block
22. drm_for_each_detailed_block
23. is_rb
24. drm_monitor_supports_rb
25. find_gtf2
26. drm_gtf2_hbreak
27. drm_gtf2_2c
28. drm_gtf2_m
29. drm_gtf2_k
30. drm_gtf2_2j
31. standard_timing_level
32. bad_std_timing
33. drm_mode_std
34. drm_mode_do_interlace_quirk
35. drm_mode_detailed
36. mode_in_hsync_range
37. mode_in_vsync_range
38. range_pixel_clock
39. mode_in_range
40. valid_inferred_mode
41. drm_dmt_modes_for_range
42. drm_mode_fixup_1366x768
43. drm_gtf_modes_for_range
44. drm_cvt_modes_for_range
45. do_inferred_modes
46. add_inferred_modes
47. drm_est3_modes
48. do_established_modes
49. add_established_modes
50. do_standard_modes
51. add_standard_modes
52. drm_cvt_modes
53. do_cvt_mode
54. add_cvt_modes
55. do_detailed_mode
56. add_detailed_modes
57. drm_find_edid_extension
58. drm_find_displayid_extension
59. drm_find_cea_extension
60. cea_mode_alternate_clock
61. cea_mode_alternate_timings
62. drm_match_cea_mode_clock_tolerance
63. drm_match_cea_mode
64. drm_valid_cea_vic
65. drm_get_cea_aspect_ratio
66. hdmi_mode_alternate_clock
67. drm_match_hdmi_mode_clock_tolerance
68. drm_match_hdmi_mode
69. drm_valid_hdmi_vic
70. add_alternate_cea_modes
71. svd_to_vic
72. drm_display_mode_from_vic_index
73. do_y420vdb_modes
74. drm_add_cmdb_modes
75. do_cea_modes
76. stereo_match_mandatory
77. add_hdmi_mandatory_stereo_modes
78. add_hdmi_mode
79. add_3d_struct_modes
80. do_hdmi_vsdb_modes
81. cea_db_payload_len
82. cea_db_extended_tag
83. cea_db_tag
84. cea_revision
85. cea_db_offsets
86. cea_db_is_hdmi_vsdb
87. cea_db_is_hdmi_forum_vsdb
88. cea_db_is_vcdb
89. cea_db_is_y420cmdb
90. cea_db_is_y420vdb
91. drm_parse_y420cmdb_bitmap
92. add_cea_modes
93. fixup_detailed_cea_mode_clock
94. cea_db_is_hdmi_hdr_metadata_block
95. eotf_supported
96. hdr_metadata_type
97. drm_parse_hdr_metadata_block
98. drm_parse_hdmi_vsdb_audio
99. monitor_name
100. get_monitor_name
101. drm_edid_get_monitor_name
102. clear_eld
103. drm_edid_to_eld
104. drm_edid_to_sad
105. drm_edid_to_speaker_allocation
106. drm_av_sync_delay
107. drm_detect_hdmi_monitor
108. drm_detect_monitor_audio
109. drm_default_rgb_quant_range
110. drm_parse_vcdb
111. drm_parse_ycbcr420_deep_color_info
112. drm_parse_hdmi_forum_vsdb
113. drm_parse_hdmi_deep_color_info
114. drm_parse_hdmi_vsdb_video
115. drm_parse_cea_ext
116. drm_reset_display_info
117. drm_add_display_info
118. validate_displayid
119. drm_mode_displayid_detailed
120. add_displayid_detailed_1_modes
121. add_displayid_detailed_modes
122. drm_add_edid_modes
123. drm_add_modes_noedid
124. drm_set_preferred_mode
125. is_hdmi2_sink
126. is_eotf_supported
127. drm_hdmi_infoframe_set_hdr_metadata
128. drm_hdmi_avi_infoframe_from_display_mode
129. drm_hdmi_avi_infoframe_colorspace
130. drm_hdmi_avi_infoframe_quant_range
131. s3d_structure_from_display_mode
132. drm_hdmi_vendor_infoframe_from_display_mode
133. drm_parse_tiled_block
134. drm_parse_display_id
135. drm_get_displayid

   1 /*
   2  * Copyright (c) 2006 Luc Verhaegen (quirks list)
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  * Copyright 2010 Red Hat, Inc.
   6  *
   7  * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
   8  * FB layer.
   9  *   Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
  10  *
  11  * Permission is hereby granted, free of charge, to any person obtaining a
  12  * copy of this software and associated documentation files (the "Software"),
  13  * to deal in the Software without restriction, including without limitation
  14  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  15  * and/or sell copies of the Software, and to permit persons to whom the
  16  * Software is furnished to do so, subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice (including the
  19  * next paragraph) shall be included in all copies or substantial portions
  20  * of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  27  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28  * DEALINGS IN THE SOFTWARE.
  29  */
  30 
  31 #include <linux/hdmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/slab.h>
  36 #include <linux/vga_switcheroo.h>
  37 
  38 #include <drm/drm_displayid.h>
  39 #include <drm/drm_drv.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_encoder.h>
  42 #include <drm/drm_print.h>
  43 #include <drm/drm_scdc_helper.h>
  44 
  45 #include "drm_crtc_internal.h"
  46 
  47 #define version_greater(edid, maj, min) \
  48         (((edid)->version > (maj)) || \
  49          ((edid)->version == (maj) && (edid)->revision > (min)))
  50 
  51 #define EDID_EST_TIMINGS 16
  52 #define EDID_STD_TIMINGS 8
  53 #define EDID_DETAILED_TIMINGS 4
  54 
  55 /*
  56  * EDID blocks out in the wild have a variety of bugs, try to collect
  57  * them here (note that userspace may work around broken monitors first,
  58  * but fixes should make their way here so that the kernel "just works"
  59  * on as many displays as possible).
  60  */
  61 
  62 /* First detailed mode wrong, use largest 60Hz mode */
  63 #define EDID_QUIRK_PREFER_LARGE_60              (1 << 0)
  64 /* Reported 135MHz pixel clock is too high, needs adjustment */
  65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH           (1 << 1)
  66 /* Prefer the largest mode at 75 Hz */
  67 #define EDID_QUIRK_PREFER_LARGE_75              (1 << 2)
  68 /* Detail timing is in cm not mm */
  69 #define EDID_QUIRK_DETAILED_IN_CM               (1 << 3)
  70 /* Detailed timing descriptors have bogus size values, so just take the
  71  * maximum size and use that.
  72  */
  73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE    (1 << 4)
  74 /* use +hsync +vsync for detailed mode */
  75 #define EDID_QUIRK_DETAILED_SYNC_PP             (1 << 6)
  76 /* Force reduced-blanking timings for detailed modes */
  77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING       (1 << 7)
  78 /* Force 8bpc */
  79 #define EDID_QUIRK_FORCE_8BPC                   (1 << 8)
  80 /* Force 12bpc */
  81 #define EDID_QUIRK_FORCE_12BPC                  (1 << 9)
  82 /* Force 6bpc */
  83 #define EDID_QUIRK_FORCE_6BPC                   (1 << 10)
  84 /* Force 10bpc */
  85 #define EDID_QUIRK_FORCE_10BPC                  (1 << 11)
  86 /* Non desktop display (i.e. HMD) */
  87 #define EDID_QUIRK_NON_DESKTOP                  (1 << 12)
  88 
  89 struct detailed_mode_closure {
  90         struct drm_connector *connector;
  91         struct edid *edid;
  92         bool preferred;
  93         u32 quirks;
  94         int modes;
  95 };
  96 
  97 #define LEVEL_DMT       0
  98 #define LEVEL_GTF       1
  99 #define LEVEL_GTF2      2
 100 #define LEVEL_CVT       3
 101 
 102 static const struct edid_quirk {
 103         char vendor[4];
 104         int product_id;
 105         u32 quirks;
 106 } edid_quirk_list[] = {
 107         /* Acer AL1706 */
 108         { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
 109         /* Acer F51 */
 110         { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
 111 
 112         /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
 113         { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
 114 
 115         /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
 116         { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
 117 
 118         /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
 119         { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
 120 
 121         /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
 122         { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
 123 
 124         /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
 125         { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
 126 
 127         /* Belinea 10 15 55 */
 128         { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
 129         { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
 130 
 131         /* Envision Peripherals, Inc. EN-7100e */
 132         { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
 133         /* Envision EN2028 */
 134         { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
 135 
 136         /* Funai Electronics PM36B */
 137         { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
 138           EDID_QUIRK_DETAILED_IN_CM },
 139 
 140         /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
 141         { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
 142 
 143         /* LG Philips LCD LP154W01-A5 */
 144         { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 145         { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 146 
 147         /* Samsung SyncMaster 205BW.  Note: irony */
 148         { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
 149         /* Samsung SyncMaster 22[5-6]BW */
 150         { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
 151         { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
 152 
 153         /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
 154         { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
 155 
 156         /* ViewSonic VA2026w */
 157         { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
 158 
 159         /* Medion MD 30217 PG */
 160         { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
 161 
 162         /* Lenovo G50 */
 163         { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
 164 
 165         /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
 166         { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
 167 
 168         /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
 169         { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
 170 
 171         /* Valve Index Headset */
 172         { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
 173         { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
 174         { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
 175         { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
 176         { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
 177         { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
 178         { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
 179         { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
 180         { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
 181         { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
 182         { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
 183         { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
 184         { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
 185         { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
 186         { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
 187         { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
 188         { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
 189 
 190         /* HTC Vive and Vive Pro VR Headsets */
 191         { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
 192         { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
 193 
 194         /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
 195         { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
 196         { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
 197         { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
 198         { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
 199 
 200         /* Windows Mixed Reality Headsets */
 201         { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 202         { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
 203         { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
 204         { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
 205         { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
 206         { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 207         { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
 208         { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
 209 
 210         /* Sony PlayStation VR Headset */
 211         { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
 212 
 213         /* Sensics VR Headsets */
 214         { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
 215 
 216         /* OSVR HDK and HDK2 VR Headsets */
 217         { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
 218 };
 219 
 220 /*
 221  * Autogenerated from the DMT spec.
 222  * This table is copied from xfree86/modes/xf86EdidModes.c.
 223  */
 224 static const struct drm_display_mode drm_dmt_modes[] = {
 225         /* 0x01 - 640x350@85Hz */
 226         { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 227                    736, 832, 0, 350, 382, 385, 445, 0,
 228                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 229         /* 0x02 - 640x400@85Hz */
 230         { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 231                    736, 832, 0, 400, 401, 404, 445, 0,
 232                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 233         /* 0x03 - 720x400@85Hz */
 234         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
 235                    828, 936, 0, 400, 401, 404, 446, 0,
 236                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 237         /* 0x04 - 640x480@60Hz */
 238         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 239                    752, 800, 0, 480, 490, 492, 525, 0,
 240                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 241         /* 0x05 - 640x480@72Hz */
 242         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 243                    704, 832, 0, 480, 489, 492, 520, 0,
 244                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 245         /* 0x06 - 640x480@75Hz */
 246         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 247                    720, 840, 0, 480, 481, 484, 500, 0,
 248                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 249         /* 0x07 - 640x480@85Hz */
 250         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
 251                    752, 832, 0, 480, 481, 484, 509, 0,
 252                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 253         /* 0x08 - 800x600@56Hz */
 254         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 255                    896, 1024, 0, 600, 601, 603, 625, 0,
 256                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 257         /* 0x09 - 800x600@60Hz */
 258         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 259                    968, 1056, 0, 600, 601, 605, 628, 0,
 260                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 261         /* 0x0a - 800x600@72Hz */
 262         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 263                    976, 1040, 0, 600, 637, 643, 666, 0,
 264                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 265         /* 0x0b - 800x600@75Hz */
 266         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 267                    896, 1056, 0, 600, 601, 604, 625, 0,
 268                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 269         /* 0x0c - 800x600@85Hz */
 270         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
 271                    896, 1048, 0, 600, 601, 604, 631, 0,
 272                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 273         /* 0x0d - 800x600@120Hz RB */
 274         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
 275                    880, 960, 0, 600, 603, 607, 636, 0,
 276                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 277         /* 0x0e - 848x480@60Hz */
 278         { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
 279                    976, 1088, 0, 480, 486, 494, 517, 0,
 280                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 281         /* 0x0f - 1024x768@43Hz, interlace */
 282         { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
 283                    1208, 1264, 0, 768, 768, 776, 817, 0,
 284                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 285                    DRM_MODE_FLAG_INTERLACE) },
 286         /* 0x10 - 1024x768@60Hz */
 287         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 288                    1184, 1344, 0, 768, 771, 777, 806, 0,
 289                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 290         /* 0x11 - 1024x768@70Hz */
 291         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 292                    1184, 1328, 0, 768, 771, 777, 806, 0,
 293                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 294         /* 0x12 - 1024x768@75Hz */
 295         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 296                    1136, 1312, 0, 768, 769, 772, 800, 0,
 297                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 298         /* 0x13 - 1024x768@85Hz */
 299         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
 300                    1168, 1376, 0, 768, 769, 772, 808, 0,
 301                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 302         /* 0x14 - 1024x768@120Hz RB */
 303         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
 304                    1104, 1184, 0, 768, 771, 775, 813, 0,
 305                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 306         /* 0x15 - 1152x864@75Hz */
 307         { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 308                    1344, 1600, 0, 864, 865, 868, 900, 0,
 309                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 310         /* 0x55 - 1280x720@60Hz */
 311         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 312                    1430, 1650, 0, 720, 725, 730, 750, 0,
 313                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 314         /* 0x16 - 1280x768@60Hz RB */
 315         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
 316                    1360, 1440, 0, 768, 771, 778, 790, 0,
 317                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 318         /* 0x17 - 1280x768@60Hz */
 319         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
 320                    1472, 1664, 0, 768, 771, 778, 798, 0,
 321                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 322         /* 0x18 - 1280x768@75Hz */
 323         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
 324                    1488, 1696, 0, 768, 771, 778, 805, 0,
 325                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 326         /* 0x19 - 1280x768@85Hz */
 327         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
 328                    1496, 1712, 0, 768, 771, 778, 809, 0,
 329                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 330         /* 0x1a - 1280x768@120Hz RB */
 331         { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
 332                    1360, 1440, 0, 768, 771, 778, 813, 0,
 333                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 334         /* 0x1b - 1280x800@60Hz RB */
 335         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
 336                    1360, 1440, 0, 800, 803, 809, 823, 0,
 337                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 338         /* 0x1c - 1280x800@60Hz */
 339         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
 340                    1480, 1680, 0, 800, 803, 809, 831, 0,
 341                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 342         /* 0x1d - 1280x800@75Hz */
 343         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
 344                    1488, 1696, 0, 800, 803, 809, 838, 0,
 345                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 346         /* 0x1e - 1280x800@85Hz */
 347         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
 348                    1496, 1712, 0, 800, 803, 809, 843, 0,
 349                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 350         /* 0x1f - 1280x800@120Hz RB */
 351         { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
 352                    1360, 1440, 0, 800, 803, 809, 847, 0,
 353                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 354         /* 0x20 - 1280x960@60Hz */
 355         { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
 356                    1488, 1800, 0, 960, 961, 964, 1000, 0,
 357                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 358         /* 0x21 - 1280x960@85Hz */
 359         { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
 360                    1504, 1728, 0, 960, 961, 964, 1011, 0,
 361                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 362         /* 0x22 - 1280x960@120Hz RB */
 363         { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
 364                    1360, 1440, 0, 960, 963, 967, 1017, 0,
 365                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 366         /* 0x23 - 1280x1024@60Hz */
 367         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
 368                    1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 369                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 370         /* 0x24 - 1280x1024@75Hz */
 371         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 372                    1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 373                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 374         /* 0x25 - 1280x1024@85Hz */
 375         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
 376                    1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
 377                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 378         /* 0x26 - 1280x1024@120Hz RB */
 379         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
 380                    1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
 381                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 382         /* 0x27 - 1360x768@60Hz */
 383         { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
 384                    1536, 1792, 0, 768, 771, 777, 795, 0,
 385                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 386         /* 0x28 - 1360x768@120Hz RB */
 387         { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
 388                    1440, 1520, 0, 768, 771, 776, 813, 0,
 389                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 390         /* 0x51 - 1366x768@60Hz */
 391         { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
 392                    1579, 1792, 0, 768, 771, 774, 798, 0,
 393                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 394         /* 0x56 - 1366x768@60Hz */
 395         { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
 396                    1436, 1500, 0, 768, 769, 772, 800, 0,
 397                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 398         /* 0x29 - 1400x1050@60Hz RB */
 399         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
 400                    1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
 401                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 402         /* 0x2a - 1400x1050@60Hz */
 403         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
 404                    1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
 405                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 406         /* 0x2b - 1400x1050@75Hz */
 407         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
 408                    1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
 409                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 410         /* 0x2c - 1400x1050@85Hz */
 411         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
 412                    1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
 413                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 414         /* 0x2d - 1400x1050@120Hz RB */
 415         { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
 416                    1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
 417                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 418         /* 0x2e - 1440x900@60Hz RB */
 419         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
 420                    1520, 1600, 0, 900, 903, 909, 926, 0,
 421                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 422         /* 0x2f - 1440x900@60Hz */
 423         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
 424                    1672, 1904, 0, 900, 903, 909, 934, 0,
 425                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 426         /* 0x30 - 1440x900@75Hz */
 427         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
 428                    1688, 1936, 0, 900, 903, 909, 942, 0,
 429                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 430         /* 0x31 - 1440x900@85Hz */
 431         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
 432                    1696, 1952, 0, 900, 903, 909, 948, 0,
 433                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 434         /* 0x32 - 1440x900@120Hz RB */
 435         { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
 436                    1520, 1600, 0, 900, 903, 909, 953, 0,
 437                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 438         /* 0x53 - 1600x900@60Hz */
 439         { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
 440                    1704, 1800, 0, 900, 901, 904, 1000, 0,
 441                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 442         /* 0x33 - 1600x1200@60Hz */
 443         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
 444                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 445                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 446         /* 0x34 - 1600x1200@65Hz */
 447         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
 448                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 449                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 450         /* 0x35 - 1600x1200@70Hz */
 451         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
 452                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 453                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 454         /* 0x36 - 1600x1200@75Hz */
 455         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
 456                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 457                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 458         /* 0x37 - 1600x1200@85Hz */
 459         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
 460                    1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 461                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 462         /* 0x38 - 1600x1200@120Hz RB */
 463         { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
 464                    1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
 465                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 466         /* 0x39 - 1680x1050@60Hz RB */
 467         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
 468                    1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
 469                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 470         /* 0x3a - 1680x1050@60Hz */
 471         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
 472                    1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
 473                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 474         /* 0x3b - 1680x1050@75Hz */
 475         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
 476                    1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
 477                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 478         /* 0x3c - 1680x1050@85Hz */
 479         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
 480                    1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
 481                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 482         /* 0x3d - 1680x1050@120Hz RB */
 483         { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
 484                    1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
 485                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 486         /* 0x3e - 1792x1344@60Hz */
 487         { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
 488                    2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
 489                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 490         /* 0x3f - 1792x1344@75Hz */
 491         { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
 492                    2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
 493                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 494         /* 0x40 - 1792x1344@120Hz RB */
 495         { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
 496                    1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
 497                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 498         /* 0x41 - 1856x1392@60Hz */
 499         { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
 500                    2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
 501                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 502         /* 0x42 - 1856x1392@75Hz */
 503         { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
 504                    2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
 505                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 506         /* 0x43 - 1856x1392@120Hz RB */
 507         { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
 508                    1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
 509                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 510         /* 0x52 - 1920x1080@60Hz */
 511         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 512                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 513                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 514         /* 0x44 - 1920x1200@60Hz RB */
 515         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
 516                    2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
 517                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 518         /* 0x45 - 1920x1200@60Hz */
 519         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
 520                    2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
 521                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 522         /* 0x46 - 1920x1200@75Hz */
 523         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
 524                    2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
 525                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 526         /* 0x47 - 1920x1200@85Hz */
 527         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
 528                    2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
 529                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 530         /* 0x48 - 1920x1200@120Hz RB */
 531         { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
 532                    2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
 533                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 534         /* 0x49 - 1920x1440@60Hz */
 535         { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
 536                    2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
 537                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 538         /* 0x4a - 1920x1440@75Hz */
 539         { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
 540                    2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
 541                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 542         /* 0x4b - 1920x1440@120Hz RB */
 543         { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
 544                    2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
 545                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 546         /* 0x54 - 2048x1152@60Hz */
 547         { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
 548                    2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
 549                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 550         /* 0x4c - 2560x1600@60Hz RB */
 551         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
 552                    2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
 553                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 554         /* 0x4d - 2560x1600@60Hz */
 555         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
 556                    3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
 557                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 558         /* 0x4e - 2560x1600@75Hz */
 559         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
 560                    3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
 561                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 562         /* 0x4f - 2560x1600@85Hz */
 563         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
 564                    3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
 565                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 566         /* 0x50 - 2560x1600@120Hz RB */
 567         { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
 568                    2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
 569                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 570         /* 0x57 - 4096x2160@60Hz RB */
 571         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
 572                    4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 573                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 574         /* 0x58 - 4096x2160@59.94Hz RB */
 575         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
 576                    4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 577                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 578 };
 579 
 580 /*
 581  * These more or less come from the DMT spec.  The 720x400 modes are
 582  * inferred from historical 80x25 practice.  The 640x480@67 and 832x624@75
 583  * modes are old-school Mac modes.  The EDID spec says the 1152x864@75 mode
 584  * should be 1152x870, again for the Mac, but instead we use the x864 DMT
 585  * mode.
 586  *
 587  * The DMT modes have been fact-checked; the rest are mild guesses.
 588  */
 589 static const struct drm_display_mode edid_est_modes[] = {
 590         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 591                    968, 1056, 0, 600, 601, 605, 628, 0,
 592                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
 593         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 594                    896, 1024, 0, 600, 601, 603,  625, 0,
 595                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
 596         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 597                    720, 840, 0, 480, 481, 484, 500, 0,
 598                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
 599         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 600                    704,  832, 0, 480, 489, 492, 520, 0,
 601                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
 602         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
 603                    768,  864, 0, 480, 483, 486, 525, 0,
 604                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
 605         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 606                    752, 800, 0, 480, 490, 492, 525, 0,
 607                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
 608         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
 609                    846, 900, 0, 400, 421, 423,  449, 0,
 610                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
 611         { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
 612                    846,  900, 0, 400, 412, 414, 449, 0,
 613                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
 614         { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 615                    1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 616                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
 617         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 618                    1136, 1312, 0,  768, 769, 772, 800, 0,
 619                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
 620         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 621                    1184, 1328, 0,  768, 771, 777, 806, 0,
 622                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
 623         { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 624                    1184, 1344, 0,  768, 771, 777, 806, 0,
 625                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
 626         { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
 627                    1208, 1264, 0, 768, 768, 776, 817, 0,
 628                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
 629         { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
 630                    928, 1152, 0, 624, 625, 628, 667, 0,
 631                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
 632         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 633                    896, 1056, 0, 600, 601, 604,  625, 0,
 634                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
 635         { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 636                    976, 1040, 0, 600, 637, 643, 666, 0,
 637                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
 638         { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 639                    1344, 1600, 0,  864, 865, 868, 900, 0,
 640                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
 641 };
 642 
 643 struct minimode {
 644         short w;
 645         short h;
 646         short r;
 647         short rb;
 648 };
 649 
 650 static const struct minimode est3_modes[] = {
 651         /* byte 6 */
 652         { 640, 350, 85, 0 },
 653         { 640, 400, 85, 0 },
 654         { 720, 400, 85, 0 },
 655         { 640, 480, 85, 0 },
 656         { 848, 480, 60, 0 },
 657         { 800, 600, 85, 0 },
 658         { 1024, 768, 85, 0 },
 659         { 1152, 864, 75, 0 },
 660         /* byte 7 */
 661         { 1280, 768, 60, 1 },
 662         { 1280, 768, 60, 0 },
 663         { 1280, 768, 75, 0 },
 664         { 1280, 768, 85, 0 },
 665         { 1280, 960, 60, 0 },
 666         { 1280, 960, 85, 0 },
 667         { 1280, 1024, 60, 0 },
 668         { 1280, 1024, 85, 0 },
 669         /* byte 8 */
 670         { 1360, 768, 60, 0 },
 671         { 1440, 900, 60, 1 },
 672         { 1440, 900, 60, 0 },
 673         { 1440, 900, 75, 0 },
 674         { 1440, 900, 85, 0 },
 675         { 1400, 1050, 60, 1 },
 676         { 1400, 1050, 60, 0 },
 677         { 1400, 1050, 75, 0 },
 678         /* byte 9 */
 679         { 1400, 1050, 85, 0 },
 680         { 1680, 1050, 60, 1 },
 681         { 1680, 1050, 60, 0 },
 682         { 1680, 1050, 75, 0 },
 683         { 1680, 1050, 85, 0 },
 684         { 1600, 1200, 60, 0 },
 685         { 1600, 1200, 65, 0 },
 686         { 1600, 1200, 70, 0 },
 687         /* byte 10 */
 688         { 1600, 1200, 75, 0 },
 689         { 1600, 1200, 85, 0 },
 690         { 1792, 1344, 60, 0 },
 691         { 1792, 1344, 75, 0 },
 692         { 1856, 1392, 60, 0 },
 693         { 1856, 1392, 75, 0 },
 694         { 1920, 1200, 60, 1 },
 695         { 1920, 1200, 60, 0 },
 696         /* byte 11 */
 697         { 1920, 1200, 75, 0 },
 698         { 1920, 1200, 85, 0 },
 699         { 1920, 1440, 60, 0 },
 700         { 1920, 1440, 75, 0 },
 701 };
 702 
 703 static const struct minimode extra_modes[] = {
 704         { 1024, 576,  60, 0 },
 705         { 1366, 768,  60, 0 },
 706         { 1600, 900,  60, 0 },
 707         { 1680, 945,  60, 0 },
 708         { 1920, 1080, 60, 0 },
 709         { 2048, 1152, 60, 0 },
 710         { 2048, 1536, 60, 0 },
 711 };
 712 
 713 /*
 714  * Probably taken from CEA-861 spec.
 715  * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
 716  *
 717  * Index using the VIC.
 718  */
 719 static const struct drm_display_mode edid_cea_modes[] = {
 720         /* 0 - dummy, VICs start at 1 */
 721         { },
 722         /* 1 - 640x480@60Hz 4:3 */
 723         { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 724                    752, 800, 0, 480, 490, 492, 525, 0,
 725                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 726           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 727         /* 2 - 720x480@60Hz 4:3 */
 728         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 729                    798, 858, 0, 480, 489, 495, 525, 0,
 730                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 731           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 732         /* 3 - 720x480@60Hz 16:9 */
 733         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 734                    798, 858, 0, 480, 489, 495, 525, 0,
 735                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 736           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 737         /* 4 - 1280x720@60Hz 16:9 */
 738         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 739                    1430, 1650, 0, 720, 725, 730, 750, 0,
 740                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 741           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 742         /* 5 - 1920x1080i@60Hz 16:9 */
 743         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 744                    2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 745                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 746                    DRM_MODE_FLAG_INTERLACE),
 747           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 748         /* 6 - 720(1440)x480i@60Hz 4:3 */
 749         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 750                    801, 858, 0, 480, 488, 494, 525, 0,
 751                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 752                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 753           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 754         /* 7 - 720(1440)x480i@60Hz 16:9 */
 755         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 756                    801, 858, 0, 480, 488, 494, 525, 0,
 757                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 758                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 759           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 760         /* 8 - 720(1440)x240@60Hz 4:3 */
 761         { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 762                    801, 858, 0, 240, 244, 247, 262, 0,
 763                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 764                    DRM_MODE_FLAG_DBLCLK),
 765           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 766         /* 9 - 720(1440)x240@60Hz 16:9 */
 767         { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 768                    801, 858, 0, 240, 244, 247, 262, 0,
 769                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 770                    DRM_MODE_FLAG_DBLCLK),
 771           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 772         /* 10 - 2880x480i@60Hz 4:3 */
 773         { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 774                    3204, 3432, 0, 480, 488, 494, 525, 0,
 775                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 776                    DRM_MODE_FLAG_INTERLACE),
 777           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 778         /* 11 - 2880x480i@60Hz 16:9 */
 779         { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 780                    3204, 3432, 0, 480, 488, 494, 525, 0,
 781                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 782                    DRM_MODE_FLAG_INTERLACE),
 783           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 784         /* 12 - 2880x240@60Hz 4:3 */
 785         { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 786                    3204, 3432, 0, 240, 244, 247, 262, 0,
 787                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 788           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 789         /* 13 - 2880x240@60Hz 16:9 */
 790         { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 791                    3204, 3432, 0, 240, 244, 247, 262, 0,
 792                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 793           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 794         /* 14 - 1440x480@60Hz 4:3 */
 795         { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 796                    1596, 1716, 0, 480, 489, 495, 525, 0,
 797                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 798           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 799         /* 15 - 1440x480@60Hz 16:9 */
 800         { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 801                    1596, 1716, 0, 480, 489, 495, 525, 0,
 802                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 803           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 804         /* 16 - 1920x1080@60Hz 16:9 */
 805         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 806                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 807                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 808           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 809         /* 17 - 720x576@50Hz 4:3 */
 810         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 811                    796, 864, 0, 576, 581, 586, 625, 0,
 812                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 813           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 814         /* 18 - 720x576@50Hz 16:9 */
 815         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 816                    796, 864, 0, 576, 581, 586, 625, 0,
 817                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 818           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 819         /* 19 - 1280x720@50Hz 16:9 */
 820         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
 821                    1760, 1980, 0, 720, 725, 730, 750, 0,
 822                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 823           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 824         /* 20 - 1920x1080i@50Hz 16:9 */
 825         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 826                    2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 827                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 828                    DRM_MODE_FLAG_INTERLACE),
 829           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 830         /* 21 - 720(1440)x576i@50Hz 4:3 */
 831         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 832                    795, 864, 0, 576, 580, 586, 625, 0,
 833                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 834                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 835           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 836         /* 22 - 720(1440)x576i@50Hz 16:9 */
 837         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 838                    795, 864, 0, 576, 580, 586, 625, 0,
 839                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 840                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 841           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 842         /* 23 - 720(1440)x288@50Hz 4:3 */
 843         { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 844                    795, 864, 0, 288, 290, 293, 312, 0,
 845                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 846                    DRM_MODE_FLAG_DBLCLK),
 847           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 848         /* 24 - 720(1440)x288@50Hz 16:9 */
 849         { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 850                    795, 864, 0, 288, 290, 293, 312, 0,
 851                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 852                    DRM_MODE_FLAG_DBLCLK),
 853           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 854         /* 25 - 2880x576i@50Hz 4:3 */
 855         { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 856                    3180, 3456, 0, 576, 580, 586, 625, 0,
 857                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 858                    DRM_MODE_FLAG_INTERLACE),
 859           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 860         /* 26 - 2880x576i@50Hz 16:9 */
 861         { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 862                    3180, 3456, 0, 576, 580, 586, 625, 0,
 863                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 864                    DRM_MODE_FLAG_INTERLACE),
 865           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 866         /* 27 - 2880x288@50Hz 4:3 */
 867         { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 868                    3180, 3456, 0, 288, 290, 293, 312, 0,
 869                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 870           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 871         /* 28 - 2880x288@50Hz 16:9 */
 872         { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 873                    3180, 3456, 0, 288, 290, 293, 312, 0,
 874                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 875           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 876         /* 29 - 1440x576@50Hz 4:3 */
 877         { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 878                    1592, 1728, 0, 576, 581, 586, 625, 0,
 879                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 880           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 881         /* 30 - 1440x576@50Hz 16:9 */
 882         { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 883                    1592, 1728, 0, 576, 581, 586, 625, 0,
 884                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 885           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 886         /* 31 - 1920x1080@50Hz 16:9 */
 887         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 888                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 889                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 890           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 891         /* 32 - 1920x1080@24Hz 16:9 */
 892         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
 893                    2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 894                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 895           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 896         /* 33 - 1920x1080@25Hz 16:9 */
 897         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 898                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 899                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 900           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 901         /* 34 - 1920x1080@30Hz 16:9 */
 902         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 903                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 904                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 905           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 906         /* 35 - 2880x480@60Hz 4:3 */
 907         { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 908                    3192, 3432, 0, 480, 489, 495, 525, 0,
 909                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 910           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 911         /* 36 - 2880x480@60Hz 16:9 */
 912         { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 913                    3192, 3432, 0, 480, 489, 495, 525, 0,
 914                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 915           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 916         /* 37 - 2880x576@50Hz 4:3 */
 917         { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 918                    3184, 3456, 0, 576, 581, 586, 625, 0,
 919                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 920           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 921         /* 38 - 2880x576@50Hz 16:9 */
 922         { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 923                    3184, 3456, 0, 576, 581, 586, 625, 0,
 924                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 925           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 926         /* 39 - 1920x1080i@50Hz 16:9 */
 927         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
 928                    2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
 929                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
 930                    DRM_MODE_FLAG_INTERLACE),
 931           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 932         /* 40 - 1920x1080i@100Hz 16:9 */
 933         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 934                    2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 935                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 936                    DRM_MODE_FLAG_INTERLACE),
 937           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 938         /* 41 - 1280x720@100Hz 16:9 */
 939         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
 940                    1760, 1980, 0, 720, 725, 730, 750, 0,
 941                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 942           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 943         /* 42 - 720x576@100Hz 4:3 */
 944         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 945                    796, 864, 0, 576, 581, 586, 625, 0,
 946                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 947           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 948         /* 43 - 720x576@100Hz 16:9 */
 949         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 950                    796, 864, 0, 576, 581, 586, 625, 0,
 951                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 952           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 953         /* 44 - 720(1440)x576i@100Hz 4:3 */
 954         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 955                    795, 864, 0, 576, 580, 586, 625, 0,
 956                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 957                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 958           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 959         /* 45 - 720(1440)x576i@100Hz 16:9 */
 960         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 961                    795, 864, 0, 576, 580, 586, 625, 0,
 962                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 963                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 964           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 965         /* 46 - 1920x1080i@120Hz 16:9 */
 966         { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 967                    2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 968                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 969                    DRM_MODE_FLAG_INTERLACE),
 970           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 971         /* 47 - 1280x720@120Hz 16:9 */
 972         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
 973                    1430, 1650, 0, 720, 725, 730, 750, 0,
 974                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 975           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 976         /* 48 - 720x480@120Hz 4:3 */
 977         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 978                    798, 858, 0, 480, 489, 495, 525, 0,
 979                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 980           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 981         /* 49 - 720x480@120Hz 16:9 */
 982         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 983                    798, 858, 0, 480, 489, 495, 525, 0,
 984                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 985           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 986         /* 50 - 720(1440)x480i@120Hz 4:3 */
 987         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 988                    801, 858, 0, 480, 488, 494, 525, 0,
 989                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 990                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 991           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 992         /* 51 - 720(1440)x480i@120Hz 16:9 */
 993         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 994                    801, 858, 0, 480, 488, 494, 525, 0,
 995                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 996                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 997           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 998         /* 52 - 720x576@200Hz 4:3 */
 999         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1000                    796, 864, 0, 576, 581, 586, 625, 0,
1001                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1002           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1003         /* 53 - 720x576@200Hz 16:9 */
1004         { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1005                    796, 864, 0, 576, 581, 586, 625, 0,
1006                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1007           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1008         /* 54 - 720(1440)x576i@200Hz 4:3 */
1009         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1010                    795, 864, 0, 576, 580, 586, 625, 0,
1011                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1012                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1013           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1014         /* 55 - 720(1440)x576i@200Hz 16:9 */
1015         { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1016                    795, 864, 0, 576, 580, 586, 625, 0,
1017                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1018                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1019           .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1020         /* 56 - 720x480@240Hz 4:3 */
1021         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1022                    798, 858, 0, 480, 489, 495, 525, 0,
1023                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1024           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1025         /* 57 - 720x480@240Hz 16:9 */
1026         { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1027                    798, 858, 0, 480, 489, 495, 525, 0,
1028                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1029           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1030         /* 58 - 720(1440)x480i@240Hz 4:3 */
1031         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1032                    801, 858, 0, 480, 488, 494, 525, 0,
1033                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1034                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1035           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1036         /* 59 - 720(1440)x480i@240Hz 16:9 */
1037         { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1038                    801, 858, 0, 480, 488, 494, 525, 0,
1039                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1040                    DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1041           .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1042         /* 60 - 1280x720@24Hz 16:9 */
1043         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1044                    3080, 3300, 0, 720, 725, 730, 750, 0,
1045                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1046           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047         /* 61 - 1280x720@25Hz 16:9 */
1048         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1049                    3740, 3960, 0, 720, 725, 730, 750, 0,
1050                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1052         /* 62 - 1280x720@30Hz 16:9 */
1053         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1054                    3080, 3300, 0, 720, 725, 730, 750, 0,
1055                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1057         /* 63 - 1920x1080@120Hz 16:9 */
1058         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1059                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1060                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1062         /* 64 - 1920x1080@100Hz 16:9 */
1063         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1064                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1065                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1067         /* 65 - 1280x720@24Hz 64:27 */
1068         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1069                    3080, 3300, 0, 720, 725, 730, 750, 0,
1070                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1072         /* 66 - 1280x720@25Hz 64:27 */
1073         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1074                    3740, 3960, 0, 720, 725, 730, 750, 0,
1075                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077         /* 67 - 1280x720@30Hz 64:27 */
1078         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1079                    3080, 3300, 0, 720, 725, 730, 750, 0,
1080                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082         /* 68 - 1280x720@50Hz 64:27 */
1083         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1084                    1760, 1980, 0, 720, 725, 730, 750, 0,
1085                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087         /* 69 - 1280x720@60Hz 64:27 */
1088         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1089                    1430, 1650, 0, 720, 725, 730, 750, 0,
1090                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092         /* 70 - 1280x720@100Hz 64:27 */
1093         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1094                    1760, 1980, 0, 720, 725, 730, 750, 0,
1095                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097         /* 71 - 1280x720@120Hz 64:27 */
1098         { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1099                    1430, 1650, 0, 720, 725, 730, 750, 0,
1100                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102         /* 72 - 1920x1080@24Hz 64:27 */
1103         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1104                    2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1105                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107         /* 73 - 1920x1080@25Hz 64:27 */
1108         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1109                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1110                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112         /* 74 - 1920x1080@30Hz 64:27 */
1113         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1114                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1115                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117         /* 75 - 1920x1080@50Hz 64:27 */
1118         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1119                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1120                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122         /* 76 - 1920x1080@60Hz 64:27 */
1123         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1124                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1125                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127         /* 77 - 1920x1080@100Hz 64:27 */
1128         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1129                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1130                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132         /* 78 - 1920x1080@120Hz 64:27 */
1133         { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1134                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1135                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137         /* 79 - 1680x720@24Hz 64:27 */
1138         { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1139                    3080, 3300, 0, 720, 725, 730, 750, 0,
1140                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142         /* 80 - 1680x720@25Hz 64:27 */
1143         { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1144                    2948, 3168, 0, 720, 725, 730, 750, 0,
1145                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147         /* 81 - 1680x720@30Hz 64:27 */
1148         { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1149                    2420, 2640, 0, 720, 725, 730, 750, 0,
1150                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152         /* 82 - 1680x720@50Hz 64:27 */
1153         { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1154                    1980, 2200, 0, 720, 725, 730, 750, 0,
1155                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157         /* 83 - 1680x720@60Hz 64:27 */
1158         { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1159                    1980, 2200, 0, 720, 725, 730, 750, 0,
1160                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162         /* 84 - 1680x720@100Hz 64:27 */
1163         { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1164                    1780, 2000, 0, 720, 725, 730, 825, 0,
1165                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167         /* 85 - 1680x720@120Hz 64:27 */
1168         { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1169                    1780, 2000, 0, 720, 725, 730, 825, 0,
1170                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172         /* 86 - 2560x1080@24Hz 64:27 */
1173         { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1174                    3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1175                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177         /* 87 - 2560x1080@25Hz 64:27 */
1178         { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1179                    3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1180                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182         /* 88 - 2560x1080@30Hz 64:27 */
1183         { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1184                    3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1185                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1187         /* 89 - 2560x1080@50Hz 64:27 */
1188         { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1189                    3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1190                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1192         /* 90 - 2560x1080@60Hz 64:27 */
1193         { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1194                    2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1195                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1197         /* 91 - 2560x1080@100Hz 64:27 */
1198         { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1199                    2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1200                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201           .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1202         /* 92 - 2560x1080@120Hz 64:27 */
1203         { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1204                    3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1205                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206           .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1207         /* 93 - 3840x2160@24Hz 16:9 */
1208         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1209                    5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1210                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1212         /* 94 - 3840x2160@25Hz 16:9 */
1213         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1214                    4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1215                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1217         /* 95 - 3840x2160@30Hz 16:9 */
1218         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1219                    4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1220                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1222         /* 96 - 3840x2160@50Hz 16:9 */
1223         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1224                    4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1227         /* 97 - 3840x2160@60Hz 16:9 */
1228         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1229                    4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1232         /* 98 - 4096x2160@24Hz 256:135 */
1233         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1234                    5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1235                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1237         /* 99 - 4096x2160@25Hz 256:135 */
1238         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1239                    5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1240                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1242         /* 100 - 4096x2160@30Hz 256:135 */
1243         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1244                    4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1245                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1247         /* 101 - 4096x2160@50Hz 256:135 */
1248         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1249                    5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1252         /* 102 - 4096x2160@60Hz 256:135 */
1253         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1254                    4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1257         /* 103 - 3840x2160@24Hz 64:27 */
1258         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1259                    5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1260                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1261           .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1262         /* 104 - 3840x2160@25Hz 64:27 */
1263         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1264                    4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1265                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266           .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1267         /* 105 - 3840x2160@30Hz 64:27 */
1268         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1269                    4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1270                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1271           .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1272         /* 106 - 3840x2160@50Hz 64:27 */
1273         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1274                    4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1275                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276           .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1277         /* 107 - 3840x2160@60Hz 64:27 */
1278         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1279                    4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1280                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281           .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1282 };
1283 
1284 /*
1285  * HDMI 1.4 4k modes. Index using the VIC.
1286  */
1287 static const struct drm_display_mode edid_4k_modes[] = {
1288         /* 0 - dummy, VICs start at 1 */
1289         { },
1290         /* 1 - 3840x2160@30Hz */
1291         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1292                    3840, 4016, 4104, 4400, 0,
1293                    2160, 2168, 2178, 2250, 0,
1294                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295           .vrefresh = 30, },
1296         /* 2 - 3840x2160@25Hz */
1297         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1298                    3840, 4896, 4984, 5280, 0,
1299                    2160, 2168, 2178, 2250, 0,
1300                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301           .vrefresh = 25, },
1302         /* 3 - 3840x2160@24Hz */
1303         { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1304                    3840, 5116, 5204, 5500, 0,
1305                    2160, 2168, 2178, 2250, 0,
1306                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307           .vrefresh = 24, },
1308         /* 4 - 4096x2160@24Hz (SMPTE) */
1309         { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1310                    4096, 5116, 5204, 5500, 0,
1311                    2160, 2168, 2178, 2250, 0,
1312                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313           .vrefresh = 24, },
1314 };
1315 
1316 /*** DDC fetch and block validation ***/
1317 
1318 static const u8 edid_header[] = {
1319         0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1320 };
1321 
1322 /**
1323  * drm_edid_header_is_valid - sanity check the header of the base EDID block
1324  * @raw_edid: pointer to raw base EDID block
1325  *
1326  * Sanity check the header of the base EDID block.
1327  *
1328  * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1329  */
1330 int drm_edid_header_is_valid(const u8 *raw_edid)
1331 {
1332         int i, score = 0;
1333 
1334         for (i = 0; i < sizeof(edid_header); i++)
1335                 if (raw_edid[i] == edid_header[i])
1336                         score++;
1337 
1338         return score;
1339 }
1340 EXPORT_SYMBOL(drm_edid_header_is_valid);
1341 
1342 static int edid_fixup __read_mostly = 6;
1343 module_param_named(edid_fixup, edid_fixup, int, 0400);
1344 MODULE_PARM_DESC(edid_fixup,
1345                  "Minimum number of valid EDID header bytes (0-8, default 6)");
1346 
1347 static void drm_get_displayid(struct drm_connector *connector,
1348                               struct edid *edid);
1349 static int validate_displayid(u8 *displayid, int length, int idx);
1350 
1351 static int drm_edid_block_checksum(const u8 *raw_edid)
1352 {
1353         int i;
1354         u8 csum = 0;
1355         for (i = 0; i < EDID_LENGTH; i++)
1356                 csum += raw_edid[i];
1357 
1358         return csum;
1359 }
1360 
1361 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1362 {
1363         if (memchr_inv(in_edid, 0, length))
1364                 return false;
1365 
1366         return true;
1367 }
1368 
1369 /**
1370  * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1371  * @raw_edid: pointer to raw EDID block
1372  * @block: type of block to validate (0 for base, extension otherwise)
1373  * @print_bad_edid: if true, dump bad EDID blocks to the console
1374  * @edid_corrupt: if true, the header or checksum is invalid
1375  *
1376  * Validate a base or extension EDID block and optionally dump bad blocks to
1377  * the console.
1378  *
1379  * Return: True if the block is valid, false otherwise.
1380  */
1381 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1382                           bool *edid_corrupt)
1383 {
1384         u8 csum;
1385         struct edid *edid = (struct edid *)raw_edid;
1386 
1387         if (WARN_ON(!raw_edid))
1388                 return false;
1389 
1390         if (edid_fixup > 8 || edid_fixup < 0)
1391                 edid_fixup = 6;
1392 
1393         if (block == 0) {
1394                 int score = drm_edid_header_is_valid(raw_edid);
1395                 if (score == 8) {
1396                         if (edid_corrupt)
1397                                 *edid_corrupt = false;
1398                 } else if (score >= edid_fixup) {
1399                         /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1400                          * The corrupt flag needs to be set here otherwise, the
1401                          * fix-up code here will correct the problem, the
1402                          * checksum is correct and the test fails
1403                          */
1404                         if (edid_corrupt)
1405                                 *edid_corrupt = true;
1406                         DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1407                         memcpy(raw_edid, edid_header, sizeof(edid_header));
1408                 } else {
1409                         if (edid_corrupt)
1410                                 *edid_corrupt = true;
1411                         goto bad;
1412                 }
1413         }
1414 
1415         csum = drm_edid_block_checksum(raw_edid);
1416         if (csum) {
1417                 if (edid_corrupt)
1418                         *edid_corrupt = true;
1419 
1420                 /* allow CEA to slide through, switches mangle this */
1421                 if (raw_edid[0] == CEA_EXT) {
1422                         DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1423                         DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1424                 } else {
1425                         if (print_bad_edid)
1426                                 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1427 
1428                         goto bad;
1429                 }
1430         }
1431 
1432         /* per-block-type checks */
1433         switch (raw_edid[0]) {
1434         case 0: /* base */
1435                 if (edid->version != 1) {
1436                         DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1437                         goto bad;
1438                 }
1439 
1440                 if (edid->revision > 4)
1441                         DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1442                 break;
1443 
1444         default:
1445                 break;
1446         }
1447 
1448         return true;
1449 
1450 bad:
1451         if (print_bad_edid) {
1452                 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1453                         pr_notice("EDID block is all zeroes\n");
1454                 } else {
1455                         pr_notice("Raw EDID:\n");
1456                         print_hex_dump(KERN_NOTICE,
1457                                        " \t", DUMP_PREFIX_NONE, 16, 1,
1458                                        raw_edid, EDID_LENGTH, false);
1459                 }
1460         }
1461         return false;
1462 }
1463 EXPORT_SYMBOL(drm_edid_block_valid);
1464 
1465 /**
1466  * drm_edid_is_valid - sanity check EDID data
1467  * @edid: EDID data
1468  *
1469  * Sanity-check an entire EDID record (including extensions)
1470  *
1471  * Return: True if the EDID data is valid, false otherwise.
1472  */
1473 bool drm_edid_is_valid(struct edid *edid)
1474 {
1475         int i;
1476         u8 *raw = (u8 *)edid;
1477 
1478         if (!edid)
1479                 return false;
1480 
1481         for (i = 0; i <= edid->extensions; i++)
1482                 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1483                         return false;
1484 
1485         return true;
1486 }
1487 EXPORT_SYMBOL(drm_edid_is_valid);
1488 
1489 #define DDC_SEGMENT_ADDR 0x30
1490 /**
1491  * drm_do_probe_ddc_edid() - get EDID information via I2C
1492  * @data: I2C device adapter
1493  * @buf: EDID data buffer to be filled
1494  * @block: 128 byte EDID block to start fetching from
1495  * @len: EDID data buffer length to fetch
1496  *
1497  * Try to fetch EDID information by calling I2C driver functions.
1498  *
1499  * Return: 0 on success or -1 on failure.
1500  */
1501 static int
1502 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1503 {
1504         struct i2c_adapter *adapter = data;
1505         unsigned char start = block * EDID_LENGTH;
1506         unsigned char segment = block >> 1;
1507         unsigned char xfers = segment ? 3 : 2;
1508         int ret, retries = 5;
1509 
1510         /*
1511          * The core I2C driver will automatically retry the transfer if the
1512          * adapter reports EAGAIN. However, we find that bit-banging transfers
1513          * are susceptible to errors under a heavily loaded machine and
1514          * generate spurious NAKs and timeouts. Retrying the transfer
1515          * of the individual block a few times seems to overcome this.
1516          */
1517         do {
1518                 struct i2c_msg msgs[] = {
1519                         {
1520                                 .addr   = DDC_SEGMENT_ADDR,
1521                                 .flags  = 0,
1522                                 .len    = 1,
1523                                 .buf    = &segment,
1524                         }, {
1525                                 .addr   = DDC_ADDR,
1526                                 .flags  = 0,
1527                                 .len    = 1,
1528                                 .buf    = &start,
1529                         }, {
1530                                 .addr   = DDC_ADDR,
1531                                 .flags  = I2C_M_RD,
1532                                 .len    = len,
1533                                 .buf    = buf,
1534                         }
1535                 };
1536 
1537                 /*
1538                  * Avoid sending the segment addr to not upset non-compliant
1539                  * DDC monitors.
1540                  */
1541                 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1542 
1543                 if (ret == -ENXIO) {
1544                         DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1545                                         adapter->name);
1546                         break;
1547                 }
1548         } while (ret != xfers && --retries);
1549 
1550         return ret == xfers ? 0 : -1;
1551 }
1552 
1553 static void connector_bad_edid(struct drm_connector *connector,
1554                                u8 *edid, int num_blocks)
1555 {
1556         int i;
1557 
1558         if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1559                 return;
1560 
1561         dev_warn(connector->dev->dev,
1562                  "%s: EDID is invalid:\n",
1563                  connector->name);
1564         for (i = 0; i < num_blocks; i++) {
1565                 u8 *block = edid + i * EDID_LENGTH;
1566                 char prefix[20];
1567 
1568                 if (drm_edid_is_zero(block, EDID_LENGTH))
1569                         sprintf(prefix, "\t[%02x] ZERO ", i);
1570                 else if (!drm_edid_block_valid(block, i, false, NULL))
1571                         sprintf(prefix, "\t[%02x] BAD  ", i);
1572                 else
1573                         sprintf(prefix, "\t[%02x] GOOD ", i);
1574 
1575                 print_hex_dump(KERN_WARNING,
1576                                prefix, DUMP_PREFIX_NONE, 16, 1,
1577                                block, EDID_LENGTH, false);
1578         }
1579 }
1580 
1581 /* Get override or firmware EDID */
1582 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1583 {
1584         struct edid *override = NULL;
1585 
1586         if (connector->override_edid)
1587                 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1588 
1589         if (!override)
1590                 override = drm_load_edid_firmware(connector);
1591 
1592         return IS_ERR(override) ? NULL : override;
1593 }
1594 
1595 /**
1596  * drm_add_override_edid_modes - add modes from override/firmware EDID
1597  * @connector: connector we're probing
1598  *
1599  * Add modes from the override/firmware EDID, if available. Only to be used from
1600  * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1601  * failed during drm_get_edid() and caused the override/firmware EDID to be
1602  * skipped.
1603  *
1604  * Return: The number of modes added or 0 if we couldn't find any.
1605  */
1606 int drm_add_override_edid_modes(struct drm_connector *connector)
1607 {
1608         struct edid *override;
1609         int num_modes = 0;
1610 
1611         override = drm_get_override_edid(connector);
1612         if (override) {
1613                 drm_connector_update_edid_property(connector, override);
1614                 num_modes = drm_add_edid_modes(connector, override);
1615                 kfree(override);
1616 
1617                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1618                               connector->base.id, connector->name, num_modes);
1619         }
1620 
1621         return num_modes;
1622 }
1623 EXPORT_SYMBOL(drm_add_override_edid_modes);
1624 
1625 /**
1626  * drm_do_get_edid - get EDID data using a custom EDID block read function
1627  * @connector: connector we're probing
1628  * @get_edid_block: EDID block read function
1629  * @data: private data passed to the block read function
1630  *
1631  * When the I2C adapter connected to the DDC bus is hidden behind a device that
1632  * exposes a different interface to read EDID blocks this function can be used
1633  * to get EDID data using a custom block read function.
1634  *
1635  * As in the general case the DDC bus is accessible by the kernel at the I2C
1636  * level, drivers must make all reasonable efforts to expose it as an I2C
1637  * adapter and use drm_get_edid() instead of abusing this function.
1638  *
1639  * The EDID may be overridden using debugfs override_edid or firmare EDID
1640  * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1641  * order. Having either of them bypasses actual EDID reads.
1642  *
1643  * Return: Pointer to valid EDID or NULL if we couldn't find any.
1644  */
1645 struct edid *drm_do_get_edid(struct drm_connector *connector,
1646         int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1647                               size_t len),
1648         void *data)
1649 {
1650         int i, j = 0, valid_extensions = 0;
1651         u8 *edid, *new;
1652         struct edid *override;
1653 
1654         override = drm_get_override_edid(connector);
1655         if (override)
1656                 return override;
1657 
1658         if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1659                 return NULL;
1660 
1661         /* base block fetch */
1662         for (i = 0; i < 4; i++) {
1663                 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1664                         goto out;
1665                 if (drm_edid_block_valid(edid, 0, false,
1666                                          &connector->edid_corrupt))
1667                         break;
1668                 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1669                         connector->null_edid_counter++;
1670                         goto carp;
1671                 }
1672         }
1673         if (i == 4)
1674                 goto carp;
1675 
1676         /* if there's no extensions, we're done */
1677         valid_extensions = edid[0x7e];
1678         if (valid_extensions == 0)
1679                 return (struct edid *)edid;
1680 
1681         new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1682         if (!new)
1683                 goto out;
1684         edid = new;
1685 
1686         for (j = 1; j <= edid[0x7e]; j++) {
1687                 u8 *block = edid + j * EDID_LENGTH;
1688 
1689                 for (i = 0; i < 4; i++) {
1690                         if (get_edid_block(data, block, j, EDID_LENGTH))
1691                                 goto out;
1692                         if (drm_edid_block_valid(block, j, false, NULL))
1693                                 break;
1694                 }
1695 
1696                 if (i == 4)
1697                         valid_extensions--;
1698         }
1699 
1700         if (valid_extensions != edid[0x7e]) {
1701                 u8 *base;
1702 
1703                 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1704 
1705                 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1706                 edid[0x7e] = valid_extensions;
1707 
1708                 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1709                                     GFP_KERNEL);
1710                 if (!new)
1711                         goto out;
1712 
1713                 base = new;
1714                 for (i = 0; i <= edid[0x7e]; i++) {
1715                         u8 *block = edid + i * EDID_LENGTH;
1716 
1717                         if (!drm_edid_block_valid(block, i, false, NULL))
1718                                 continue;
1719 
1720                         memcpy(base, block, EDID_LENGTH);
1721                         base += EDID_LENGTH;
1722                 }
1723 
1724                 kfree(edid);
1725                 edid = new;
1726         }
1727 
1728         return (struct edid *)edid;
1729 
1730 carp:
1731         connector_bad_edid(connector, edid, 1);
1732 out:
1733         kfree(edid);
1734         return NULL;
1735 }
1736 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1737 
1738 /**
1739  * drm_probe_ddc() - probe DDC presence
1740  * @adapter: I2C adapter to probe
1741  *
1742  * Return: True on success, false on failure.
1743  */
1744 bool
1745 drm_probe_ddc(struct i2c_adapter *adapter)
1746 {
1747         unsigned char out;
1748 
1749         return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1750 }
1751 EXPORT_SYMBOL(drm_probe_ddc);
1752 
1753 /**
1754  * drm_get_edid - get EDID data, if available
1755  * @connector: connector we're probing
1756  * @adapter: I2C adapter to use for DDC
1757  *
1758  * Poke the given I2C channel to grab EDID data if possible.  If found,
1759  * attach it to the connector.
1760  *
1761  * Return: Pointer to valid EDID or NULL if we couldn't find any.
1762  */
1763 struct edid *drm_get_edid(struct drm_connector *connector,
1764                           struct i2c_adapter *adapter)
1765 {
1766         struct edid *edid;
1767 
1768         if (connector->force == DRM_FORCE_OFF)
1769                 return NULL;
1770 
1771         if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1772                 return NULL;
1773 
1774         edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1775         if (edid)
1776                 drm_get_displayid(connector, edid);
1777         return edid;
1778 }
1779 EXPORT_SYMBOL(drm_get_edid);
1780 
1781 /**
1782  * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1783  * @connector: connector we're probing
1784  * @adapter: I2C adapter to use for DDC
1785  *
1786  * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1787  * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1788  * switch DDC to the GPU which is retrieving EDID.
1789  *
1790  * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1791  */
1792 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1793                                      struct i2c_adapter *adapter)
1794 {
1795         struct pci_dev *pdev = connector->dev->pdev;
1796         struct edid *edid;
1797 
1798         vga_switcheroo_lock_ddc(pdev);
1799         edid = drm_get_edid(connector, adapter);
1800         vga_switcheroo_unlock_ddc(pdev);
1801 
1802         return edid;
1803 }
1804 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1805 
1806 /**
1807  * drm_edid_duplicate - duplicate an EDID and the extensions
1808  * @edid: EDID to duplicate
1809  *
1810  * Return: Pointer to duplicated EDID or NULL on allocation failure.
1811  */
1812 struct edid *drm_edid_duplicate(const struct edid *edid)
1813 {
1814         return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1815 }
1816 EXPORT_SYMBOL(drm_edid_duplicate);
1817 
1818 /*** EDID parsing ***/
1819 
1820 /**
1821  * edid_vendor - match a string against EDID's obfuscated vendor field
1822  * @edid: EDID to match
1823  * @vendor: vendor string
1824  *
1825  * Returns true if @vendor is in @edid, false otherwise
1826  */
1827 static bool edid_vendor(const struct edid *edid, const char *vendor)
1828 {
1829         char edid_vendor[3];
1830 
1831         edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1832         edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1833                           ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1834         edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1835 
1836         return !strncmp(edid_vendor, vendor, 3);
1837 }
1838 
1839 /**
1840  * edid_get_quirks - return quirk flags for a given EDID
1841  * @edid: EDID to process
1842  *
1843  * This tells subsequent routines what fixes they need to apply.
1844  */
1845 static u32 edid_get_quirks(const struct edid *edid)
1846 {
1847         const struct edid_quirk *quirk;
1848         int i;
1849 
1850         for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1851                 quirk = &edid_quirk_list[i];
1852 
1853                 if (edid_vendor(edid, quirk->vendor) &&
1854                     (EDID_PRODUCT_ID(edid) == quirk->product_id))
1855                         return quirk->quirks;
1856         }
1857 
1858         return 0;
1859 }
1860 
1861 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1862 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1863 
1864 /**
1865  * edid_fixup_preferred - set preferred modes based on quirk list
1866  * @connector: has mode list to fix up
1867  * @quirks: quirks list
1868  *
1869  * Walk the mode list for @connector, clearing the preferred status
1870  * on existing modes and setting it anew for the right mode ala @quirks.
1871  */
1872 static void edid_fixup_preferred(struct drm_connector *connector,
1873                                  u32 quirks)
1874 {
1875         struct drm_display_mode *t, *cur_mode, *preferred_mode;
1876         int target_refresh = 0;
1877         int cur_vrefresh, preferred_vrefresh;
1878 
1879         if (list_empty(&connector->probed_modes))
1880                 return;
1881 
1882         if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1883                 target_refresh = 60;
1884         if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1885                 target_refresh = 75;
1886 
1887         preferred_mode = list_first_entry(&connector->probed_modes,
1888                                           struct drm_display_mode, head);
1889 
1890         list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1891                 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1892 
1893                 if (cur_mode == preferred_mode)
1894                         continue;
1895 
1896                 /* Largest mode is preferred */
1897                 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1898                         preferred_mode = cur_mode;
1899 
1900                 cur_vrefresh = cur_mode->vrefresh ?
1901                         cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1902                 preferred_vrefresh = preferred_mode->vrefresh ?
1903                         preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1904                 /* At a given size, try to get closest to target refresh */
1905                 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1906                     MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1907                     MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1908                         preferred_mode = cur_mode;
1909                 }
1910         }
1911 
1912         preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1913 }
1914 
1915 static bool
1916 mode_is_rb(const struct drm_display_mode *mode)
1917 {
1918         return (mode->htotal - mode->hdisplay == 160) &&
1919                (mode->hsync_end - mode->hdisplay == 80) &&
1920                (mode->hsync_end - mode->hsync_start == 32) &&
1921                (mode->vsync_start - mode->vdisplay == 3);
1922 }
1923 
1924 /*
1925  * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1926  * @dev: Device to duplicate against
1927  * @hsize: Mode width
1928  * @vsize: Mode height
1929  * @fresh: Mode refresh rate
1930  * @rb: Mode reduced-blanking-ness
1931  *
1932  * Walk the DMT mode list looking for a match for the given parameters.
1933  *
1934  * Return: A newly allocated copy of the mode, or NULL if not found.
1935  */
1936 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1937                                            int hsize, int vsize, int fresh,
1938                                            bool rb)
1939 {
1940         int i;
1941 
1942         for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1943                 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1944                 if (hsize != ptr->hdisplay)
1945                         continue;
1946                 if (vsize != ptr->vdisplay)
1947                         continue;
1948                 if (fresh != drm_mode_vrefresh(ptr))
1949                         continue;
1950                 if (rb != mode_is_rb(ptr))
1951                         continue;
1952 
1953                 return drm_mode_duplicate(dev, ptr);
1954         }
1955 
1956         return NULL;
1957 }
1958 EXPORT_SYMBOL(drm_mode_find_dmt);
1959 
1960 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1961 
1962 static void
1963 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1964 {
1965         int i, n = 0;
1966         u8 d = ext[0x02];
1967         u8 *det_base = ext + d;
1968 
1969         n = (127 - d) / 18;
1970         for (i = 0; i < n; i++)
1971                 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1972 }
1973 
1974 static void
1975 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1976 {
1977         unsigned int i, n = min((int)ext[0x02], 6);
1978         u8 *det_base = ext + 5;
1979 
1980         if (ext[0x01] != 1)
1981                 return; /* unknown version */
1982 
1983         for (i = 0; i < n; i++)
1984                 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1985 }
1986 
1987 static void
1988 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1989 {
1990         int i;
1991         struct edid *edid = (struct edid *)raw_edid;
1992 
1993         if (edid == NULL)
1994                 return;
1995 
1996         for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1997                 cb(&(edid->detailed_timings[i]), closure);
1998 
1999         for (i = 1; i <= raw_edid[0x7e]; i++) {
2000                 u8 *ext = raw_edid + (i * EDID_LENGTH);
2001                 switch (*ext) {
2002                 case CEA_EXT:
2003                         cea_for_each_detailed_block(ext, cb, closure);
2004                         break;
2005                 case VTB_EXT:
2006                         vtb_for_each_detailed_block(ext, cb, closure);
2007                         break;
2008                 default:
2009                         break;
2010                 }
2011         }
2012 }
2013 
2014 static void
2015 is_rb(struct detailed_timing *t, void *data)
2016 {
2017         u8 *r = (u8 *)t;
2018         if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2019                 if (r[15] & 0x10)
2020                         *(bool *)data = true;
2021 }
2022 
2023 /* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
2024 static bool
2025 drm_monitor_supports_rb(struct edid *edid)
2026 {
2027         if (edid->revision >= 4) {
2028                 bool ret = false;
2029                 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2030                 return ret;
2031         }
2032 
2033         return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2034 }
2035 
2036 static void
2037 find_gtf2(struct detailed_timing *t, void *data)
2038 {
2039         u8 *r = (u8 *)t;
2040         if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2041                 *(u8 **)data = r;
2042 }
2043 
2044 /* Secondary GTF curve kicks in above some break frequency */
2045 static int
2046 drm_gtf2_hbreak(struct edid *edid)
2047 {
2048         u8 *r = NULL;
2049         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2050         return r ? (r[12] * 2) : 0;
2051 }
2052 
2053 static int
2054 drm_gtf2_2c(struct edid *edid)
2055 {
2056         u8 *r = NULL;
2057         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2058         return r ? r[13] : 0;
2059 }
2060 
2061 static int
2062 drm_gtf2_m(struct edid *edid)
2063 {
2064         u8 *r = NULL;
2065         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2066         return r ? (r[15] << 8) + r[14] : 0;
2067 }
2068 
2069 static int
2070 drm_gtf2_k(struct edid *edid)
2071 {
2072         u8 *r = NULL;
2073         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2074         return r ? r[16] : 0;
2075 }
2076 
2077 static int
2078 drm_gtf2_2j(struct edid *edid)
2079 {
2080         u8 *r = NULL;
2081         drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2082         return r ? r[17] : 0;
2083 }
2084 
2085 /**
2086  * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2087  * @edid: EDID block to scan
2088  */
2089 static int standard_timing_level(struct edid *edid)
2090 {
2091         if (edid->revision >= 2) {
2092                 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2093                         return LEVEL_CVT;
2094                 if (drm_gtf2_hbreak(edid))
2095                         return LEVEL_GTF2;
2096                 return LEVEL_GTF;
2097         }
2098         return LEVEL_DMT;
2099 }
2100 
2101 /*
2102  * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
2103  * monitors fill with ascii space (0x20) instead.
2104  */
2105 static int
2106 bad_std_timing(u8 a, u8 b)
2107 {
2108         return (a == 0x00 && b == 0x00) ||
2109                (a == 0x01 && b == 0x01) ||
2110                (a == 0x20 && b == 0x20);
2111 }
2112 
2113 /**
2114  * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2115  * @connector: connector of for the EDID block
2116  * @edid: EDID block to scan
2117  * @t: standard timing params
2118  *
2119  * Take the standard timing params (in this case width, aspect, and refresh)
2120  * and convert them into a real mode using CVT/GTF/DMT.
2121  */
2122 static struct drm_display_mode *
2123 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2124              struct std_timing *t)
2125 {
2126         struct drm_device *dev = connector->dev;
2127         struct drm_display_mode *m, *mode = NULL;
2128         int hsize, vsize;
2129         int vrefresh_rate;
2130         unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2131                 >> EDID_TIMING_ASPECT_SHIFT;
2132         unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2133                 >> EDID_TIMING_VFREQ_SHIFT;
2134         int timing_level = standard_timing_level(edid);
2135 
2136         if (bad_std_timing(t->hsize, t->vfreq_aspect))
2137                 return NULL;
2138 
2139         /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2140         hsize = t->hsize * 8 + 248;
2141         /* vrefresh_rate = vfreq + 60 */
2142         vrefresh_rate = vfreq + 60;
2143         /* the vdisplay is calculated based on the aspect ratio */
2144         if (aspect_ratio == 0) {
2145                 if (edid->revision < 3)
2146                         vsize = hsize;
2147                 else
2148                         vsize = (hsize * 10) / 16;
2149         } else if (aspect_ratio == 1)
2150                 vsize = (hsize * 3) / 4;
2151         else if (aspect_ratio == 2)
2152                 vsize = (hsize * 4) / 5;
2153         else
2154                 vsize = (hsize * 9) / 16;
2155 
2156         /* HDTV hack, part 1 */
2157         if (vrefresh_rate == 60 &&
2158             ((hsize == 1360 && vsize == 765) ||
2159              (hsize == 1368 && vsize == 769))) {
2160                 hsize = 1366;
2161                 vsize = 768;
2162         }
2163 
2164         /*
2165          * If this connector already has a mode for this size and refresh
2166          * rate (because it came from detailed or CVT info), use that
2167          * instead.  This way we don't have to guess at interlace or
2168          * reduced blanking.
2169          */
2170         list_for_each_entry(m, &connector->probed_modes, head)
2171                 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2172                     drm_mode_vrefresh(m) == vrefresh_rate)
2173                         return NULL;
2174 
2175         /* HDTV hack, part 2 */
2176         if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2177                 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2178                                     false);
2179                 if (!mode)
2180                         return NULL;
2181                 mode->hdisplay = 1366;
2182                 mode->hsync_start = mode->hsync_start - 1;
2183                 mode->hsync_end = mode->hsync_end - 1;
2184                 return mode;
2185         }
2186 
2187         /* check whether it can be found in default mode table */
2188         if (drm_monitor_supports_rb(edid)) {
2189                 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2190                                          true);
2191                 if (mode)
2192                         return mode;
2193         }
2194         mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2195         if (mode)
2196                 return mode;
2197 
2198         /* okay, generate it */
2199         switch (timing_level) {
2200         case LEVEL_DMT:
2201                 break;
2202         case LEVEL_GTF:
2203                 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2204                 break;
2205         case LEVEL_GTF2:
2206                 /*
2207                  * This is potentially wrong if there's ever a monitor with
2208                  * more than one ranges section, each claiming a different
2209                  * secondary GTF curve.  Please don't do that.
2210                  */
2211                 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2212                 if (!mode)
2213                         return NULL;
2214                 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2215                         drm_mode_destroy(dev, mode);
2216                         mode = drm_gtf_mode_complex(dev, hsize, vsize,
2217                                                     vrefresh_rate, 0, 0,
2218                                                     drm_gtf2_m(edid),
2219                                                     drm_gtf2_2c(edid),
2220                                                     drm_gtf2_k(edid),
2221                                                     drm_gtf2_2j(edid));
2222                 }
2223                 break;
2224         case LEVEL_CVT:
2225                 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2226                                     false);
2227                 break;
2228         }
2229         return mode;
2230 }
2231 
2232 /*
2233  * EDID is delightfully ambiguous about how interlaced modes are to be
2234  * encoded.  Our internal representation is of frame height, but some
2235  * HDTV detailed timings are encoded as field height.
2236  *
2237  * The format list here is from CEA, in frame size.  Technically we
2238  * should be checking refresh rate too.  Whatever.
2239  */
2240 static void
2241 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2242                             struct detailed_pixel_timing *pt)
2243 {
2244         int i;
2245         static const struct {
2246                 int w, h;
2247         } cea_interlaced[] = {
2248                 { 1920, 1080 },
2249                 {  720,  480 },
2250                 { 1440,  480 },
2251                 { 2880,  480 },
2252                 {  720,  576 },
2253                 { 1440,  576 },
2254                 { 2880,  576 },
2255         };
2256 
2257         if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2258                 return;
2259 
2260         for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2261                 if ((mode->hdisplay == cea_interlaced[i].w) &&
2262                     (mode->vdisplay == cea_interlaced[i].h / 2)) {
2263                         mode->vdisplay *= 2;
2264                         mode->vsync_start *= 2;
2265                         mode->vsync_end *= 2;
2266                         mode->vtotal *= 2;
2267                         mode->vtotal |= 1;
2268                 }
2269         }
2270 
2271         mode->flags |= DRM_MODE_FLAG_INTERLACE;
2272 }
2273 
2274 /**
2275  * drm_mode_detailed - create a new mode from an EDID detailed timing section
2276  * @dev: DRM device (needed to create new mode)
2277  * @edid: EDID block
2278  * @timing: EDID detailed timing info
2279  * @quirks: quirks to apply
2280  *
2281  * An EDID detailed timing block contains enough info for us to create and
2282  * return a new struct drm_display_mode.
2283  */
2284 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2285                                                   struct edid *edid,
2286                                                   struct detailed_timing *timing,
2287                                                   u32 quirks)
2288 {
2289         struct drm_display_mode *mode;
2290         struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2291         unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2292         unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2293         unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2294         unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2295         unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2296         unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2297         unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2298         unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2299 
2300         /* ignore tiny modes */
2301         if (hactive < 64 || vactive < 64)
2302                 return NULL;
2303 
2304         if (pt->misc & DRM_EDID_PT_STEREO) {
2305                 DRM_DEBUG_KMS("stereo mode not supported\n");
2306                 return NULL;
2307         }
2308         if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2309                 DRM_DEBUG_KMS("composite sync not supported\n");
2310         }
2311 
2312         /* it is incorrect if hsync/vsync width is zero */
2313         if (!hsync_pulse_width || !vsync_pulse_width) {
2314                 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2315                                 "Wrong Hsync/Vsync pulse width\n");
2316                 return NULL;
2317         }
2318 
2319         if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2320                 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2321                 if (!mode)
2322                         return NULL;
2323 
2324                 goto set_size;
2325         }
2326 
2327         mode = drm_mode_create(dev);
2328         if (!mode)
2329                 return NULL;
2330 
2331         if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2332                 timing->pixel_clock = cpu_to_le16(1088);
2333 
2334         mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2335 
2336         mode->hdisplay = hactive;
2337         mode->hsync_start = mode->hdisplay + hsync_offset;
2338         mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2339         mode->htotal = mode->hdisplay + hblank;
2340 
2341         mode->vdisplay = vactive;
2342         mode->vsync_start = mode->vdisplay + vsync_offset;
2343         mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2344         mode->vtotal = mode->vdisplay + vblank;
2345 
2346         /* Some EDIDs have bogus h/vtotal values */
2347         if (mode->hsync_end > mode->htotal)
2348                 mode->htotal = mode->hsync_end + 1;
2349         if (mode->vsync_end > mode->vtotal)
2350                 mode->vtotal = mode->vsync_end + 1;
2351 
2352         drm_mode_do_interlace_quirk(mode, pt);
2353 
2354         if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2355                 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2356         }
2357 
2358         mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2359                 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2360         mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2361                 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2362 
2363 set_size:
2364         mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2365         mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2366 
2367         if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2368                 mode->width_mm *= 10;
2369                 mode->height_mm *= 10;
2370         }
2371 
2372         if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2373                 mode->width_mm = edid->width_cm * 10;
2374                 mode->height_mm = edid->height_cm * 10;
2375         }
2376 
2377         mode->type = DRM_MODE_TYPE_DRIVER;
2378         mode->vrefresh = drm_mode_vrefresh(mode);
2379         drm_mode_set_name(mode);
2380 
2381         return mode;
2382 }
2383 
2384 static bool
2385 mode_in_hsync_range(const struct drm_display_mode *mode,
2386                     struct edid *edid, u8 *t)
2387 {
2388         int hsync, hmin, hmax;
2389 
2390         hmin = t[7];
2391         if (edid->revision >= 4)
2392             hmin += ((t[4] & 0x04) ? 255 : 0);
2393         hmax = t[8];
2394         if (edid->revision >= 4)
2395             hmax += ((t[4] & 0x08) ? 255 : 0);
2396         hsync = drm_mode_hsync(mode);
2397 
2398         return (hsync <= hmax && hsync >= hmin);
2399 }
2400 
2401 static bool
2402 mode_in_vsync_range(const struct drm_display_mode *mode,
2403                     struct edid *edid, u8 *t)
2404 {
2405         int vsync, vmin, vmax;
2406 
2407         vmin = t[5];
2408         if (edid->revision >= 4)
2409             vmin += ((t[4] & 0x01) ? 255 : 0);
2410         vmax = t[6];
2411         if (edid->revision >= 4)
2412             vmax += ((t[4] & 0x02) ? 255 : 0);
2413         vsync = drm_mode_vrefresh(mode);
2414 
2415         return (vsync <= vmax && vsync >= vmin);
2416 }
2417 
2418 static u32
2419 range_pixel_clock(struct edid *edid, u8 *t)
2420 {
2421         /* unspecified */
2422         if (t[9] == 0 || t[9] == 255)
2423                 return 0;
2424 
2425         /* 1.4 with CVT support gives us real precision, yay */
2426         if (edid->revision >= 4 && t[10] == 0x04)
2427                 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2428 
2429         /* 1.3 is pathetic, so fuzz up a bit */
2430         return t[9] * 10000 + 5001;
2431 }
2432 
2433 static bool
2434 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2435               struct detailed_timing *timing)
2436 {
2437         u32 max_clock;
2438         u8 *t = (u8 *)timing;
2439 
2440         if (!mode_in_hsync_range(mode, edid, t))
2441                 return false;
2442 
2443         if (!mode_in_vsync_range(mode, edid, t))
2444                 return false;
2445 
2446         if ((max_clock = range_pixel_clock(edid, t)))
2447                 if (mode->clock > max_clock)
2448                         return false;
2449 
2450         /* 1.4 max horizontal check */
2451         if (edid->revision >= 4 && t[10] == 0x04)
2452                 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2453                         return false;
2454 
2455         if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2456                 return false;
2457 
2458         return true;
2459 }
2460 
2461 static bool valid_inferred_mode(const struct drm_connector *connector,
2462                                 const struct drm_display_mode *mode)
2463 {
2464         const struct drm_display_mode *m;
2465         bool ok = false;
2466 
2467         list_for_each_entry(m, &connector->probed_modes, head) {
2468                 if (mode->hdisplay == m->hdisplay &&
2469                     mode->vdisplay == m->vdisplay &&
2470                     drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2471                         return false; /* duplicated */
2472                 if (mode->hdisplay <= m->hdisplay &&
2473                     mode->vdisplay <= m->vdisplay)
2474                         ok = true;
2475         }
2476         return ok;
2477 }
2478 
2479 static int
2480 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2481                         struct detailed_timing *timing)
2482 {
2483         int i, modes = 0;
2484         struct drm_display_mode *newmode;
2485         struct drm_device *dev = connector->dev;
2486 
2487         for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2488                 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2489                     valid_inferred_mode(connector, drm_dmt_modes + i)) {
2490                         newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2491                         if (newmode) {
2492                                 drm_mode_probed_add(connector, newmode);
2493                                 modes++;
2494                         }
2495                 }
2496         }
2497 
2498         return modes;
2499 }
2500 
2501 /* fix up 1366x768 mode from 1368x768;
2502  * GFT/CVT can't express 1366 width which isn't dividable by 8
2503  */
2504 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2505 {
2506         if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2507                 mode->hdisplay = 1366;
2508                 mode->hsync_start--;
2509                 mode->hsync_end--;
2510                 drm_mode_set_name(mode);
2511         }
2512 }
2513 
2514 static int
2515 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2516                         struct detailed_timing *timing)
2517 {
2518         int i, modes = 0;
2519         struct drm_display_mode *newmode;
2520         struct drm_device *dev = connector->dev;
2521 
2522         for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2523                 const struct minimode *m = &extra_modes[i];
2524                 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2525                 if (!newmode)
2526                         return modes;
2527 
2528                 drm_mode_fixup_1366x768(newmode);
2529                 if (!mode_in_range(newmode, edid, timing) ||
2530                     !valid_inferred_mode(connector, newmode)) {
2531                         drm_mode_destroy(dev, newmode);
2532                         continue;
2533                 }
2534 
2535                 drm_mode_probed_add(connector, newmode);
2536                 modes++;
2537         }
2538 
2539         return modes;
2540 }
2541 
2542 static int
2543 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2544                         struct detailed_timing *timing)
2545 {
2546         int i, modes = 0;
2547         struct drm_display_mode *newmode;
2548         struct drm_device *dev = connector->dev;
2549         bool rb = drm_monitor_supports_rb(edid);
2550 
2551         for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2552                 const struct minimode *m = &extra_modes[i];
2553                 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2554                 if (!newmode)
2555                         return modes;
2556 
2557                 drm_mode_fixup_1366x768(newmode);
2558                 if (!mode_in_range(newmode, edid, timing) ||
2559                     !valid_inferred_mode(connector, newmode)) {
2560                         drm_mode_destroy(dev, newmode);
2561                         continue;
2562                 }
2563 
2564                 drm_mode_probed_add(connector, newmode);
2565                 modes++;
2566         }
2567 
2568         return modes;
2569 }
2570 
2571 static void
2572 do_inferred_modes(struct detailed_timing *timing, void *c)
2573 {
2574         struct detailed_mode_closure *closure = c;
2575         struct detailed_non_pixel *data = &timing->data.other_data;
2576         struct detailed_data_monitor_range *range = &data->data.range;
2577 
2578         if (data->type != EDID_DETAIL_MONITOR_RANGE)
2579                 return;
2580 
2581         closure->modes += drm_dmt_modes_for_range(closure->connector,
2582                                                   closure->edid,
2583                                                   timing);
2584         
2585         if (!version_greater(closure->edid, 1, 1))
2586                 return; /* GTF not defined yet */
2587 
2588         switch (range->flags) {
2589         case 0x02: /* secondary gtf, XXX could do more */
2590         case 0x00: /* default gtf */
2591                 closure->modes += drm_gtf_modes_for_range(closure->connector,
2592                                                           closure->edid,
2593                                                           timing);
2594                 break;
2595         case 0x04: /* cvt, only in 1.4+ */
2596                 if (!version_greater(closure->edid, 1, 3))
2597                         break;
2598 
2599                 closure->modes += drm_cvt_modes_for_range(closure->connector,
2600                                                           closure->edid,
2601                                                           timing);
2602                 break;
2603         case 0x01: /* just the ranges, no formula */
2604         default:
2605                 break;
2606         }
2607 }
2608 
2609 static int
2610 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2611 {
2612         struct detailed_mode_closure closure = {
2613                 .connector = connector,
2614                 .edid = edid,
2615         };
2616 
2617         if (version_greater(edid, 1, 0))
2618                 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2619                                             &closure);
2620 
2621         return closure.modes;
2622 }
2623 
2624 static int
2625 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2626 {
2627         int i, j, m, modes = 0;
2628         struct drm_display_mode *mode;
2629         u8 *est = ((u8 *)timing) + 6;
2630 
2631         for (i = 0; i < 6; i++) {
2632                 for (j = 7; j >= 0; j--) {
2633                         m = (i * 8) + (7 - j);
2634                         if (m >= ARRAY_SIZE(est3_modes))
2635                                 break;
2636                         if (est[i] & (1 << j)) {
2637                                 mode = drm_mode_find_dmt(connector->dev,
2638                                                          est3_modes[m].w,
2639                                                          est3_modes[m].h,
2640                                                          est3_modes[m].r,
2641                                                          est3_modes[m].rb);
2642                                 if (mode) {
2643                                         drm_mode_probed_add(connector, mode);
2644                                         modes++;
2645                                 }
2646                         }
2647                 }
2648         }
2649 
2650         return modes;
2651 }
2652 
2653 static void
2654 do_established_modes(struct detailed_timing *timing, void *c)
2655 {
2656         struct detailed_mode_closure *closure = c;
2657         struct detailed_non_pixel *data = &timing->data.other_data;
2658 
2659         if (data->type == EDID_DETAIL_EST_TIMINGS)
2660                 closure->modes += drm_est3_modes(closure->connector, timing);
2661 }
2662 
2663 /**
2664  * add_established_modes - get est. modes from EDID and add them
2665  * @connector: connector to add mode(s) to
2666  * @edid: EDID block to scan
2667  *
2668  * Each EDID block contains a bitmap of the supported "established modes" list
2669  * (defined above).  Tease them out and add them to the global modes list.
2670  */
2671 static int
2672 add_established_modes(struct drm_connector *connector, struct edid *edid)
2673 {
2674         struct drm_device *dev = connector->dev;
2675         unsigned long est_bits = edid->established_timings.t1 |
2676                 (edid->established_timings.t2 << 8) |
2677                 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2678         int i, modes = 0;
2679         struct detailed_mode_closure closure = {
2680                 .connector = connector,
2681                 .edid = edid,
2682         };
2683 
2684         for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2685                 if (est_bits & (1<<i)) {
2686                         struct drm_display_mode *newmode;
2687                         newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2688                         if (newmode) {
2689                                 drm_mode_probed_add(connector, newmode);
2690                                 modes++;
2691                         }
2692                 }
2693         }
2694 
2695         if (version_greater(edid, 1, 0))
2696                     drm_for_each_detailed_block((u8 *)edid,
2697                                                 do_established_modes, &closure);
2698 
2699         return modes + closure.modes;
2700 }
2701 
2702 static void
2703 do_standard_modes(struct detailed_timing *timing, void *c)
2704 {
2705         struct detailed_mode_closure *closure = c;
2706         struct detailed_non_pixel *data = &timing->data.other_data;
2707         struct drm_connector *connector = closure->connector;
2708         struct edid *edid = closure->edid;
2709 
2710         if (data->type == EDID_DETAIL_STD_MODES) {
2711                 int i;
2712                 for (i = 0; i < 6; i++) {
2713                         struct std_timing *std;
2714                         struct drm_display_mode *newmode;
2715 
2716                         std = &data->data.timings[i];
2717                         newmode = drm_mode_std(connector, edid, std);
2718                         if (newmode) {
2719                                 drm_mode_probed_add(connector, newmode);
2720                                 closure->modes++;
2721                         }
2722                 }
2723         }
2724 }
2725 
2726 /**
2727  * add_standard_modes - get std. modes from EDID and add them
2728  * @connector: connector to add mode(s) to
2729  * @edid: EDID block to scan
2730  *
2731  * Standard modes can be calculated using the appropriate standard (DMT,
2732  * GTF or CVT. Grab them from @edid and add them to the list.
2733  */
2734 static int
2735 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2736 {
2737         int i, modes = 0;
2738         struct detailed_mode_closure closure = {
2739                 .connector = connector,
2740                 .edid = edid,
2741         };
2742 
2743         for (i = 0; i < EDID_STD_TIMINGS; i++) {
2744                 struct drm_display_mode *newmode;
2745 
2746                 newmode = drm_mode_std(connector, edid,
2747                                        &edid->standard_timings[i]);
2748                 if (newmode) {
2749                         drm_mode_probed_add(connector, newmode);
2750                         modes++;
2751                 }
2752         }
2753 
2754         if (version_greater(edid, 1, 0))
2755                 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2756                                             &closure);
2757 
2758         /* XXX should also look for standard codes in VTB blocks */
2759 
2760         return modes + closure.modes;
2761 }
2762 
2763 static int drm_cvt_modes(struct drm_connector *connector,
2764                          struct detailed_timing *timing)
2765 {
2766         int i, j, modes = 0;
2767         struct drm_display_mode *newmode;
2768         struct drm_device *dev = connector->dev;
2769         struct cvt_timing *cvt;
2770         const int rates[] = { 60, 85, 75, 60, 50 };
2771         const u8 empty[3] = { 0, 0, 0 };
2772 
2773         for (i = 0; i < 4; i++) {
2774                 int uninitialized_var(width), height;
2775                 cvt = &(timing->data.other_data.data.cvt[i]);
2776 
2777                 if (!memcmp(cvt->code, empty, 3))
2778                         continue;
2779 
2780                 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2781                 switch (cvt->code[1] & 0x0c) {
2782                 case 0x00:
2783                         width = height * 4 / 3;
2784                         break;
2785                 case 0x04:
2786                         width = height * 16 / 9;
2787                         break;
2788                 case 0x08:
2789                         width = height * 16 / 10;
2790                         break;
2791                 case 0x0c:
2792                         width = height * 15 / 9;
2793                         break;
2794                 }
2795 
2796                 for (j = 1; j < 5; j++) {
2797                         if (cvt->code[2] & (1 << j)) {
2798                                 newmode = drm_cvt_mode(dev, width, height,
2799                                                        rates[j], j == 0,
2800                                                        false, false);
2801                                 if (newmode) {
2802                                         drm_mode_probed_add(connector, newmode);
2803                                         modes++;
2804                                 }
2805                         }
2806                 }
2807         }
2808 
2809         return modes;
2810 }
2811 
2812 static void
2813 do_cvt_mode(struct detailed_timing *timing, void *c)
2814 {
2815         struct detailed_mode_closure *closure = c;
2816         struct detailed_non_pixel *data = &timing->data.other_data;
2817 
2818         if (data->type == EDID_DETAIL_CVT_3BYTE)
2819                 closure->modes += drm_cvt_modes(closure->connector, timing);
2820 }
2821 
2822 static int
2823 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2824 {       
2825         struct detailed_mode_closure closure = {
2826                 .connector = connector,
2827                 .edid = edid,
2828         };
2829 
2830         if (version_greater(edid, 1, 2))
2831                 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2832 
2833         /* XXX should also look for CVT codes in VTB blocks */
2834 
2835         return closure.modes;
2836 }
2837 
2838 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2839 
2840 static void
2841 do_detailed_mode(struct detailed_timing *timing, void *c)
2842 {
2843         struct detailed_mode_closure *closure = c;
2844         struct drm_display_mode *newmode;
2845 
2846         if (timing->pixel_clock) {
2847                 newmode = drm_mode_detailed(closure->connector->dev,
2848                                             closure->edid, timing,
2849                                             closure->quirks);
2850                 if (!newmode)
2851                         return;
2852 
2853                 if (closure->preferred)
2854                         newmode->type |= DRM_MODE_TYPE_PREFERRED;
2855 
2856                 /*
2857                  * Detailed modes are limited to 10kHz pixel clock resolution,
2858                  * so fix up anything that looks like CEA/HDMI mode, but the clock
2859                  * is just slightly off.
2860                  */
2861                 fixup_detailed_cea_mode_clock(newmode);
2862 
2863                 drm_mode_probed_add(closure->connector, newmode);
2864                 closure->modes++;
2865                 closure->preferred = false;
2866         }
2867 }
2868 
2869 /*
2870  * add_detailed_modes - Add modes from detailed timings
2871  * @connector: attached connector
2872  * @edid: EDID block to scan
2873  * @quirks: quirks to apply
2874  */
2875 static int
2876 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2877                    u32 quirks)
2878 {
2879         struct detailed_mode_closure closure = {
2880                 .connector = connector,
2881                 .edid = edid,
2882                 .preferred = true,
2883                 .quirks = quirks,
2884         };
2885 
2886         if (closure.preferred && !version_greater(edid, 1, 3))
2887                 closure.preferred =
2888                     (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2889 
2890         drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2891 
2892         return closure.modes;
2893 }
2894 
2895 #define AUDIO_BLOCK     0x01
2896 #define VIDEO_BLOCK     0x02
2897 #define VENDOR_BLOCK    0x03
2898 #define SPEAKER_BLOCK   0x04
2899 #define HDR_STATIC_METADATA_BLOCK       0x6
2900 #define USE_EXTENDED_TAG 0x07
2901 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2902 #define EXT_VIDEO_DATA_BLOCK_420        0x0E
2903 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2904 #define EDID_BASIC_AUDIO        (1 << 6)
2905 #define EDID_CEA_YCRCB444       (1 << 5)
2906 #define EDID_CEA_YCRCB422       (1 << 4)
2907 #define EDID_CEA_VCDB_QS        (1 << 6)
2908 
2909 /*
2910  * Search EDID for CEA extension block.
2911  */
2912 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2913 {
2914         u8 *edid_ext = NULL;
2915         int i;
2916 
2917         /* No EDID or EDID extensions */
2918         if (edid == NULL || edid->extensions == 0)
2919                 return NULL;
2920 
2921         /* Find CEA extension */
2922         for (i = 0; i < edid->extensions; i++) {
2923                 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2924                 if (edid_ext[0] == ext_id)
2925                         break;
2926         }
2927 
2928         if (i == edid->extensions)
2929                 return NULL;
2930 
2931         return edid_ext;
2932 }
2933 
2934 
2935 static u8 *drm_find_displayid_extension(const struct edid *edid)
2936 {
2937         return drm_find_edid_extension(edid, DISPLAYID_EXT);
2938 }
2939 
2940 static u8 *drm_find_cea_extension(const struct edid *edid)
2941 {
2942         int ret;
2943         int idx = 1;
2944         int length = EDID_LENGTH;
2945         struct displayid_block *block;
2946         u8 *cea;
2947         u8 *displayid;
2948 
2949         /* Look for a top level CEA extension block */
2950         cea = drm_find_edid_extension(edid, CEA_EXT);
2951         if (cea)
2952                 return cea;
2953 
2954         /* CEA blocks can also be found embedded in a DisplayID block */
2955         displayid = drm_find_displayid_extension(edid);
2956         if (!displayid)
2957                 return NULL;
2958 
2959         ret = validate_displayid(displayid, length, idx);
2960         if (ret)
2961                 return NULL;
2962 
2963         idx += sizeof(struct displayid_hdr);
2964         for_each_displayid_db(displayid, block, idx, length) {
2965                 if (block->tag == DATA_BLOCK_CTA) {
2966                         cea = (u8 *)block;
2967                         break;
2968                 }
2969         }
2970 
2971         return cea;
2972 }
2973 
2974 /*
2975  * Calculate the alternate clock for the CEA mode
2976  * (60Hz vs. 59.94Hz etc.)
2977  */
2978 static unsigned int
2979 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2980 {
2981         unsigned int clock = cea_mode->clock;
2982 
2983         if (cea_mode->vrefresh % 6 != 0)
2984                 return clock;
2985 
2986         /*
2987          * edid_cea_modes contains the 59.94Hz
2988          * variant for 240 and 480 line modes,
2989          * and the 60Hz variant otherwise.
2990          */
2991         if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2992                 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2993         else
2994                 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2995 
2996         return clock;
2997 }
2998 
2999 static bool
3000 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3001 {
3002         /*
3003          * For certain VICs the spec allows the vertical
3004          * front porch to vary by one or two lines.
3005          *
3006          * cea_modes[] stores the variant with the shortest
3007          * vertical front porch. We can adjust the mode to
3008          * get the other variants by simply increasing the
3009          * vertical front porch length.
3010          */
3011         BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
3012                      edid_cea_modes[9].vtotal != 262 ||
3013                      edid_cea_modes[12].vtotal != 262 ||
3014                      edid_cea_modes[13].vtotal != 262 ||
3015                      edid_cea_modes[23].vtotal != 312 ||
3016                      edid_cea_modes[24].vtotal != 312 ||
3017                      edid_cea_modes[27].vtotal != 312 ||
3018                      edid_cea_modes[28].vtotal != 312);
3019 
3020         if (((vic == 8 || vic == 9 ||
3021               vic == 12 || vic == 13) && mode->vtotal < 263) ||
3022             ((vic == 23 || vic == 24 ||
3023               vic == 27 || vic == 28) && mode->vtotal < 314)) {
3024                 mode->vsync_start++;
3025                 mode->vsync_end++;
3026                 mode->vtotal++;
3027 
3028                 return true;
3029         }
3030 
3031         return false;
3032 }
3033 
3034 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3035                                              unsigned int clock_tolerance)
3036 {
3037         unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3038         u8 vic;
3039 
3040         if (!to_match->clock)
3041                 return 0;
3042 
3043         if (to_match->picture_aspect_ratio)
3044                 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3045 
3046         for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3047                 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3048                 unsigned int clock1, clock2;
3049 
3050                 /* Check both 60Hz and 59.94Hz */
3051                 clock1 = cea_mode.clock;
3052                 clock2 = cea_mode_alternate_clock(&cea_mode);
3053 
3054                 if (abs(to_match->clock - clock1) > clock_tolerance &&
3055                     abs(to_match->clock - clock2) > clock_tolerance)
3056                         continue;
3057 
3058                 do {
3059                         if (drm_mode_match(to_match, &cea_mode, match_flags))
3060                                 return vic;
3061                 } while (cea_mode_alternate_timings(vic, &cea_mode));
3062         }
3063 
3064         return 0;
3065 }
3066 
3067 /**
3068  * drm_match_cea_mode - look for a CEA mode matching given mode
3069  * @to_match: display mode
3070  *
3071  * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3072  * mode.
3073  */
3074 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3075 {
3076         unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3077         u8 vic;
3078 
3079         if (!to_match->clock)
3080                 return 0;
3081 
3082         if (to_match->picture_aspect_ratio)
3083                 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3084 
3085         for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3086                 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3087                 unsigned int clock1, clock2;
3088 
3089                 /* Check both 60Hz and 59.94Hz */
3090                 clock1 = cea_mode.clock;
3091                 clock2 = cea_mode_alternate_clock(&cea_mode);
3092 
3093                 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3094                     KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3095                         continue;
3096 
3097                 do {
3098                         if (drm_mode_match(to_match, &cea_mode, match_flags))
3099                                 return vic;
3100                 } while (cea_mode_alternate_timings(vic, &cea_mode));
3101         }
3102 
3103         return 0;
3104 }
3105 EXPORT_SYMBOL(drm_match_cea_mode);
3106 
3107 static bool drm_valid_cea_vic(u8 vic)
3108 {
3109         return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3110 }
3111 
3112 /**
3113  * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3114  * the input VIC from the CEA mode list
3115  * @video_code: ID given to each of the CEA modes
3116  *
3117  * Returns picture aspect ratio
3118  */
3119 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3120 {
3121         return edid_cea_modes[video_code].picture_aspect_ratio;
3122 }
3123 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3124 
3125 /*
3126  * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3127  * specific block).
3128  *
3129  * It's almost like cea_mode_alternate_clock(), we just need to add an
3130  * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3131  * one.
3132  */
3133 static unsigned int
3134 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3135 {
3136         if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3137                 return hdmi_mode->clock;
3138 
3139         return cea_mode_alternate_clock(hdmi_mode);
3140 }
3141 
3142 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3143                                               unsigned int clock_tolerance)
3144 {
3145         unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3146         u8 vic;
3147 
3148         if (!to_match->clock)
3149                 return 0;
3150 
3151         for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3152                 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3153                 unsigned int clock1, clock2;
3154 
3155                 /* Make sure to also match alternate clocks */
3156                 clock1 = hdmi_mode->clock;
3157                 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3158 
3159                 if (abs(to_match->clock - clock1) > clock_tolerance &&
3160                     abs(to_match->clock - clock2) > clock_tolerance)
3161                         continue;
3162 
3163                 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3164                         return vic;
3165         }
3166 
3167         return 0;
3168 }
3169 
3170 /*
3171  * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3172  * @to_match: display mode
3173  *
3174  * An HDMI mode is one defined in the HDMI vendor specific block.
3175  *
3176  * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3177  */
3178 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3179 {
3180         unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3181         u8 vic;
3182 
3183         if (!to_match->clock)
3184                 return 0;
3185 
3186         for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3187                 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3188                 unsigned int clock1, clock2;
3189 
3190                 /* Make sure to also match alternate clocks */
3191                 clock1 = hdmi_mode->clock;
3192                 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3193 
3194                 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3195                      KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3196                     drm_mode_match(to_match, hdmi_mode, match_flags))
3197                         return vic;
3198         }
3199         return 0;
3200 }
3201 
3202 static bool drm_valid_hdmi_vic(u8 vic)
3203 {
3204         return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3205 }
3206 
3207 static int
3208 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3209 {
3210         struct drm_device *dev = connector->dev;
3211         struct drm_display_mode *mode, *tmp;
3212         LIST_HEAD(list);
3213         int modes = 0;
3214 
3215         /* Don't add CEA modes if the CEA extension block is missing */
3216         if (!drm_find_cea_extension(edid))
3217                 return 0;
3218 
3219         /*
3220          * Go through all probed modes and create a new mode
3221          * with the alternate clock for certain CEA modes.
3222          */
3223         list_for_each_entry(mode, &connector->probed_modes, head) {
3224                 const struct drm_display_mode *cea_mode = NULL;
3225                 struct drm_display_mode *newmode;
3226                 u8 vic = drm_match_cea_mode(mode);
3227                 unsigned int clock1, clock2;
3228 
3229                 if (drm_valid_cea_vic(vic)) {
3230                         cea_mode = &edid_cea_modes[vic];
3231                         clock2 = cea_mode_alternate_clock(cea_mode);
3232                 } else {
3233                         vic = drm_match_hdmi_mode(mode);
3234                         if (drm_valid_hdmi_vic(vic)) {
3235                                 cea_mode = &edid_4k_modes[vic];
3236                                 clock2 = hdmi_mode_alternate_clock(cea_mode);
3237                         }
3238                 }
3239 
3240                 if (!cea_mode)
3241                         continue;
3242 
3243                 clock1 = cea_mode->clock;
3244 
3245                 if (clock1 == clock2)
3246                         continue;
3247 
3248                 if (mode->clock != clock1 && mode->clock != clock2)
3249                         continue;
3250 
3251                 newmode = drm_mode_duplicate(dev, cea_mode);
3252                 if (!newmode)
3253                         continue;
3254 
3255                 /* Carry over the stereo flags */
3256                 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3257 
3258                 /*
3259                  * The current mode could be either variant. Make
3260                  * sure to pick the "other" clock for the new mode.
3261                  */
3262                 if (mode->clock != clock1)
3263                         newmode->clock = clock1;
3264                 else
3265                         newmode->clock = clock2;
3266 
3267                 list_add_tail(&newmode->head, &list);
3268         }
3269 
3270         list_for_each_entry_safe(mode, tmp, &list, head) {
3271                 list_del(&mode->head);
3272                 drm_mode_probed_add(connector, mode);
3273                 modes++;
3274         }
3275 
3276         return modes;
3277 }
3278 
3279 static u8 svd_to_vic(u8 svd)
3280 {
3281         /* 0-6 bit vic, 7th bit native mode indicator */
3282         if ((svd >= 1 &&  svd <= 64) || (svd >= 129 && svd <= 192))
3283                 return svd & 127;
3284 
3285         return svd;
3286 }
3287 
3288 static struct drm_display_mode *
3289 drm_display_mode_from_vic_index(struct drm_connector *connector,
3290                                 const u8 *video_db, u8 video_len,
3291                                 u8 video_index)
3292 {
3293         struct drm_device *dev = connector->dev;
3294         struct drm_display_mode *newmode;
3295         u8 vic;
3296 
3297         if (video_db == NULL || video_index >= video_len)
3298                 return NULL;
3299 
3300         /* CEA modes are numbered 1..127 */
3301         vic = svd_to_vic(video_db[video_index]);
3302         if (!drm_valid_cea_vic(vic))
3303                 return NULL;
3304 
3305         newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3306         if (!newmode)
3307                 return NULL;
3308 
3309         newmode->vrefresh = 0;
3310 
3311         return newmode;
3312 }
3313 
3314 /*
3315  * do_y420vdb_modes - Parse YCBCR 420 only modes
3316  * @connector: connector corresponding to the HDMI sink
3317  * @svds: start of the data block of CEA YCBCR 420 VDB
3318  * @len: length of the CEA YCBCR 420 VDB
3319  *
3320  * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3321  * which contains modes which can be supported in YCBCR 420
3322  * output format only.
3323  */
3324 static int do_y420vdb_modes(struct drm_connector *connector,
3325                             const u8 *svds, u8 svds_len)
3326 {
3327         int modes = 0, i;
3328         struct drm_device *dev = connector->dev;
3329         struct drm_display_info *info = &connector->display_info;
3330         struct drm_hdmi_info *hdmi = &info->hdmi;
3331 
3332         for (i = 0; i < svds_len; i++) {
3333                 u8 vic = svd_to_vic(svds[i]);
3334                 struct drm_display_mode *newmode;
3335 
3336                 if (!drm_valid_cea_vic(vic))
3337                         continue;
3338 
3339                 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3340                 if (!newmode)
3341                         break;
3342                 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3343                 drm_mode_probed_add(connector, newmode);
3344                 modes++;
3345         }
3346 
3347         if (modes > 0)
3348                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3349         return modes;
3350 }
3351 
3352 /*
3353  * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3354  * @connector: connector corresponding to the HDMI sink
3355  * @vic: CEA vic for the video mode to be added in the map
3356  *
3357  * Makes an entry for a videomode in the YCBCR 420 bitmap
3358  */
3359 static void
3360 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3361 {
3362         u8 vic = svd_to_vic(svd);
3363         struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3364 
3365         if (!drm_valid_cea_vic(vic))
3366                 return;
3367 
3368         bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3369 }
3370 
3371 static int
3372 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3373 {
3374         int i, modes = 0;
3375         struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3376 
3377         for (i = 0; i < len; i++) {
3378                 struct drm_display_mode *mode;
3379                 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3380                 if (mode) {
3381                         /*
3382                          * YCBCR420 capability block contains a bitmap which
3383                          * gives the index of CEA modes from CEA VDB, which
3384                          * can support YCBCR 420 sampling output also (apart
3385                          * from RGB/YCBCR444 etc).
3386                          * For example, if the bit 0 in bitmap is set,
3387                          * first mode in VDB can support YCBCR420 output too.
3388                          * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3389                          */
3390                         if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3391                                 drm_add_cmdb_modes(connector, db[i]);
3392 
3393                         drm_mode_probed_add(connector, mode);
3394                         modes++;
3395                 }
3396         }
3397 
3398         return modes;
3399 }
3400 
3401 struct stereo_mandatory_mode {
3402         int width, height, vrefresh;
3403         unsigned int flags;
3404 };
3405 
3406 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3407         { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3408         { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3409         { 1920, 1080, 50,
3410           DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3411         { 1920, 1080, 60,
3412           DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3413         { 1280, 720,  50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3414         { 1280, 720,  50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3415         { 1280, 720,  60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3416         { 1280, 720,  60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3417 };
3418 
3419 static bool
3420 stereo_match_mandatory(const struct drm_display_mode *mode,
3421                        const struct stereo_mandatory_mode *stereo_mode)
3422 {
3423         unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3424 
3425         return mode->hdisplay == stereo_mode->width &&
3426                mode->vdisplay == stereo_mode->height &&
3427                interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3428                drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3429 }
3430 
3431 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3432 {
3433         struct drm_device *dev = connector->dev;
3434         const struct drm_display_mode *mode;
3435         struct list_head stereo_modes;
3436         int modes = 0, i;
3437 
3438         INIT_LIST_HEAD(&stereo_modes);
3439 
3440         list_for_each_entry(mode, &connector->probed_modes, head) {
3441                 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3442                         const struct stereo_mandatory_mode *mandatory;
3443                         struct drm_display_mode *new_mode;
3444 
3445                         if (!stereo_match_mandatory(mode,
3446                                                     &stereo_mandatory_modes[i]))
3447                                 continue;
3448 
3449                         mandatory = &stereo_mandatory_modes[i];
3450                         new_mode = drm_mode_duplicate(dev, mode);
3451                         if (!new_mode)
3452                                 continue;
3453 
3454                         new_mode->flags |= mandatory->flags;
3455                         list_add_tail(&new_mode->head, &stereo_modes);
3456                         modes++;
3457                 }
3458         }
3459 
3460         list_splice_tail(&stereo_modes, &connector->probed_modes);
3461 
3462         return modes;
3463 }
3464 
3465 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3466 {
3467         struct drm_device *dev = connector->dev;
3468         struct drm_display_mode *newmode;
3469 
3470         if (!drm_valid_hdmi_vic(vic)) {
3471                 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3472                 return 0;
3473         }
3474 
3475         newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3476         if (!newmode)
3477                 return 0;
3478 
3479         drm_mode_probed_add(connector, newmode);
3480 
3481         return 1;
3482 }
3483 
3484 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3485                                const u8 *video_db, u8 video_len, u8 video_index)
3486 {
3487         struct drm_display_mode *newmode;
3488         int modes = 0;
3489 
3490         if (structure & (1 << 0)) {
3491                 newmode = drm_display_mode_from_vic_index(connector, video_db,
3492                                                           video_len,
3493                                                           video_index);
3494                 if (newmode) {
3495                         newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3496                         drm_mode_probed_add(connector, newmode);
3497                         modes++;
3498                 }
3499         }
3500         if (structure & (1 << 6)) {
3501                 newmode = drm_display_mode_from_vic_index(connector, video_db,
3502                                                           video_len,
3503                                                           video_index);
3504                 if (newmode) {
3505                         newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3506                         drm_mode_probed_add(connector, newmode);
3507                         modes++;
3508                 }
3509         }
3510         if (structure & (1 << 8)) {
3511                 newmode = drm_display_mode_from_vic_index(connector, video_db,
3512                                                           video_len,
3513                                                           video_index);
3514                 if (newmode) {
3515                         newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3516                         drm_mode_probed_add(connector, newmode);
3517                         modes++;
3518                 }
3519         }
3520 
3521         return modes;
3522 }
3523 
3524 /*
3525  * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3526  * @connector: connector corresponding to the HDMI sink
3527  * @db: start of the CEA vendor specific block
3528  * @len: length of the CEA block payload, ie. one can access up to db[len]
3529  *
3530  * Parses the HDMI VSDB looking for modes to add to @connector. This function
3531  * also adds the stereo 3d modes when applicable.
3532  */
3533 static int
3534 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3535                    const u8 *video_db, u8 video_len)
3536 {
3537         struct drm_display_info *info = &connector->display_info;
3538         int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3539         u8 vic_len, hdmi_3d_len = 0;
3540         u16 mask;
3541         u16 structure_all;
3542 
3543         if (len < 8)
3544                 goto out;
3545 
3546         /* no HDMI_Video_Present */
3547         if (!(db[8] & (1 << 5)))
3548                 goto out;
3549 
3550         /* Latency_Fields_Present */
3551         if (db[8] & (1 << 7))
3552                 offset += 2;
3553 
3554         /* I_Latency_Fields_Present */
3555         if (db[8] & (1 << 6))
3556                 offset += 2;
3557 
3558         /* the declared length is not long enough for the 2 first bytes
3559          * of additional video format capabilities */
3560         if (len < (8 + offset + 2))
3561                 goto out;
3562 
3563         /* 3D_Present */
3564         offset++;
3565         if (db[8 + offset] & (1 << 7)) {
3566                 modes += add_hdmi_mandatory_stereo_modes(connector);
3567 
3568                 /* 3D_Multi_present */
3569                 multi_present = (db[8 + offset] & 0x60) >> 5;
3570         }
3571 
3572         offset++;
3573         vic_len = db[8 + offset] >> 5;
3574         hdmi_3d_len = db[8 + offset] & 0x1f;
3575 
3576         for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3577                 u8 vic;
3578 
3579                 vic = db[9 + offset + i];
3580                 modes += add_hdmi_mode(connector, vic);
3581         }
3582         offset += 1 + vic_len;
3583 
3584         if (multi_present == 1)
3585                 multi_len = 2;
3586         else if (multi_present == 2)
3587                 multi_len = 4;
3588         else
3589                 multi_len = 0;
3590 
3591         if (len < (8 + offset + hdmi_3d_len - 1))
3592                 goto out;
3593 
3594         if (hdmi_3d_len < multi_len)
3595                 goto out;
3596 
3597         if (multi_present == 1 || multi_present == 2) {
3598                 /* 3D_Structure_ALL */
3599                 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3600 
3601                 /* check if 3D_MASK is present */
3602                 if (multi_present == 2)
3603                         mask = (db[10 + offset] << 8) | db[11 + offset];
3604                 else
3605                         mask = 0xffff;
3606 
3607                 for (i = 0; i < 16; i++) {
3608                         if (mask & (1 << i))
3609                                 modes += add_3d_struct_modes(connector,
3610                                                 structure_all,
3611                                                 video_db,
3612                                                 video_len, i);
3613                 }
3614         }
3615 
3616         offset += multi_len;
3617 
3618         for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3619                 int vic_index;
3620                 struct drm_display_mode *newmode = NULL;
3621                 unsigned int newflag = 0;
3622                 bool detail_present;
3623 
3624                 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3625 
3626                 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3627                         break;
3628 
3629                 /* 2D_VIC_order_X */
3630                 vic_index = db[8 + offset + i] >> 4;
3631 
3632                 /* 3D_Structure_X */
3633                 switch (db[8 + offset + i] & 0x0f) {
3634                 case 0:
3635                         newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3636                         break;
3637                 case 6:
3638                         newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3639                         break;
3640                 case 8:
3641                         /* 3D_Detail_X */
3642                         if ((db[9 + offset + i] >> 4) == 1)
3643                                 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3644                         break;
3645                 }
3646 
3647                 if (newflag != 0) {
3648                         newmode = drm_display_mode_from_vic_index(connector,
3649                                                                   video_db,
3650                                                                   video_len,
3651                                                                   vic_index);
3652 
3653                         if (newmode) {
3654                                 newmode->flags |= newflag;
3655                                 drm_mode_probed_add(connector, newmode);
3656                                 modes++;
3657                         }
3658                 }
3659 
3660                 if (detail_present)
3661                         i++;
3662         }
3663 
3664 out:
3665         if (modes > 0)
3666                 info->has_hdmi_infoframe = true;
3667         return modes;
3668 }
3669 
3670 static int
3671 cea_db_payload_len(const u8 *db)
3672 {
3673         return db[0] & 0x1f;
3674 }
3675 
3676 static int
3677 cea_db_extended_tag(const u8 *db)
3678 {
3679         return db[1];
3680 }
3681 
3682 static int
3683 cea_db_tag(const u8 *db)
3684 {
3685         return db[0] >> 5;
3686 }
3687 
3688 static int
3689 cea_revision(const u8 *cea)
3690 {
3691         return cea[1];
3692 }
3693 
3694 static int
3695 cea_db_offsets(const u8 *cea, int *start, int *end)
3696 {
3697         /* DisplayID CTA extension blocks and top-level CEA EDID
3698          * block header definitions differ in the following bytes:
3699          *   1) Byte 2 of the header specifies length differently,
3700          *   2) Byte 3 is only present in the CEA top level block.
3701          *
3702          * The different definitions for byte 2 follow.
3703          *
3704          * DisplayID CTA extension block defines byte 2 as:
3705          *   Number of payload bytes
3706          *
3707          * CEA EDID block defines byte 2 as:
3708          *   Byte number (decimal) within this block where the 18-byte
3709          *   DTDs begin. If no non-DTD data is present in this extension
3710          *   block, the value should be set to 04h (the byte after next).
3711          *   If set to 00h, there are no DTDs present in this block and
3712          *   no non-DTD data.
3713          */
3714         if (cea[0] == DATA_BLOCK_CTA) {
3715                 *start = 3;
3716                 *end = *start + cea[2];
3717         } else if (cea[0] == CEA_EXT) {
3718                 /* Data block offset in CEA extension block */
3719                 *start = 4;
3720                 *end = cea[2];
3721                 if (*end == 0)
3722                         *end = 127;
3723                 if (*end < 4 || *end > 127)
3724                         return -ERANGE;
3725         } else {
3726                 return -EOPNOTSUPP;
3727         }
3728 
3729         return 0;
3730 }
3731 
3732 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3733 {
3734         int hdmi_id;
3735 
3736         if (cea_db_tag(db) != VENDOR_BLOCK)
3737                 return false;
3738 
3739         if (cea_db_payload_len(db) < 5)
3740                 return false;
3741 
3742         hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3743 
3744         return hdmi_id == HDMI_IEEE_OUI;
3745 }
3746 
3747 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3748 {
3749         unsigned int oui;
3750 
3751         if (cea_db_tag(db) != VENDOR_BLOCK)
3752                 return false;
3753 
3754         if (cea_db_payload_len(db) < 7)
3755                 return false;
3756 
3757         oui = db[3] << 16 | db[2] << 8 | db[1];
3758 
3759         return oui == HDMI_FORUM_IEEE_OUI;
3760 }
3761 
3762 static bool cea_db_is_vcdb(const u8 *db)
3763 {
3764         if (cea_db_tag(db) != USE_EXTENDED_TAG)
3765                 return false;
3766 
3767         if (cea_db_payload_len(db) != 2)
3768                 return false;
3769 
3770         if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3771                 return false;
3772 
3773         return true;
3774 }
3775 
3776 static bool cea_db_is_y420cmdb(const u8 *db)
3777 {
3778         if (cea_db_tag(db) != USE_EXTENDED_TAG)
3779                 return false;
3780 
3781         if (!cea_db_payload_len(db))
3782                 return false;
3783 
3784         if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3785                 return false;
3786 
3787         return true;
3788 }
3789 
3790 static bool cea_db_is_y420vdb(const u8 *db)
3791 {
3792         if (cea_db_tag(db) != USE_EXTENDED_TAG)
3793                 return false;
3794 
3795         if (!cea_db_payload_len(db))
3796                 return false;
3797 
3798         if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3799                 return false;
3800 
3801         return true;
3802 }
3803 
3804 #define for_each_cea_db(cea, i, start, end) \
3805         for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3806 
3807 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3808                                       const u8 *db)
3809 {
3810         struct drm_display_info *info = &connector->display_info;
3811         struct drm_hdmi_info *hdmi = &info->hdmi;
3812         u8 map_len = cea_db_payload_len(db) - 1;
3813         u8 count;
3814         u64 map = 0;
3815 
3816         if (map_len == 0) {
3817                 /* All CEA modes support ycbcr420 sampling also.*/
3818                 hdmi->y420_cmdb_map = U64_MAX;
3819                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3820                 return;
3821         }
3822 
3823         /*
3824          * This map indicates which of the existing CEA block modes
3825          * from VDB can support YCBCR420 output too. So if bit=0 is
3826          * set, first mode from VDB can support YCBCR420 output too.
3827          * We will parse and keep this map, before parsing VDB itself
3828          * to avoid going through the same block again and again.
3829          *
3830          * Spec is not clear about max possible size of this block.
3831          * Clamping max bitmap block size at 8 bytes. Every byte can
3832          * address 8 CEA modes, in this way this map can address
3833          * 8*8 = first 64 SVDs.
3834          */
3835         if (WARN_ON_ONCE(map_len > 8))
3836                 map_len = 8;
3837 
3838         for (count = 0; count < map_len; count++)
3839                 map |= (u64)db[2 + count] << (8 * count);
3840 
3841         if (map)
3842                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3843 
3844         hdmi->y420_cmdb_map = map;
3845 }
3846 
3847 static int
3848 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3849 {
3850         const u8 *cea = drm_find_cea_extension(edid);
3851         const u8 *db, *hdmi = NULL, *video = NULL;
3852         u8 dbl, hdmi_len, video_len = 0;
3853         int modes = 0;
3854 
3855         if (cea && cea_revision(cea) >= 3) {
3856                 int i, start, end;
3857 
3858                 if (cea_db_offsets(cea, &start, &end))
3859                         return 0;
3860 
3861                 for_each_cea_db(cea, i, start, end) {
3862                         db = &cea[i];
3863                         dbl = cea_db_payload_len(db);
3864 
3865                         if (cea_db_tag(db) == VIDEO_BLOCK) {
3866                                 video = db + 1;
3867                                 video_len = dbl;
3868                                 modes += do_cea_modes(connector, video, dbl);
3869                         } else if (cea_db_is_hdmi_vsdb(db)) {
3870                                 hdmi = db;
3871                                 hdmi_len = dbl;
3872                         } else if (cea_db_is_y420vdb(db)) {
3873                                 const u8 *vdb420 = &db[2];
3874 
3875                                 /* Add 4:2:0(only) modes present in EDID */
3876                                 modes += do_y420vdb_modes(connector,
3877                                                           vdb420,
3878                                                           dbl - 1);
3879                         }
3880                 }
3881         }
3882 
3883         /*
3884          * We parse the HDMI VSDB after having added the cea modes as we will
3885          * be patching their flags when the sink supports stereo 3D.
3886          */
3887         if (hdmi)
3888                 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3889                                             video_len);
3890 
3891         return modes;
3892 }
3893 
3894 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3895 {
3896         const struct drm_display_mode *cea_mode;
3897         int clock1, clock2, clock;
3898         u8 vic;
3899         const char *type;
3900 
3901         /*
3902          * allow 5kHz clock difference either way to account for
3903          * the 10kHz clock resolution limit of detailed timings.
3904          */
3905         vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3906         if (drm_valid_cea_vic(vic)) {
3907                 type = "CEA";
3908                 cea_mode = &edid_cea_modes[vic];
3909                 clock1 = cea_mode->clock;
3910                 clock2 = cea_mode_alternate_clock(cea_mode);
3911         } else {
3912                 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3913                 if (drm_valid_hdmi_vic(vic)) {
3914                         type = "HDMI";
3915                         cea_mode = &edid_4k_modes[vic];
3916                         clock1 = cea_mode->clock;
3917                         clock2 = hdmi_mode_alternate_clock(cea_mode);
3918                 } else {
3919                         return;
3920                 }
3921         }
3922 
3923         /* pick whichever is closest */
3924         if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3925                 clock = clock1;
3926         else
3927                 clock = clock2;
3928 
3929         if (mode->clock == clock)
3930                 return;
3931 
3932         DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3933                   type, vic, mode->clock, clock);
3934         mode->clock = clock;
3935 }
3936 
3937 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
3938 {
3939         if (cea_db_tag(db) != USE_EXTENDED_TAG)
3940                 return false;
3941 
3942         if (db[1] != HDR_STATIC_METADATA_BLOCK)
3943                 return false;
3944 
3945         if (cea_db_payload_len(db) < 3)
3946                 return false;
3947 
3948         return true;
3949 }
3950 
3951 static uint8_t eotf_supported(const u8 *edid_ext)
3952 {
3953         return edid_ext[2] &
3954                 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
3955                  BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
3956                  BIT(HDMI_EOTF_SMPTE_ST2084) |
3957                  BIT(HDMI_EOTF_BT_2100_HLG));
3958 }
3959 
3960 static uint8_t hdr_metadata_type(const u8 *edid_ext)
3961 {
3962         return edid_ext[3] &
3963                 BIT(HDMI_STATIC_METADATA_TYPE1);
3964 }
3965 
3966 static void
3967 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
3968 {
3969         u16 len;
3970 
3971         len = cea_db_payload_len(db);
3972 
3973         connector->hdr_sink_metadata.hdmi_type1.eotf =
3974                                                 eotf_supported(db);
3975         connector->hdr_sink_metadata.hdmi_type1.metadata_type =
3976                                                 hdr_metadata_type(db);
3977 
3978         if (len >= 4)
3979                 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
3980         if (len >= 5)
3981                 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
3982         if (len >= 6)
3983                 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
3984 }
3985 
3986 static void
3987 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3988 {
3989         u8 len = cea_db_payload_len(db);
3990 
3991         if (len >= 6 && (db[6] & (1 << 7)))
3992                 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3993         if (len >= 8) {
3994                 connector->latency_present[0] = db[8] >> 7;
3995                 connector->latency_present[1] = (db[8] >> 6) & 1;
3996         }
3997         if (len >= 9)
3998                 connector->video_latency[0] = db[9];
3999         if (len >= 10)
4000                 connector->audio_latency[0] = db[10];
4001         if (len >= 11)
4002                 connector->video_latency[1] = db[11];
4003         if (len >= 12)
4004                 connector->audio_latency[1] = db[12];
4005 
4006         DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4007                       "video latency %d %d, "
4008                       "audio latency %d %d\n",
4009                       connector->latency_present[0],
4010                       connector->latency_present[1],
4011                       connector->video_latency[0],
4012                       connector->video_latency[1],
4013                       connector->audio_latency[0],
4014                       connector->audio_latency[1]);
4015 }
4016 
4017 static void
4018 monitor_name(struct detailed_timing *t, void *data)
4019 {
4020         if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
4021                 *(u8 **)data = t->data.other_data.data.str.str;
4022 }
4023 
4024 static int get_monitor_name(struct edid *edid, char name[13])
4025 {
4026         char *edid_name = NULL;
4027         int mnl;
4028 
4029         if (!edid || !name)
4030                 return 0;
4031 
4032         drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4033         for (mnl = 0; edid_name && mnl < 13; mnl++) {
4034                 if (edid_name[mnl] == 0x0a)
4035                         break;
4036 
4037                 name[mnl] = edid_name[mnl];
4038         }
4039 
4040         return mnl;
4041 }
4042 
4043 /**
4044  * drm_edid_get_monitor_name - fetch the monitor name from the edid
4045  * @edid: monitor EDID information
4046  * @name: pointer to a character array to hold the name of the monitor
4047  * @bufsize: The size of the name buffer (should be at least 14 chars.)
4048  *
4049  */
4050 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4051 {
4052         int name_length;
4053         char buf[13];
4054         
4055         if (bufsize <= 0)
4056                 return;
4057 
4058         name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4059         memcpy(name, buf, name_length);
4060         name[name_length] = '\0';
4061 }
4062 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4063 
4064 static void clear_eld(struct drm_connector *connector)
4065 {
4066         memset(connector->eld, 0, sizeof(connector->eld));
4067 
4068         connector->latency_present[0] = false;
4069         connector->latency_present[1] = false;
4070         connector->video_latency[0] = 0;
4071         connector->audio_latency[0] = 0;
4072         connector->video_latency[1] = 0;
4073         connector->audio_latency[1] = 0;
4074 }
4075 
4076 /*
4077  * drm_edid_to_eld - build ELD from EDID
4078  * @connector: connector corresponding to the HDMI/DP sink
4079  * @edid: EDID to parse
4080  *
4081  * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4082  * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4083  */
4084 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4085 {
4086         uint8_t *eld = connector->eld;
4087         u8 *cea;
4088         u8 *db;
4089         int total_sad_count = 0;
4090         int mnl;
4091         int dbl;
4092 
4093         clear_eld(connector);
4094 
4095         if (!edid)
4096                 return;
4097 
4098         cea = drm_find_cea_extension(edid);
4099         if (!cea) {
4100                 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4101                 return;
4102         }
4103 
4104         mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4105         DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4106 
4107         eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4108         eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4109 
4110         eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4111 
4112         eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4113         eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4114         eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4115         eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4116 
4117         if (cea_revision(cea) >= 3) {
4118                 int i, start, end;
4119 
4120                 if (cea_db_offsets(cea, &start, &end)) {
4121                         start = 0;
4122                         end = 0;
4123                 }
4124 
4125                 for_each_cea_db(cea, i, start, end) {
4126                         db = &cea[i];
4127                         dbl = cea_db_payload_len(db);
4128 
4129                         switch (cea_db_tag(db)) {
4130                                 int sad_count;
4131 
4132                         case AUDIO_BLOCK:
4133                                 /* Audio Data Block, contains SADs */
4134                                 sad_count = min(dbl / 3, 15 - total_sad_count);
4135                                 if (sad_count >= 1)
4136                                         memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4137                                                &db[1], sad_count * 3);
4138                                 total_sad_count += sad_count;
4139                                 break;
4140                         case SPEAKER_BLOCK:
4141                                 /* Speaker Allocation Data Block */
4142                                 if (dbl >= 1)
4143                                         eld[DRM_ELD_SPEAKER] = db[1];
4144                                 break;
4145                         case VENDOR_BLOCK:
4146                                 /* HDMI Vendor-Specific Data Block */
4147                                 if (cea_db_is_hdmi_vsdb(db))
4148                                         drm_parse_hdmi_vsdb_audio(connector, db);
4149                                 break;
4150                         default:
4151                                 break;
4152                         }
4153                 }
4154         }
4155         eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4156 
4157         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4158             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4159                 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4160         else
4161                 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4162 
4163         eld[DRM_ELD_BASELINE_ELD_LEN] =
4164                 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4165 
4166         DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4167                       drm_eld_size(eld), total_sad_count);
4168 }
4169 
4170 /**
4171  * drm_edid_to_sad - extracts SADs from EDID
4172  * @edid: EDID to parse
4173  * @sads: pointer that will be set to the extracted SADs
4174  *
4175  * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4176  *
4177  * Note: The returned pointer needs to be freed using kfree().
4178  *
4179  * Return: The number of found SADs or negative number on error.
4180  */
4181 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4182 {
4183         int count = 0;
4184         int i, start, end, dbl;
4185         u8 *cea;
4186 
4187         cea = drm_find_cea_extension(edid);
4188         if (!cea) {
4189                 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4190                 return -ENOENT;
4191         }
4192 
4193         if (cea_revision(cea) < 3) {
4194                 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4195                 return -EOPNOTSUPP;
4196         }
4197 
4198         if (cea_db_offsets(cea, &start, &end)) {
4199                 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4200                 return -EPROTO;
4201         }
4202 
4203         for_each_cea_db(cea, i, start, end) {
4204                 u8 *db = &cea[i];
4205 
4206                 if (cea_db_tag(db) == AUDIO_BLOCK) {
4207                         int j;
4208                         dbl = cea_db_payload_len(db);
4209 
4210                         count = dbl / 3; /* SAD is 3B */
4211                         *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4212                         if (!*sads)
4213                                 return -ENOMEM;
4214                         for (j = 0; j < count; j++) {
4215                                 u8 *sad = &db[1 + j * 3];
4216 
4217                                 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4218                                 (*sads)[j].channels = sad[0] & 0x7;
4219                                 (*sads)[j].freq = sad[1] & 0x7F;
4220                                 (*sads)[j].byte2 = sad[2];
4221                         }
4222                         break;
4223                 }
4224         }
4225 
4226         return count;
4227 }
4228 EXPORT_SYMBOL(drm_edid_to_sad);
4229 
4230 /**
4231  * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4232  * @edid: EDID to parse
4233  * @sadb: pointer to the speaker block
4234  *
4235  * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4236  *
4237  * Note: The returned pointer needs to be freed using kfree().
4238  *
4239  * Return: The number of found Speaker Allocation Blocks or negative number on
4240  * error.
4241  */
4242 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4243 {
4244         int count = 0;
4245         int i, start, end, dbl;
4246         const u8 *cea;
4247 
4248         cea = drm_find_cea_extension(edid);
4249         if (!cea) {
4250                 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4251                 return -ENOENT;
4252         }
4253 
4254         if (cea_revision(cea) < 3) {
4255                 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4256                 return -EOPNOTSUPP;
4257         }
4258 
4259         if (cea_db_offsets(cea, &start, &end)) {
4260                 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4261                 return -EPROTO;
4262         }
4263 
4264         for_each_cea_db(cea, i, start, end) {
4265                 const u8 *db = &cea[i];
4266 
4267                 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4268                         dbl = cea_db_payload_len(db);
4269 
4270                         /* Speaker Allocation Data Block */
4271                         if (dbl == 3) {
4272                                 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4273                                 if (!*sadb)
4274                                         return -ENOMEM;
4275                                 count = dbl;
4276                                 break;
4277                         }
4278                 }
4279         }
4280 
4281         return count;
4282 }
4283 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4284 
4285 /**
4286  * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4287  * @connector: connector associated with the HDMI/DP sink
4288  * @mode: the display mode
4289  *
4290  * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4291  * the sink doesn't support audio or video.
4292  */
4293 int drm_av_sync_delay(struct drm_connector *connector,
4294                       const struct drm_display_mode *mode)
4295 {
4296         int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4297         int a, v;
4298 
4299         if (!connector->latency_present[0])
4300                 return 0;
4301         if (!connector->latency_present[1])
4302                 i = 0;
4303 
4304         a = connector->audio_latency[i];
4305         v = connector->video_latency[i];
4306 
4307         /*
4308          * HDMI/DP sink doesn't support audio or video?
4309          */
4310         if (a == 255 || v == 255)
4311                 return 0;
4312 
4313         /*
4314          * Convert raw EDID values to millisecond.
4315          * Treat unknown latency as 0ms.
4316          */
4317         if (a)
4318                 a = min(2 * (a - 1), 500);
4319         if (v)
4320                 v = min(2 * (v - 1), 500);
4321 
4322         return max(v - a, 0);
4323 }
4324 EXPORT_SYMBOL(drm_av_sync_delay);
4325 
4326 /**
4327  * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4328  * @edid: monitor EDID information
4329  *
4330  * Parse the CEA extension according to CEA-861-B.
4331  *
4332  * Return: True if the monitor is HDMI, false if not or unknown.
4333  */
4334 bool drm_detect_hdmi_monitor(struct edid *edid)
4335 {
4336         u8 *edid_ext;
4337         int i;
4338         int start_offset, end_offset;
4339 
4340         edid_ext = drm_find_cea_extension(edid);
4341         if (!edid_ext)
4342                 return false;
4343 
4344         if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4345                 return false;
4346 
4347         /*
4348          * Because HDMI identifier is in Vendor Specific Block,
4349          * search it from all data blocks of CEA extension.
4350          */
4351         for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4352                 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4353                         return true;
4354         }
4355 
4356         return false;
4357 }
4358 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4359 
4360 /**
4361  * drm_detect_monitor_audio - check monitor audio capability
4362  * @edid: EDID block to scan
4363  *
4364  * Monitor should have CEA extension block.
4365  * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4366  * audio' only. If there is any audio extension block and supported
4367  * audio format, assume at least 'basic audio' support, even if 'basic
4368  * audio' is not defined in EDID.
4369  *
4370  * Return: True if the monitor supports audio, false otherwise.
4371  */
4372 bool drm_detect_monitor_audio(struct edid *edid)
4373 {
4374         u8 *edid_ext;
4375         int i, j;
4376         bool has_audio = false;
4377         int start_offset, end_offset;
4378 
4379         edid_ext = drm_find_cea_extension(edid);
4380         if (!edid_ext)
4381                 goto end;
4382 
4383         has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4384 
4385         if (has_audio) {
4386                 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4387                 goto end;
4388         }
4389 
4390         if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4391                 goto end;
4392 
4393         for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4394                 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4395                         has_audio = true;
4396                         for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4397                                 DRM_DEBUG_KMS("CEA audio format %d\n",
4398                                               (edid_ext[i + j] >> 3) & 0xf);
4399                         goto end;
4400                 }
4401         }
4402 end:
4403         return has_audio;
4404 }
4405 EXPORT_SYMBOL(drm_detect_monitor_audio);
4406 
4407 
4408 /**
4409  * drm_default_rgb_quant_range - default RGB quantization range
4410  * @mode: display mode
4411  *
4412  * Determine the default RGB quantization range for the mode,
4413  * as specified in CEA-861.
4414  *
4415  * Return: The default RGB quantization range for the mode
4416  */
4417 enum hdmi_quantization_range
4418 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4419 {
4420         /* All CEA modes other than VIC 1 use limited quantization range. */
4421         return drm_match_cea_mode(mode) > 1 ?
4422                 HDMI_QUANTIZATION_RANGE_LIMITED :
4423                 HDMI_QUANTIZATION_RANGE_FULL;
4424 }
4425 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4426 
4427 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4428 {
4429         struct drm_display_info *info = &connector->display_info;
4430 
4431         DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4432 
4433         if (db[2] & EDID_CEA_VCDB_QS)
4434                 info->rgb_quant_range_selectable = true;
4435 }
4436 
4437 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4438                                                const u8 *db)
4439 {
4440         u8 dc_mask;
4441         struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4442 
4443         dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4444         hdmi->y420_dc_modes = dc_mask;
4445 }
4446 
4447 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4448                                  const u8 *hf_vsdb)
4449 {
4450         struct drm_display_info *display = &connector->display_info;
4451         struct drm_hdmi_info *hdmi = &display->hdmi;
4452 
4453         display->has_hdmi_infoframe = true;
4454 
4455         if (hf_vsdb[6] & 0x80) {
4456                 hdmi->scdc.supported = true;
4457                 if (hf_vsdb[6] & 0x40)
4458                         hdmi->scdc.read_request = true;
4459         }
4460 
4461         /*
4462          * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4463          * And as per the spec, three factors confirm this:
4464          * * Availability of a HF-VSDB block in EDID (check)
4465          * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4466          * * SCDC support available (let's check)
4467          * Lets check it out.
4468          */
4469 
4470         if (hf_vsdb[5]) {
4471                 /* max clock is 5000 KHz times block value */
4472                 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4473                 struct drm_scdc *scdc = &hdmi->scdc;
4474 
4475                 if (max_tmds_clock > 340000) {
4476                         display->max_tmds_clock = max_tmds_clock;
4477                         DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4478                                 display->max_tmds_clock);
4479                 }
4480 
4481                 if (scdc->supported) {
4482                         scdc->scrambling.supported = true;
4483 
4484                         /* Few sinks support scrambling for cloks < 340M */
4485                         if ((hf_vsdb[6] & 0x8))
4486                                 scdc->scrambling.low_rates = true;
4487                 }
4488         }
4489 
4490         drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4491 }
4492 
4493 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4494                                            const u8 *hdmi)
4495 {
4496         struct drm_display_info *info = &connector->display_info;
4497         unsigned int dc_bpc = 0;
4498 
4499         /* HDMI supports at least 8 bpc */
4500         info->bpc = 8;
4501 
4502         if (cea_db_payload_len(hdmi) < 6)
4503                 return;
4504 
4505         if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4506                 dc_bpc = 10;
4507                 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4508                 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4509                           connector->name);
4510         }
4511 
4512         if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4513                 dc_bpc = 12;
4514                 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4515                 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4516                           connector->name);
4517         }
4518 
4519         if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4520                 dc_bpc = 16;
4521                 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4522                 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4523                           connector->name);
4524         }
4525 
4526         if (dc_bpc == 0) {
4527                 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4528                           connector->name);
4529                 return;
4530         }
4531 
4532         DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4533                   connector->name, dc_bpc);
4534         info->bpc = dc_bpc;
4535 
4536         /*
4537          * Deep color support mandates RGB444 support for all video
4538          * modes and forbids YCRCB422 support for all video modes per
4539          * HDMI 1.3 spec.
4540          */
4541         info->color_formats = DRM_COLOR_FORMAT_RGB444;
4542 
4543         /* YCRCB444 is optional according to spec. */
4544         if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4545                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4546                 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4547                           connector->name);
4548         }
4549 
4550         /*
4551          * Spec says that if any deep color mode is supported at all,
4552          * then deep color 36 bit must be supported.
4553          */
4554         if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4555                 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4556                           connector->name);
4557         }
4558 }
4559 
4560 static void
4561 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4562 {
4563         struct drm_display_info *info = &connector->display_info;
4564         u8 len = cea_db_payload_len(db);
4565 
4566         if (len >= 6)
4567                 info->dvi_dual = db[6] & 1;
4568         if (len >= 7)
4569                 info->max_tmds_clock = db[7] * 5000;
4570 
4571         DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4572                       "max TMDS clock %d kHz\n",
4573                       info->dvi_dual,
4574                       info->max_tmds_clock);
4575 
4576         drm_parse_hdmi_deep_color_info(connector, db);
4577 }
4578 
4579 static void drm_parse_cea_ext(struct drm_connector *connector,
4580                               const struct edid *edid)
4581 {
4582         struct drm_display_info *info = &connector->display_info;
4583         const u8 *edid_ext;
4584         int i, start, end;
4585 
4586         edid_ext = drm_find_cea_extension(edid);
4587         if (!edid_ext)
4588                 return;
4589 
4590         info->cea_rev = edid_ext[1];
4591 
4592         /* The existence of a CEA block should imply RGB support */
4593         info->color_formats = DRM_COLOR_FORMAT_RGB444;
4594         if (edid_ext[3] & EDID_CEA_YCRCB444)
4595                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4596         if (edid_ext[3] & EDID_CEA_YCRCB422)
4597                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4598 
4599         if (cea_db_offsets(edid_ext, &start, &end))
4600                 return;
4601 
4602         for_each_cea_db(edid_ext, i, start, end) {
4603                 const u8 *db = &edid_ext[i];
4604 
4605                 if (cea_db_is_hdmi_vsdb(db))
4606                         drm_parse_hdmi_vsdb_video(connector, db);
4607                 if (cea_db_is_hdmi_forum_vsdb(db))
4608                         drm_parse_hdmi_forum_vsdb(connector, db);
4609                 if (cea_db_is_y420cmdb(db))
4610                         drm_parse_y420cmdb_bitmap(connector, db);
4611                 if (cea_db_is_vcdb(db))
4612                         drm_parse_vcdb(connector, db);
4613                 if (cea_db_is_hdmi_hdr_metadata_block(db))
4614                         drm_parse_hdr_metadata_block(connector, db);
4615         }
4616 }
4617 
4618 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4619  * all of the values which would have been set from EDID
4620  */
4621 void
4622 drm_reset_display_info(struct drm_connector *connector)
4623 {
4624         struct drm_display_info *info = &connector->display_info;
4625 
4626         info->width_mm = 0;
4627         info->height_mm = 0;
4628 
4629         info->bpc = 0;
4630         info->color_formats = 0;
4631         info->cea_rev = 0;
4632         info->max_tmds_clock = 0;
4633         info->dvi_dual = false;
4634         info->has_hdmi_infoframe = false;
4635         info->rgb_quant_range_selectable = false;
4636         memset(&info->hdmi, 0, sizeof(info->hdmi));
4637 
4638         info->non_desktop = 0;
4639 }
4640 
4641 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4642 {
4643         struct drm_display_info *info = &connector->display_info;
4644 
4645         u32 quirks = edid_get_quirks(edid);
4646 
4647         drm_reset_display_info(connector);
4648 
4649         info->width_mm = edid->width_cm * 10;
4650         info->height_mm = edid->height_cm * 10;
4651 
4652         info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4653 
4654         DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4655 
4656         if (edid->revision < 3)
4657                 return quirks;
4658 
4659         if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4660                 return quirks;
4661 
4662         drm_parse_cea_ext(connector, edid);
4663 
4664         /*
4665          * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4666          *
4667          * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4668          * tells us to assume 8 bpc color depth if the EDID doesn't have
4669          * extensions which tell otherwise.
4670          */
4671         if (info->bpc == 0 && edid->revision == 3 &&
4672             edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4673                 info->bpc = 8;
4674                 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4675                           connector->name, info->bpc);
4676         }
4677 
4678         /* Only defined for 1.4 with digital displays */
4679         if (edid->revision < 4)
4680                 return quirks;
4681 
4682         switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4683         case DRM_EDID_DIGITAL_DEPTH_6:
4684                 info->bpc = 6;
4685                 break;
4686         case DRM_EDID_DIGITAL_DEPTH_8:
4687                 info->bpc = 8;
4688                 break;
4689         case DRM_EDID_DIGITAL_DEPTH_10:
4690                 info->bpc = 10;
4691                 break;
4692         case DRM_EDID_DIGITAL_DEPTH_12:
4693                 info->bpc = 12;
4694                 break;
4695         case DRM_EDID_DIGITAL_DEPTH_14:
4696                 info->bpc = 14;
4697                 break;
4698         case DRM_EDID_DIGITAL_DEPTH_16:
4699                 info->bpc = 16;
4700                 break;
4701         case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4702         default:
4703                 info->bpc = 0;
4704                 break;
4705         }
4706 
4707         DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4708                           connector->name, info->bpc);
4709 
4710         info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4711         if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4712                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4713         if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4714                 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4715         return quirks;
4716 }
4717 
4718 static int validate_displayid(u8 *displayid, int length, int idx)
4719 {
4720         int i;
4721         u8 csum = 0;
4722         struct displayid_hdr *base;
4723 
4724         base = (struct displayid_hdr *)&displayid[idx];
4725 
4726         DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4727                       base->rev, base->bytes, base->prod_id, base->ext_count);
4728 
4729         if (base->bytes + 5 > length - idx)
4730                 return -EINVAL;
4731         for (i = idx; i <= base->bytes + 5; i++) {
4732                 csum += displayid[i];
4733         }
4734         if (csum) {
4735                 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4736                 return -EINVAL;
4737         }
4738         return 0;
4739 }
4740 
4741 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4742                                                             struct displayid_detailed_timings_1 *timings)
4743 {
4744         struct drm_display_mode *mode;
4745         unsigned pixel_clock = (timings->pixel_clock[0] |
4746                                 (timings->pixel_clock[1] << 8) |
4747                                 (timings->pixel_clock[2] << 16)) + 1;
4748         unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4749         unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4750         unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4751         unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4752         unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4753         unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4754         unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4755         unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4756         bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4757         bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4758         mode = drm_mode_create(dev);
4759         if (!mode)
4760                 return NULL;
4761 
4762         mode->clock = pixel_clock * 10;
4763         mode->hdisplay = hactive;
4764         mode->hsync_start = mode->hdisplay + hsync;
4765         mode->hsync_end = mode->hsync_start + hsync_width;
4766         mode->htotal = mode->hdisplay + hblank;
4767 
4768         mode->vdisplay = vactive;
4769         mode->vsync_start = mode->vdisplay + vsync;
4770         mode->vsync_end = mode->vsync_start + vsync_width;
4771         mode->vtotal = mode->vdisplay + vblank;
4772 
4773         mode->flags = 0;
4774         mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4775         mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4776         mode->type = DRM_MODE_TYPE_DRIVER;
4777 
4778         if (timings->flags & 0x80)
4779                 mode->type |= DRM_MODE_TYPE_PREFERRED;
4780         mode->vrefresh = drm_mode_vrefresh(mode);
4781         drm_mode_set_name(mode);
4782 
4783         return mode;
4784 }
4785 
4786 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4787                                           struct displayid_block *block)
4788 {
4789         struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4790         int i;
4791         int num_timings;
4792         struct drm_display_mode *newmode;
4793         int num_modes = 0;
4794         /* blocks must be multiple of 20 bytes length */
4795         if (block->num_bytes % 20)
4796                 return 0;
4797 
4798         num_timings = block->num_bytes / 20;
4799         for (i = 0; i < num_timings; i++) {
4800                 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4801 
4802                 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4803                 if (!newmode)
4804                         continue;
4805 
4806                 drm_mode_probed_add(connector, newmode);
4807                 num_modes++;
4808         }
4809         return num_modes;
4810 }
4811 
4812 static int add_displayid_detailed_modes(struct drm_connector *connector,
4813                                         struct edid *edid)
4814 {
4815         u8 *displayid;
4816         int ret;
4817         int idx = 1;
4818         int length = EDID_LENGTH;
4819         struct displayid_block *block;
4820         int num_modes = 0;
4821 
4822         displayid = drm_find_displayid_extension(edid);
4823         if (!displayid)
4824                 return 0;
4825 
4826         ret = validate_displayid(displayid, length, idx);
4827         if (ret)
4828                 return 0;
4829 
4830         idx += sizeof(struct displayid_hdr);
4831         for_each_displayid_db(displayid, block, idx, length) {
4832                 switch (block->tag) {
4833                 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4834                         num_modes += add_displayid_detailed_1_modes(connector, block);
4835                         break;
4836                 }
4837         }
4838         return num_modes;
4839 }
4840 
4841 /**
4842  * drm_add_edid_modes - add modes from EDID data, if available
4843  * @connector: connector we're probing
4844  * @edid: EDID data
4845  *
4846  * Add the specified modes to the connector's mode list. Also fills out the
4847  * &drm_display_info structure and ELD in @connector with any information which
4848  * can be derived from the edid.
4849  *
4850  * Return: The number of modes added or 0 if we couldn't find any.
4851  */
4852 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4853 {
4854         int num_modes = 0;
4855         u32 quirks;
4856 
4857         if (edid == NULL) {
4858                 clear_eld(connector);
4859                 return 0;
4860         }
4861         if (!drm_edid_is_valid(edid)) {
4862                 clear_eld(connector);
4863                 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4864                          connector->name);
4865                 return 0;
4866         }
4867 
4868         drm_edid_to_eld(connector, edid);
4869 
4870         /*
4871          * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4872          * To avoid multiple parsing of same block, lets parse that map
4873          * from sink info, before parsing CEA modes.
4874          */
4875         quirks = drm_add_display_info(connector, edid);
4876 
4877         /*
4878          * EDID spec says modes should be preferred in this order:
4879          * - preferred detailed mode
4880          * - other detailed modes from base block
4881          * - detailed modes from extension blocks
4882          * - CVT 3-byte code modes
4883          * - standard timing codes
4884          * - established timing codes
4885          * - modes inferred from GTF or CVT range information
4886          *
4887          * We get this pretty much right.
4888          *
4889          * XXX order for additional mode types in extension blocks?
4890          */
4891         num_modes += add_detailed_modes(connector, edid, quirks);
4892         num_modes += add_cvt_modes(connector, edid);
4893         num_modes += add_standard_modes(connector, edid);
4894         num_modes += add_established_modes(connector, edid);
4895         num_modes += add_cea_modes(connector, edid);
4896         num_modes += add_alternate_cea_modes(connector, edid);
4897         num_modes += add_displayid_detailed_modes(connector, edid);
4898         if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4899                 num_modes += add_inferred_modes(connector, edid);
4900 
4901         if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4902                 edid_fixup_preferred(connector, quirks);
4903 
4904         if (quirks & EDID_QUIRK_FORCE_6BPC)
4905                 connector->display_info.bpc = 6;
4906 
4907         if (quirks & EDID_QUIRK_FORCE_8BPC)
4908                 connector->display_info.bpc = 8;
4909 
4910         if (quirks & EDID_QUIRK_FORCE_10BPC)
4911                 connector->display_info.bpc = 10;
4912 
4913         if (quirks & EDID_QUIRK_FORCE_12BPC)
4914                 connector->display_info.bpc = 12;
4915 
4916         return num_modes;
4917 }
4918 EXPORT_SYMBOL(drm_add_edid_modes);
4919 
4920 /**
4921  * drm_add_modes_noedid - add modes for the connectors without EDID
4922  * @connector: connector we're probing
4923  * @hdisplay: the horizontal display limit
4924  * @vdisplay: the vertical display limit
4925  *
4926  * Add the specified modes to the connector's mode list. Only when the
4927  * hdisplay/vdisplay is not beyond the given limit, it will be added.
4928  *
4929  * Return: The number of modes added or 0 if we couldn't find any.
4930  */
4931 int drm_add_modes_noedid(struct drm_connector *connector,
4932                         int hdisplay, int vdisplay)
4933 {
4934         int i, count, num_modes = 0;
4935         struct drm_display_mode *mode;
4936         struct drm_device *dev = connector->dev;
4937 
4938         count = ARRAY_SIZE(drm_dmt_modes);
4939         if (hdisplay < 0)
4940                 hdisplay = 0;
4941         if (vdisplay < 0)
4942                 vdisplay = 0;
4943 
4944         for (i = 0; i < count; i++) {
4945                 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4946                 if (hdisplay && vdisplay) {
4947                         /*
4948                          * Only when two are valid, they will be used to check
4949                          * whether the mode should be added to the mode list of
4950                          * the connector.
4951                          */
4952                         if (ptr->hdisplay > hdisplay ||
4953                                         ptr->vdisplay > vdisplay)
4954                                 continue;
4955                 }
4956                 if (drm_mode_vrefresh(ptr) > 61)
4957                         continue;
4958                 mode = drm_mode_duplicate(dev, ptr);
4959                 if (mode) {
4960                         drm_mode_probed_add(connector, mode);
4961                         num_modes++;
4962                 }
4963         }
4964         return num_modes;
4965 }
4966 EXPORT_SYMBOL(drm_add_modes_noedid);
4967 
4968 /**
4969  * drm_set_preferred_mode - Sets the preferred mode of a connector
4970  * @connector: connector whose mode list should be processed
4971  * @hpref: horizontal resolution of preferred mode
4972  * @vpref: vertical resolution of preferred mode
4973  *
4974  * Marks a mode as preferred if it matches the resolution specified by @hpref
4975  * and @vpref.
4976  */
4977 void drm_set_preferred_mode(struct drm_connector *connector,
4978                            int hpref, int vpref)
4979 {
4980         struct drm_display_mode *mode;
4981 
4982         list_for_each_entry(mode, &connector->probed_modes, head) {
4983                 if (mode->hdisplay == hpref &&
4984                     mode->vdisplay == vpref)
4985                         mode->type |= DRM_MODE_TYPE_PREFERRED;
4986         }
4987 }
4988 EXPORT_SYMBOL(drm_set_preferred_mode);
4989 
4990 static bool is_hdmi2_sink(struct drm_connector *connector)
4991 {
4992         /*
4993          * FIXME: sil-sii8620 doesn't have a connector around when
4994          * we need one, so we have to be prepared for a NULL connector.
4995          */
4996         if (!connector)
4997                 return true;
4998 
4999         return connector->display_info.hdmi.scdc.supported ||
5000                 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5001 }
5002 
5003 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5004 {
5005         return sink_eotf & BIT(output_eotf);
5006 }
5007 
5008 /**
5009  * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5010  *                                         HDR metadata from userspace
5011  * @frame: HDMI DRM infoframe
5012  * @conn_state: Connector state containing HDR metadata
5013  *
5014  * Return: 0 on success or a negative error code on failure.
5015  */
5016 int
5017 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5018                                     const struct drm_connector_state *conn_state)
5019 {
5020         struct drm_connector *connector;
5021         struct hdr_output_metadata *hdr_metadata;
5022         int err;
5023 
5024         if (!frame || !conn_state)
5025                 return -EINVAL;
5026 
5027         connector = conn_state->connector;
5028 
5029         if (!conn_state->hdr_output_metadata)
5030                 return -EINVAL;
5031 
5032         hdr_metadata = conn_state->hdr_output_metadata->data;
5033 
5034         if (!hdr_metadata || !connector)
5035                 return -EINVAL;
5036 
5037         /* Sink EOTF is Bit map while infoframe is absolute values */
5038         if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5039             connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5040                 DRM_DEBUG_KMS("EOTF Not Supported\n");
5041                 return -EINVAL;
5042         }
5043 
5044         err = hdmi_drm_infoframe_init(frame);
5045         if (err < 0)
5046                 return err;
5047 
5048         frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5049         frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5050 
5051         BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5052                      sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5053         BUILD_BUG_ON(sizeof(frame->white_point) !=
5054                      sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5055 
5056         memcpy(&frame->display_primaries,
5057                &hdr_metadata->hdmi_metadata_type1.display_primaries,
5058                sizeof(frame->display_primaries));
5059 
5060         memcpy(&frame->white_point,
5061                &hdr_metadata->hdmi_metadata_type1.white_point,
5062                sizeof(frame->white_point));
5063 
5064         frame->max_display_mastering_luminance =
5065                 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5066         frame->min_display_mastering_luminance =
5067                 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5068         frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5069         frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5070 
5071         return 0;
5072 }
5073 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5074 
5075 /**
5076  * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5077  *                                              data from a DRM display mode
5078  * @frame: HDMI AVI infoframe
5079  * @connector: the connector
5080  * @mode: DRM display mode
5081  *
5082  * Return: 0 on success or a negative error code on failure.
5083  */
5084 int
5085 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5086                                          struct drm_connector *connector,
5087                                          const struct drm_display_mode *mode)
5088 {
5089         enum hdmi_picture_aspect picture_aspect;
5090         int err;
5091 
5092         if (!frame || !mode)
5093                 return -EINVAL;
5094 
5095         err = hdmi_avi_infoframe_init(frame);
5096         if (err < 0)
5097                 return err;
5098 
5099         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5100                 frame->pixel_repeat = 1;
5101 
5102         frame->video_code = drm_match_cea_mode(mode);
5103 
5104         /*
5105          * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5106          * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5107          * have to make sure we dont break HDMI 1.4 sinks.
5108          */
5109         if (!is_hdmi2_sink(connector) && frame->video_code > 64)
5110                 frame->video_code = 0;
5111 
5112         /*
5113          * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5114          * we should send its VIC in vendor infoframes, else send the
5115          * VIC in AVI infoframes. Lets check if this mode is present in
5116          * HDMI 1.4b 4K modes
5117          */
5118         if (frame->video_code) {
5119                 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
5120                 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
5121 
5122                 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
5123                         frame->video_code = 0;
5124         }
5125 
5126         frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5127 
5128         /*
5129          * As some drivers don't support atomic, we can't use connector state.
5130          * So just initialize the frame with default values, just the same way
5131          * as it's done with other properties here.
5132          */
5133         frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5134         frame->itc = 0;
5135 
5136         /*
5137          * Populate picture aspect ratio from either
5138          * user input (if specified) or from the CEA mode list.
5139          */
5140         picture_aspect = mode->picture_aspect_ratio;
5141         if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
5142                 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
5143 
5144         /*
5145          * The infoframe can't convey anything but none, 4:3
5146          * and 16:9, so if the user has asked for anything else
5147          * we can only satisfy it by specifying the right VIC.
5148          */
5149         if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5150                 if (picture_aspect !=
5151                     drm_get_cea_aspect_ratio(frame->video_code))
5152                         return -EINVAL;
5153                 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5154         }
5155 
5156         frame->picture_aspect = picture_aspect;
5157         frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5158         frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5159 
5160         return 0;
5161 }
5162 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5163 
5164 /* HDMI Colorspace Spec Definitions */
5165 #define FULL_COLORIMETRY_MASK           0x1FF
5166 #define NORMAL_COLORIMETRY_MASK         0x3
5167 #define EXTENDED_COLORIMETRY_MASK       0x7
5168 #define EXTENDED_ACE_COLORIMETRY_MASK   0xF
5169 
5170 #define C(x) ((x) << 0)
5171 #define EC(x) ((x) << 2)
5172 #define ACE(x) ((x) << 5)
5173 
5174 #define HDMI_COLORIMETRY_NO_DATA                0x0
5175 #define HDMI_COLORIMETRY_SMPTE_170M_YCC         (C(1) | EC(0) | ACE(0))
5176 #define HDMI_COLORIMETRY_BT709_YCC              (C(2) | EC(0) | ACE(0))
5177 #define HDMI_COLORIMETRY_XVYCC_601              (C(3) | EC(0) | ACE(0))
5178 #define HDMI_COLORIMETRY_XVYCC_709              (C(3) | EC(1) | ACE(0))
5179 #define HDMI_COLORIMETRY_SYCC_601               (C(3) | EC(2) | ACE(0))
5180 #define HDMI_COLORIMETRY_OPYCC_601              (C(3) | EC(3) | ACE(0))
5181 #define HDMI_COLORIMETRY_OPRGB                  (C(3) | EC(4) | ACE(0))
5182 #define HDMI_COLORIMETRY_BT2020_CYCC            (C(3) | EC(5) | ACE(0))
5183 #define HDMI_COLORIMETRY_BT2020_RGB             (C(3) | EC(6) | ACE(0))
5184 #define HDMI_COLORIMETRY_BT2020_YCC             (C(3) | EC(6) | ACE(0))
5185 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65         (C(3) | EC(7) | ACE(0))
5186 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER     (C(3) | EC(7) | ACE(1))
5187 
5188 static const u32 hdmi_colorimetry_val[] = {
5189         [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5190         [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5191         [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5192         [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5193         [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5194         [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5195         [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5196         [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5197         [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5198         [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5199         [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5200 };
5201 
5202 #undef C
5203 #undef EC
5204 #undef ACE
5205 
5206 /**
5207  * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5208  *                                       colorspace information
5209  * @frame: HDMI AVI infoframe
5210  * @conn_state: connector state
5211  */
5212 void
5213 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5214                                   const struct drm_connector_state *conn_state)
5215 {
5216         u32 colorimetry_val;
5217         u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5218 
5219         if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5220                 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5221         else
5222                 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5223 
5224         frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5225         /*
5226          * ToDo: Extend it for ACE formats as well. Modify the infoframe
5227          * structure and extend it in drivers/video/hdmi
5228          */
5229         frame->extended_colorimetry = (colorimetry_val >> 2) &
5230                                         EXTENDED_COLORIMETRY_MASK;
5231 }
5232 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5233 
5234 /**
5235  * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5236  *                                        quantization range information
5237  * @frame: HDMI AVI infoframe
5238  * @connector: the connector
5239  * @mode: DRM display mode
5240  * @rgb_quant_range: RGB quantization range (Q)
5241  */
5242 void
5243 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5244                                    struct drm_connector *connector,
5245                                    const struct drm_display_mode *mode,
5246                                    enum hdmi_quantization_range rgb_quant_range)
5247 {
5248         const struct drm_display_info *info = &connector->display_info;
5249 
5250         /*
5251          * CEA-861:
5252          * "A Source shall not send a non-zero Q value that does not correspond
5253          *  to the default RGB Quantization Range for the transmitted Picture
5254          *  unless the Sink indicates support for the Q bit in a Video
5255          *  Capabilities Data Block."
5256          *
5257          * HDMI 2.0 recommends sending non-zero Q when it does match the
5258          * default RGB quantization range for the mode, even when QS=0.
5259          */
5260         if (info->rgb_quant_range_selectable ||
5261             rgb_quant_range == drm_default_rgb_quant_range(mode))
5262                 frame->quantization_range = rgb_quant_range;
5263         else
5264                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5265 
5266         /*
5267          * CEA-861-F:
5268          * "When transmitting any RGB colorimetry, the Source should set the
5269          *  YQ-field to match the RGB Quantization Range being transmitted
5270          *  (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5271          *  set YQ=1) and the Sink shall ignore the YQ-field."
5272          *
5273          * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5274          * by non-zero YQ when receiving RGB. There doesn't seem to be any
5275          * good way to tell which version of CEA-861 the sink supports, so
5276          * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5277          * on on CEA-861-F.
5278          */
5279         if (!is_hdmi2_sink(connector) ||
5280             rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5281                 frame->ycc_quantization_range =
5282                         HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5283         else
5284                 frame->ycc_quantization_range =
5285                         HDMI_YCC_QUANTIZATION_RANGE_FULL;
5286 }
5287 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5288 
5289 static enum hdmi_3d_structure
5290 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5291 {
5292         u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5293 
5294         switch (layout) {
5295         case DRM_MODE_FLAG_3D_FRAME_PACKING:
5296                 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5297         case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5298                 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5299         case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5300                 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5301         case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5302                 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5303         case DRM_MODE_FLAG_3D_L_DEPTH:
5304                 return HDMI_3D_STRUCTURE_L_DEPTH;
5305         case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5306                 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5307         case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5308                 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5309         case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5310                 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5311         default:
5312                 return HDMI_3D_STRUCTURE_INVALID;
5313         }
5314 }
5315 
5316 /**
5317  * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5318  * data from a DRM display mode
5319  * @frame: HDMI vendor infoframe
5320  * @connector: the connector
5321  * @mode: DRM display mode
5322  *
5323  * Note that there's is a need to send HDMI vendor infoframes only when using a
5324  * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5325  * function will return -EINVAL, error that can be safely ignored.
5326  *
5327  * Return: 0 on success or a negative error code on failure.
5328  */
5329 int
5330 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5331                                             struct drm_connector *connector,
5332                                             const struct drm_display_mode *mode)
5333 {
5334         /*
5335          * FIXME: sil-sii8620 doesn't have a connector around when
5336          * we need one, so we have to be prepared for a NULL connector.
5337          */
5338         bool has_hdmi_infoframe = connector ?
5339                 connector->display_info.has_hdmi_infoframe : false;
5340         int err;
5341         u32 s3d_flags;
5342         u8 vic;
5343 
5344         if (!frame || !mode)
5345                 return -EINVAL;
5346 
5347         if (!has_hdmi_infoframe)
5348                 return -EINVAL;
5349 
5350         vic = drm_match_hdmi_mode(mode);
5351         s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5352 
5353         /*
5354          * Even if it's not absolutely necessary to send the infoframe
5355          * (ie.vic==0 and s3d_struct==0) we will still send it if we
5356          * know that the sink can handle it. This is based on a
5357          * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5358          * have trouble realizing that they shuld switch from 3D to 2D
5359          * mode if the source simply stops sending the infoframe when
5360          * it wants to switch from 3D to 2D.
5361          */
5362 
5363         if (vic && s3d_flags)
5364                 return -EINVAL;
5365 
5366         err = hdmi_vendor_infoframe_init(frame);
5367         if (err < 0)
5368                 return err;
5369 
5370         frame->vic = vic;
5371         frame->s3d_struct = s3d_structure_from_display_mode(mode);
5372 
5373         return 0;
5374 }
5375 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5376 
5377 static int drm_parse_tiled_block(struct drm_connector *connector,
5378                                  struct displayid_block *block)
5379 {
5380         struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5381         u16 w, h;
5382         u8 tile_v_loc, tile_h_loc;
5383         u8 num_v_tile, num_h_tile;
5384         struct drm_tile_group *tg;
5385 
5386         w = tile->tile_size[0] | tile->tile_size[1] << 8;
5387         h = tile->tile_size[2] | tile->tile_size[3] << 8;
5388 
5389         num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5390         num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5391         tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5392         tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5393 
5394         connector->has_tile = true;
5395         if (tile->tile_cap & 0x80)
5396                 connector->tile_is_single_monitor = true;
5397 
5398         connector->num_h_tile = num_h_tile + 1;
5399         connector->num_v_tile = num_v_tile + 1;
5400         connector->tile_h_loc = tile_h_loc;
5401         connector->tile_v_loc = tile_v_loc;
5402         connector->tile_h_size = w + 1;
5403         connector->tile_v_size = h + 1;
5404 
5405         DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5406         DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5407         DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5408                       num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5409         DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5410 
5411         tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5412         if (!tg) {
5413                 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5414         }
5415         if (!tg)
5416                 return -ENOMEM;
5417 
5418         if (connector->tile_group != tg) {
5419                 /* if we haven't got a pointer,
5420                    take the reference, drop ref to old tile group */
5421                 if (connector->tile_group) {
5422                         drm_mode_put_tile_group(connector->dev, connector->tile_group);
5423                 }
5424                 connector->tile_group = tg;
5425         } else
5426                 /* if same tile group, then release the ref we just took. */
5427                 drm_mode_put_tile_group(connector->dev, tg);
5428         return 0;
5429 }
5430 
5431 static int drm_parse_display_id(struct drm_connector *connector,
5432                                 u8 *displayid, int length,
5433                                 bool is_edid_extension)
5434 {
5435         /* if this is an EDID extension the first byte will be 0x70 */
5436         int idx = 0;
5437         struct displayid_block *block;
5438         int ret;
5439 
5440         if (is_edid_extension)
5441                 idx = 1;
5442 
5443         ret = validate_displayid(displayid, length, idx);
5444         if (ret)
5445                 return ret;
5446 
5447         idx += sizeof(struct displayid_hdr);
5448         for_each_displayid_db(displayid, block, idx, length) {
5449                 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5450                               block->tag, block->rev, block->num_bytes);
5451 
5452                 switch (block->tag) {
5453                 case DATA_BLOCK_TILED_DISPLAY:
5454                         ret = drm_parse_tiled_block(connector, block);
5455                         if (ret)
5456                                 return ret;
5457                         break;
5458                 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5459                         /* handled in mode gathering code. */
5460                         break;
5461                 case DATA_BLOCK_CTA:
5462                         /* handled in the cea parser code. */
5463                         break;
5464                 default:
5465                         DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5466                         break;
5467                 }
5468         }
5469         return 0;
5470 }
5471 
5472 static void drm_get_displayid(struct drm_connector *connector,
5473                               struct edid *edid)
5474 {
5475         void *displayid = NULL;
5476         int ret;
5477         connector->has_tile = false;
5478         displayid = drm_find_displayid_extension(edid);
5479         if (!displayid) {
5480                 /* drop reference to any tile group we had */
5481                 goto out_drop_ref;
5482         }
5483 
5484         ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5485         if (ret < 0)
5486                 goto out_drop_ref;
5487         if (!connector->has_tile)
5488                 goto out_drop_ref;
5489         return;
5490 out_drop_ref:
5491         if (connector->tile_group) {
5492                 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5493                 connector->tile_group = NULL;
5494         }
5495         return;
5496 }