1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
5 */
6
7 #ifndef _STI_HDMI_H_
8 #define _STI_HDMI_H_
9
10 #include <linux/hdmi.h>
11 #include <linux/platform_device.h>
12
13 #include <media/cec-notifier.h>
14
15 #include <drm/drm_modes.h>
16 #include <drm/drm_property.h>
17
18 #define HDMI_STA 0x0010
19 #define HDMI_STA_DLL_LCK BIT(5)
20 #define HDMI_STA_HOT_PLUG BIT(4)
21
22 struct sti_hdmi;
23
24 struct hdmi_phy_ops {
25 bool (*start)(struct sti_hdmi *hdmi);
26 void (*stop)(struct sti_hdmi *hdmi);
27 };
28
29 struct hdmi_audio_params {
30 bool enabled;
31 unsigned int sample_width;
32 unsigned int sample_rate;
33 struct hdmi_audio_infoframe cea;
34 };
35
36 static const struct drm_prop_enum_list colorspace_mode_names[] = {
37 { HDMI_COLORSPACE_RGB, "rgb" },
38 { HDMI_COLORSPACE_YUV422, "yuv422" },
39 { HDMI_COLORSPACE_YUV444, "yuv444" },
40 };
41
42 #define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB
43
44 /**
45 * STI hdmi structure
46 *
47 * @dev: driver device
48 * @drm_dev: pointer to drm device
49 * @mode: current display mode selected
50 * @regs: hdmi register
51 * @syscfg: syscfg register for pll rejection configuration
52 * @clk_pix: hdmi pixel clock
53 * @clk_tmds: hdmi tmds clock
54 * @clk_phy: hdmi phy clock
55 * @clk_audio: hdmi audio clock
56 * @irq: hdmi interrupt number
57 * @irq_status: interrupt status register
58 * @phy_ops: phy start/stop operations
59 * @enabled: true if hdmi is enabled else false
60 * @hpd: hot plug detect status
61 * @wait_event: wait event
62 * @event_received: wait event status
63 * @reset: reset control of the hdmi phy
64 * @ddc_adapt: i2c ddc adapter
65 * @colorspace: current colorspace selected
66 * @hdmi_monitor: true if HDMI monitor detected else DVI monitor assumed
67 * @audio_pdev: ASoC hdmi-codec platform device
68 * @audio: hdmi audio parameters.
69 * @drm_connector: hdmi connector
70 * @notifier: hotplug detect notifier
71 */
72 struct sti_hdmi {
73 struct device dev;
74 struct drm_device *drm_dev;
75 struct drm_display_mode mode;
76 void __iomem *regs;
77 void __iomem *syscfg;
78 struct clk *clk_pix;
79 struct clk *clk_tmds;
80 struct clk *clk_phy;
81 struct clk *clk_audio;
82 int irq;
83 u32 irq_status;
84 struct hdmi_phy_ops *phy_ops;
85 bool enabled;
86 bool hpd;
87 wait_queue_head_t wait_event;
88 bool event_received;
89 struct reset_control *reset;
90 struct i2c_adapter *ddc_adapt;
91 enum hdmi_colorspace colorspace;
92 bool hdmi_monitor;
93 struct platform_device *audio_pdev;
94 struct hdmi_audio_params audio;
95 struct drm_connector *drm_connector;
96 struct cec_notifier *notifier;
97 };
98
99 u32 hdmi_read(struct sti_hdmi *hdmi, int offset);
100 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset);
101
102 /**
103 * hdmi phy config structure
104 *
105 * A pointer to an array of these structures is passed to a TMDS (HDMI) output
106 * via the control interface to provide board and SoC specific
107 * configurations of the HDMI PHY. Each entry in the array specifies a hardware
108 * specific configuration for a given TMDS clock frequency range.
109 *
110 * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to
111 * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to
112 * @config: SoC specific register configuration
113 */
114 struct hdmi_phy_config {
115 u32 min_tmds_freq;
116 u32 max_tmds_freq;
117 u32 config[4];
118 };
119
120 #endif