drivers/gpu/drm/sti/sti

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This source file includes following definitions.
sti_hqvdp_get_free_cmd
sti_hqvdp_get_curr_cmd
sti_hqvdp_get_next_cmd
hqvdp_dbg_get_lut
hqvdp_dbg_dump_cmd
hqvdp_dbg_show
hqvdp_debugfs_init
sti_hqvdp_update_hvsrc
sti_hqvdp_check_hw_scaling
sti_hqvdp_disable
sti_hqvdp_vtg_cb
sti_hqvdp_init
sti_hqvdp_init_plugs
sti_hqvdp_start_xp70
sti_hqvdp_atomic_check
sti_hqvdp_atomic_update
sti_hqvdp_atomic_disable
sti_hqvdp_destroy
sti_hqvdp_late_register
sti_hqvdp_create
sti_hqvdp_bind
sti_hqvdp_unbind
sti_hqvdp_probe
sti_hqvdp_remove
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2014
   4  * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
   5  */
   6 
   7 #include <linux/component.h>
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/firmware.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/reset.h>
  14 #include <linux/seq_file.h>
  15 
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_device.h>
  18 #include <drm/drm_fb_cma_helper.h>
  19 #include <drm/drm_fourcc.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 
  22 #include "sti_compositor.h"
  23 #include "sti_drv.h"
  24 #include "sti_hqvdp_lut.h"
  25 #include "sti_plane.h"
  26 #include "sti_vtg.h"
  27 
  28 /* Firmware name */
  29 #define HQVDP_FMW_NAME          "hqvdp-stih407.bin"
  30 
  31 /* Regs address */
  32 #define HQVDP_DMEM              0x00000000               /* 0x00000000 */
  33 #define HQVDP_PMEM              0x00040000               /* 0x00040000 */
  34 #define HQVDP_RD_PLUG           0x000E0000               /* 0x000E0000 */
  35 #define HQVDP_RD_PLUG_CONTROL   (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */
  36 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */
  37 #define HQVDP_RD_PLUG_MIN_OPC   (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */
  38 #define HQVDP_RD_PLUG_MAX_OPC   (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */
  39 #define HQVDP_RD_PLUG_MAX_CHK   (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */
  40 #define HQVDP_RD_PLUG_MAX_MSG   (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */
  41 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */
  42 #define HQVDP_WR_PLUG           0x000E2000               /* 0x000E2000 */
  43 #define HQVDP_WR_PLUG_CONTROL   (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */
  44 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */
  45 #define HQVDP_WR_PLUG_MIN_OPC   (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */
  46 #define HQVDP_WR_PLUG_MAX_OPC   (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */
  47 #define HQVDP_WR_PLUG_MAX_CHK   (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */
  48 #define HQVDP_WR_PLUG_MAX_MSG   (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */
  49 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */
  50 #define HQVDP_MBX               0x000E4000               /* 0x000E4000 */
  51 #define HQVDP_MBX_IRQ_TO_XP70   (HQVDP_MBX + 0x0000)     /* 0x000E4000 */
  52 #define HQVDP_MBX_INFO_HOST     (HQVDP_MBX + 0x0004)     /* 0x000E4004 */
  53 #define HQVDP_MBX_IRQ_TO_HOST   (HQVDP_MBX + 0x0008)     /* 0x000E4008 */
  54 #define HQVDP_MBX_INFO_XP70     (HQVDP_MBX + 0x000C)     /* 0x000E400C */
  55 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010)     /* 0x000E4010 */
  56 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014)     /* 0x000E4014 */
  57 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018)     /* 0x000E4018 */
  58 #define HQVDP_MBX_GP_STATUS     (HQVDP_MBX + 0x001C)     /* 0x000E401C */
  59 #define HQVDP_MBX_NEXT_CMD      (HQVDP_MBX + 0x0020)     /* 0x000E4020 */
  60 #define HQVDP_MBX_CURRENT_CMD   (HQVDP_MBX + 0x0024)     /* 0x000E4024 */
  61 #define HQVDP_MBX_SOFT_VSYNC    (HQVDP_MBX + 0x0028)     /* 0x000E4028 */
  62 
  63 /* Plugs config */
  64 #define PLUG_CONTROL_ENABLE     0x00000001
  65 #define PLUG_PAGE_SIZE_256      0x00000002
  66 #define PLUG_MIN_OPC_8          0x00000003
  67 #define PLUG_MAX_OPC_64         0x00000006
  68 #define PLUG_MAX_CHK_2X         0x00000001
  69 #define PLUG_MAX_MSG_1X         0x00000000
  70 #define PLUG_MIN_SPACE_1        0x00000000
  71 
  72 /* SW reset CTRL */
  73 #define SW_RESET_CTRL_FULL      BIT(0)
  74 #define SW_RESET_CTRL_CORE      BIT(1)
  75 
  76 /* Startup ctrl 1 */
  77 #define STARTUP_CTRL1_RST_DONE  BIT(0)
  78 #define STARTUP_CTRL1_AUTH_IDLE BIT(2)
  79 
  80 /* Startup ctrl 2 */
  81 #define STARTUP_CTRL2_FETCH_EN  BIT(1)
  82 
  83 /* Info xP70 */
  84 #define INFO_XP70_FW_READY      BIT(15)
  85 #define INFO_XP70_FW_PROCESSING BIT(14)
  86 #define INFO_XP70_FW_INITQUEUES BIT(13)
  87 
  88 /* SOFT_VSYNC */
  89 #define SOFT_VSYNC_HW           0x00000000
  90 #define SOFT_VSYNC_SW_CMD       0x00000001
  91 #define SOFT_VSYNC_SW_CTRL_IRQ  0x00000003
  92 
  93 /* Reset & boot poll config */
  94 #define POLL_MAX_ATTEMPT        50
  95 #define POLL_DELAY_MS           20
  96 
  97 #define SCALE_FACTOR            8192
  98 #define SCALE_MAX_FOR_LEG_LUT_F 4096
  99 #define SCALE_MAX_FOR_LEG_LUT_E 4915
 100 #define SCALE_MAX_FOR_LEG_LUT_D 6654
 101 #define SCALE_MAX_FOR_LEG_LUT_C 8192
 102 
 103 enum sti_hvsrc_orient {
 104         HVSRC_HORI,
 105         HVSRC_VERT
 106 };
 107 
 108 /* Command structures */
 109 struct sti_hqvdp_top {
 110         u32 config;
 111         u32 mem_format;
 112         u32 current_luma;
 113         u32 current_enh_luma;
 114         u32 current_right_luma;
 115         u32 current_enh_right_luma;
 116         u32 current_chroma;
 117         u32 current_enh_chroma;
 118         u32 current_right_chroma;
 119         u32 current_enh_right_chroma;
 120         u32 output_luma;
 121         u32 output_chroma;
 122         u32 luma_src_pitch;
 123         u32 luma_enh_src_pitch;
 124         u32 luma_right_src_pitch;
 125         u32 luma_enh_right_src_pitch;
 126         u32 chroma_src_pitch;
 127         u32 chroma_enh_src_pitch;
 128         u32 chroma_right_src_pitch;
 129         u32 chroma_enh_right_src_pitch;
 130         u32 luma_processed_pitch;
 131         u32 chroma_processed_pitch;
 132         u32 input_frame_size;
 133         u32 input_viewport_ori;
 134         u32 input_viewport_ori_right;
 135         u32 input_viewport_size;
 136         u32 left_view_border_width;
 137         u32 right_view_border_width;
 138         u32 left_view_3d_offset_width;
 139         u32 right_view_3d_offset_width;
 140         u32 side_stripe_color;
 141         u32 crc_reset_ctrl;
 142 };
 143 
 144 /* Configs for interlaced : no IT, no pass thru, 3 fields */
 145 #define TOP_CONFIG_INTER_BTM            0x00000000
 146 #define TOP_CONFIG_INTER_TOP            0x00000002
 147 
 148 /* Config for progressive : no IT, no pass thru, 3 fields */
 149 #define TOP_CONFIG_PROGRESSIVE          0x00000001
 150 
 151 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */
 152 #define TOP_MEM_FORMAT_DFLT             0x00018060
 153 
 154 /* Min/Max size */
 155 #define MAX_WIDTH                       0x1FFF
 156 #define MAX_HEIGHT                      0x0FFF
 157 #define MIN_WIDTH                       0x0030
 158 #define MIN_HEIGHT                      0x0010
 159 
 160 struct sti_hqvdp_vc1re {
 161         u32 ctrl_prv_csdi;
 162         u32 ctrl_cur_csdi;
 163         u32 ctrl_nxt_csdi;
 164         u32 ctrl_cur_fmd;
 165         u32 ctrl_nxt_fmd;
 166 };
 167 
 168 struct sti_hqvdp_fmd {
 169         u32 config;
 170         u32 viewport_ori;
 171         u32 viewport_size;
 172         u32 next_next_luma;
 173         u32 next_next_right_luma;
 174         u32 next_next_next_luma;
 175         u32 next_next_next_right_luma;
 176         u32 threshold_scd;
 177         u32 threshold_rfd;
 178         u32 threshold_move;
 179         u32 threshold_cfd;
 180 };
 181 
 182 struct sti_hqvdp_csdi {
 183         u32 config;
 184         u32 config2;
 185         u32 dcdi_config;
 186         u32 prev_luma;
 187         u32 prev_enh_luma;
 188         u32 prev_right_luma;
 189         u32 prev_enh_right_luma;
 190         u32 next_luma;
 191         u32 next_enh_luma;
 192         u32 next_right_luma;
 193         u32 next_enh_right_luma;
 194         u32 prev_chroma;
 195         u32 prev_enh_chroma;
 196         u32 prev_right_chroma;
 197         u32 prev_enh_right_chroma;
 198         u32 next_chroma;
 199         u32 next_enh_chroma;
 200         u32 next_right_chroma;
 201         u32 next_enh_right_chroma;
 202         u32 prev_motion;
 203         u32 prev_right_motion;
 204         u32 cur_motion;
 205         u32 cur_right_motion;
 206         u32 next_motion;
 207         u32 next_right_motion;
 208 };
 209 
 210 /* Config for progressive: by pass */
 211 #define CSDI_CONFIG_PROG                0x00000000
 212 /* Config for directional deinterlacing without motion */
 213 #define CSDI_CONFIG_INTER_DIR           0x00000016
 214 /* Additional configs for fader, blender, motion,... deinterlace algorithms */
 215 #define CSDI_CONFIG2_DFLT               0x000001B3
 216 #define CSDI_DCDI_CONFIG_DFLT           0x00203803
 217 
 218 struct sti_hqvdp_hvsrc {
 219         u32 hor_panoramic_ctrl;
 220         u32 output_picture_size;
 221         u32 init_horizontal;
 222         u32 init_vertical;
 223         u32 param_ctrl;
 224         u32 yh_coef[NB_COEF];
 225         u32 ch_coef[NB_COEF];
 226         u32 yv_coef[NB_COEF];
 227         u32 cv_coef[NB_COEF];
 228         u32 hori_shift;
 229         u32 vert_shift;
 230 };
 231 
 232 /* Default ParamCtrl: all controls enabled */
 233 #define HVSRC_PARAM_CTRL_DFLT           0xFFFFFFFF
 234 
 235 struct sti_hqvdp_iqi {
 236         u32 config;
 237         u32 demo_wind_size;
 238         u32 pk_config;
 239         u32 coeff0_coeff1;
 240         u32 coeff2_coeff3;
 241         u32 coeff4;
 242         u32 pk_lut;
 243         u32 pk_gain;
 244         u32 pk_coring_level;
 245         u32 cti_config;
 246         u32 le_config;
 247         u32 le_lut[64];
 248         u32 con_bri;
 249         u32 sat_gain;
 250         u32 pxf_conf;
 251         u32 default_color;
 252 };
 253 
 254 /* Default Config : IQI bypassed */
 255 #define IQI_CONFIG_DFLT                 0x00000001
 256 /* Default Contrast & Brightness gain = 256 */
 257 #define IQI_CON_BRI_DFLT                0x00000100
 258 /* Default Saturation gain = 256 */
 259 #define IQI_SAT_GAIN_DFLT               0x00000100
 260 /* Default PxfConf : P2I bypassed */
 261 #define IQI_PXF_CONF_DFLT               0x00000001
 262 
 263 struct sti_hqvdp_top_status {
 264         u32 processing_time;
 265         u32 input_y_crc;
 266         u32 input_uv_crc;
 267 };
 268 
 269 struct sti_hqvdp_fmd_status {
 270         u32 fmd_repeat_move_status;
 271         u32 fmd_scene_count_status;
 272         u32 cfd_sum;
 273         u32 field_sum;
 274         u32 next_y_fmd_crc;
 275         u32 next_next_y_fmd_crc;
 276         u32 next_next_next_y_fmd_crc;
 277 };
 278 
 279 struct sti_hqvdp_csdi_status {
 280         u32 prev_y_csdi_crc;
 281         u32 cur_y_csdi_crc;
 282         u32 next_y_csdi_crc;
 283         u32 prev_uv_csdi_crc;
 284         u32 cur_uv_csdi_crc;
 285         u32 next_uv_csdi_crc;
 286         u32 y_csdi_crc;
 287         u32 uv_csdi_crc;
 288         u32 uv_cup_crc;
 289         u32 mot_csdi_crc;
 290         u32 mot_cur_csdi_crc;
 291         u32 mot_prev_csdi_crc;
 292 };
 293 
 294 struct sti_hqvdp_hvsrc_status {
 295         u32 y_hvsrc_crc;
 296         u32 u_hvsrc_crc;
 297         u32 v_hvsrc_crc;
 298 };
 299 
 300 struct sti_hqvdp_iqi_status {
 301         u32 pxf_it_status;
 302         u32 y_iqi_crc;
 303         u32 u_iqi_crc;
 304         u32 v_iqi_crc;
 305 };
 306 
 307 /* Main commands. We use 2 commands one being processed by the firmware, one
 308  * ready to be fetched upon next Vsync*/
 309 #define NB_VDP_CMD      2
 310 
 311 struct sti_hqvdp_cmd {
 312         struct sti_hqvdp_top top;
 313         struct sti_hqvdp_vc1re vc1re;
 314         struct sti_hqvdp_fmd fmd;
 315         struct sti_hqvdp_csdi csdi;
 316         struct sti_hqvdp_hvsrc hvsrc;
 317         struct sti_hqvdp_iqi iqi;
 318         struct sti_hqvdp_top_status top_status;
 319         struct sti_hqvdp_fmd_status fmd_status;
 320         struct sti_hqvdp_csdi_status csdi_status;
 321         struct sti_hqvdp_hvsrc_status hvsrc_status;
 322         struct sti_hqvdp_iqi_status iqi_status;
 323 };
 324 
 325 /*
 326  * STI HQVDP structure
 327  *
 328  * @dev:               driver device
 329  * @drm_dev:           the drm device
 330  * @regs:              registers
 331  * @plane:             plane structure for hqvdp it self
 332  * @clk:               IP clock
 333  * @clk_pix_main:      pix main clock
 334  * @reset:             reset control
 335  * @vtg_nb:            notifier to handle VTG Vsync
 336  * @btm_field_pending: is there any bottom field (interlaced frame) to display
 337  * @hqvdp_cmd:         buffer of commands
 338  * @hqvdp_cmd_paddr:   physical address of hqvdp_cmd
 339  * @vtg:               vtg for main data path
 340  * @xp70_initialized:  true if xp70 is already initialized
 341  * @vtg_registered:    true if registered to VTG
 342  */
 343 struct sti_hqvdp {
 344         struct device *dev;
 345         struct drm_device *drm_dev;
 346         void __iomem *regs;
 347         struct sti_plane plane;
 348         struct clk *clk;
 349         struct clk *clk_pix_main;
 350         struct reset_control *reset;
 351         struct notifier_block vtg_nb;
 352         bool btm_field_pending;
 353         void *hqvdp_cmd;
 354         u32 hqvdp_cmd_paddr;
 355         struct sti_vtg *vtg;
 356         bool xp70_initialized;
 357         bool vtg_registered;
 358 };
 359 
 360 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane)
 361 
 362 static const uint32_t hqvdp_supported_formats[] = {
 363         DRM_FORMAT_NV12,
 364 };
 365 
 366 /**
 367  * sti_hqvdp_get_free_cmd
 368  * @hqvdp: hqvdp structure
 369  *
 370  * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW.
 371  *
 372  * RETURNS:
 373  * the offset of the command to be used.
 374  * -1 in error cases
 375  */
 376 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp)
 377 {
 378         u32 curr_cmd, next_cmd;
 379         u32 cmd = hqvdp->hqvdp_cmd_paddr;
 380         int i;
 381 
 382         curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
 383         next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 384 
 385         for (i = 0; i < NB_VDP_CMD; i++) {
 386                 if ((cmd != curr_cmd) && (cmd != next_cmd))
 387                         return i * sizeof(struct sti_hqvdp_cmd);
 388                 cmd += sizeof(struct sti_hqvdp_cmd);
 389         }
 390 
 391         return -1;
 392 }
 393 
 394 /**
 395  * sti_hqvdp_get_curr_cmd
 396  * @hqvdp: hqvdp structure
 397  *
 398  * Look for the hqvdp_cmd that is being used by the FW.
 399  *
 400  * RETURNS:
 401  *  the offset of the command to be used.
 402  * -1 in error cases
 403  */
 404 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp)
 405 {
 406         u32 curr_cmd;
 407         u32 cmd = hqvdp->hqvdp_cmd_paddr;
 408         unsigned int i;
 409 
 410         curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
 411 
 412         for (i = 0; i < NB_VDP_CMD; i++) {
 413                 if (cmd == curr_cmd)
 414                         return i * sizeof(struct sti_hqvdp_cmd);
 415 
 416                 cmd += sizeof(struct sti_hqvdp_cmd);
 417         }
 418 
 419         return -1;
 420 }
 421 
 422 /**
 423  * sti_hqvdp_get_next_cmd
 424  * @hqvdp: hqvdp structure
 425  *
 426  * Look for the next hqvdp_cmd that will be used by the FW.
 427  *
 428  * RETURNS:
 429  *  the offset of the next command that will be used.
 430  * -1 in error cases
 431  */
 432 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp *hqvdp)
 433 {
 434         int next_cmd;
 435         dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr;
 436         unsigned int i;
 437 
 438         next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 439 
 440         for (i = 0; i < NB_VDP_CMD; i++) {
 441                 if (cmd == next_cmd)
 442                         return i * sizeof(struct sti_hqvdp_cmd);
 443 
 444                 cmd += sizeof(struct sti_hqvdp_cmd);
 445         }
 446 
 447         return -1;
 448 }
 449 
 450 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
 451                                    readl(hqvdp->regs + reg))
 452 
 453 static const char *hqvdp_dbg_get_lut(u32 *coef)
 454 {
 455         if (!memcmp(coef, coef_lut_a_legacy, 16))
 456                 return "LUT A";
 457         if (!memcmp(coef, coef_lut_b, 16))
 458                 return "LUT B";
 459         if (!memcmp(coef, coef_lut_c_y_legacy, 16))
 460                 return "LUT C Y";
 461         if (!memcmp(coef, coef_lut_c_c_legacy, 16))
 462                 return "LUT C C";
 463         if (!memcmp(coef, coef_lut_d_y_legacy, 16))
 464                 return "LUT D Y";
 465         if (!memcmp(coef, coef_lut_d_c_legacy, 16))
 466                 return "LUT D C";
 467         if (!memcmp(coef, coef_lut_e_y_legacy, 16))
 468                 return "LUT E Y";
 469         if (!memcmp(coef, coef_lut_e_c_legacy, 16))
 470                 return "LUT E C";
 471         if (!memcmp(coef, coef_lut_f_y_legacy, 16))
 472                 return "LUT F Y";
 473         if (!memcmp(coef, coef_lut_f_c_legacy, 16))
 474                 return "LUT F C";
 475         return "<UNKNOWN>";
 476 }
 477 
 478 static void hqvdp_dbg_dump_cmd(struct seq_file *s, struct sti_hqvdp_cmd *c)
 479 {
 480         int src_w, src_h, dst_w, dst_h;
 481 
 482         seq_puts(s, "\n\tTOP:");
 483         seq_printf(s, "\n\t %-20s 0x%08X", "Config", c->top.config);
 484         switch (c->top.config) {
 485         case TOP_CONFIG_PROGRESSIVE:
 486                 seq_puts(s, "\tProgressive");
 487                 break;
 488         case TOP_CONFIG_INTER_TOP:
 489                 seq_puts(s, "\tInterlaced, top field");
 490                 break;
 491         case TOP_CONFIG_INTER_BTM:
 492                 seq_puts(s, "\tInterlaced, bottom field");
 493                 break;
 494         default:
 495                 seq_puts(s, "\t<UNKNOWN>");
 496                 break;
 497         }
 498 
 499         seq_printf(s, "\n\t %-20s 0x%08X", "MemFormat", c->top.mem_format);
 500         seq_printf(s, "\n\t %-20s 0x%08X", "CurrentY", c->top.current_luma);
 501         seq_printf(s, "\n\t %-20s 0x%08X", "CurrentC", c->top.current_chroma);
 502         seq_printf(s, "\n\t %-20s 0x%08X", "YSrcPitch", c->top.luma_src_pitch);
 503         seq_printf(s, "\n\t %-20s 0x%08X", "CSrcPitch",
 504                    c->top.chroma_src_pitch);
 505         seq_printf(s, "\n\t %-20s 0x%08X", "InputFrameSize",
 506                    c->top.input_frame_size);
 507         seq_printf(s, "\t%dx%d",
 508                    c->top.input_frame_size & 0x0000FFFF,
 509                    c->top.input_frame_size >> 16);
 510         seq_printf(s, "\n\t %-20s 0x%08X", "InputViewportSize",
 511                    c->top.input_viewport_size);
 512         src_w = c->top.input_viewport_size & 0x0000FFFF;
 513         src_h = c->top.input_viewport_size >> 16;
 514         seq_printf(s, "\t%dx%d", src_w, src_h);
 515 
 516         seq_puts(s, "\n\tHVSRC:");
 517         seq_printf(s, "\n\t %-20s 0x%08X", "OutputPictureSize",
 518                    c->hvsrc.output_picture_size);
 519         dst_w = c->hvsrc.output_picture_size & 0x0000FFFF;
 520         dst_h = c->hvsrc.output_picture_size >> 16;
 521         seq_printf(s, "\t%dx%d", dst_w, dst_h);
 522         seq_printf(s, "\n\t %-20s 0x%08X", "ParamCtrl", c->hvsrc.param_ctrl);
 523 
 524         seq_printf(s, "\n\t %-20s %s", "yh_coef",
 525                    hqvdp_dbg_get_lut(c->hvsrc.yh_coef));
 526         seq_printf(s, "\n\t %-20s %s", "ch_coef",
 527                    hqvdp_dbg_get_lut(c->hvsrc.ch_coef));
 528         seq_printf(s, "\n\t %-20s %s", "yv_coef",
 529                    hqvdp_dbg_get_lut(c->hvsrc.yv_coef));
 530         seq_printf(s, "\n\t %-20s %s", "cv_coef",
 531                    hqvdp_dbg_get_lut(c->hvsrc.cv_coef));
 532 
 533         seq_printf(s, "\n\t %-20s", "ScaleH");
 534         if (dst_w > src_w)
 535                 seq_printf(s, " %d/1", dst_w / src_w);
 536         else
 537                 seq_printf(s, " 1/%d", src_w / dst_w);
 538 
 539         seq_printf(s, "\n\t %-20s", "tScaleV");
 540         if (dst_h > src_h)
 541                 seq_printf(s, " %d/1", dst_h / src_h);
 542         else
 543                 seq_printf(s, " 1/%d", src_h / dst_h);
 544 
 545         seq_puts(s, "\n\tCSDI:");
 546         seq_printf(s, "\n\t %-20s 0x%08X\t", "Config", c->csdi.config);
 547         switch (c->csdi.config) {
 548         case CSDI_CONFIG_PROG:
 549                 seq_puts(s, "Bypass");
 550                 break;
 551         case CSDI_CONFIG_INTER_DIR:
 552                 seq_puts(s, "Deinterlace, directional");
 553                 break;
 554         default:
 555                 seq_puts(s, "<UNKNOWN>");
 556                 break;
 557         }
 558 
 559         seq_printf(s, "\n\t %-20s 0x%08X", "Config2", c->csdi.config2);
 560         seq_printf(s, "\n\t %-20s 0x%08X", "DcdiConfig", c->csdi.dcdi_config);
 561 }
 562 
 563 static int hqvdp_dbg_show(struct seq_file *s, void *data)
 564 {
 565         struct drm_info_node *node = s->private;
 566         struct sti_hqvdp *hqvdp = (struct sti_hqvdp *)node->info_ent->data;
 567         int cmd, cmd_offset, infoxp70;
 568         void *virt;
 569 
 570         seq_printf(s, "%s: (vaddr = 0x%p)",
 571                    sti_plane_to_str(&hqvdp->plane), hqvdp->regs);
 572 
 573         DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70);
 574         DBGFS_DUMP(HQVDP_MBX_INFO_HOST);
 575         DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST);
 576         DBGFS_DUMP(HQVDP_MBX_INFO_XP70);
 577         infoxp70 = readl(hqvdp->regs + HQVDP_MBX_INFO_XP70);
 578         seq_puts(s, "\tFirmware state: ");
 579         if (infoxp70 & INFO_XP70_FW_READY)
 580                 seq_puts(s, "idle and ready");
 581         else if (infoxp70 & INFO_XP70_FW_PROCESSING)
 582                 seq_puts(s, "processing a picture");
 583         else if (infoxp70 & INFO_XP70_FW_INITQUEUES)
 584                 seq_puts(s, "programming queues");
 585         else
 586                 seq_puts(s, "NOT READY");
 587 
 588         DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL);
 589         DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1);
 590         if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
 591                                         & STARTUP_CTRL1_RST_DONE)
 592                 seq_puts(s, "\tReset is done");
 593         else
 594                 seq_puts(s, "\tReset is NOT done");
 595         DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2);
 596         if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2)
 597                                         & STARTUP_CTRL2_FETCH_EN)
 598                 seq_puts(s, "\tFetch is enabled");
 599         else
 600                 seq_puts(s, "\tFetch is NOT enabled");
 601         DBGFS_DUMP(HQVDP_MBX_GP_STATUS);
 602         DBGFS_DUMP(HQVDP_MBX_NEXT_CMD);
 603         DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD);
 604         DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC);
 605         if (!(readl(hqvdp->regs + HQVDP_MBX_SOFT_VSYNC) & 3))
 606                 seq_puts(s, "\tHW Vsync");
 607         else
 608                 seq_puts(s, "\tSW Vsync ?!?!");
 609 
 610         /* Last command */
 611         cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
 612         cmd_offset = sti_hqvdp_get_curr_cmd(hqvdp);
 613         if (cmd_offset == -1) {
 614                 seq_puts(s, "\n\n  Last command: unknown");
 615         } else {
 616                 virt = hqvdp->hqvdp_cmd + cmd_offset;
 617                 seq_printf(s, "\n\n  Last command: address @ 0x%x (0x%p)",
 618                            cmd, virt);
 619                 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt);
 620         }
 621 
 622         /* Next command */
 623         cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 624         cmd_offset = sti_hqvdp_get_next_cmd(hqvdp);
 625         if (cmd_offset == -1) {
 626                 seq_puts(s, "\n\n  Next command: unknown");
 627         } else {
 628                 virt = hqvdp->hqvdp_cmd + cmd_offset;
 629                 seq_printf(s, "\n\n  Next command address: @ 0x%x (0x%p)",
 630                            cmd, virt);
 631                 hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt);
 632         }
 633 
 634         seq_putc(s, '\n');
 635         return 0;
 636 }
 637 
 638 static struct drm_info_list hqvdp_debugfs_files[] = {
 639         { "hqvdp", hqvdp_dbg_show, 0, NULL },
 640 };
 641 
 642 static int hqvdp_debugfs_init(struct sti_hqvdp *hqvdp, struct drm_minor *minor)
 643 {
 644         unsigned int i;
 645 
 646         for (i = 0; i < ARRAY_SIZE(hqvdp_debugfs_files); i++)
 647                 hqvdp_debugfs_files[i].data = hqvdp;
 648 
 649         return drm_debugfs_create_files(hqvdp_debugfs_files,
 650                                         ARRAY_SIZE(hqvdp_debugfs_files),
 651                                         minor->debugfs_root, minor);
 652 }
 653 
 654 /**
 655  * sti_hqvdp_update_hvsrc
 656  * @orient: horizontal or vertical
 657  * @scale:  scaling/zoom factor
 658  * @hvsrc:  the structure containing the LUT coef
 659  *
 660  * Update the Y and C Lut coef, as well as the shift param
 661  *
 662  * RETURNS:
 663  * None.
 664  */
 665 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale,
 666                 struct sti_hqvdp_hvsrc *hvsrc)
 667 {
 668         const int *coef_c, *coef_y;
 669         int shift_c, shift_y;
 670 
 671         /* Get the appropriate coef tables */
 672         if (scale < SCALE_MAX_FOR_LEG_LUT_F) {
 673                 coef_y = coef_lut_f_y_legacy;
 674                 coef_c = coef_lut_f_c_legacy;
 675                 shift_y = SHIFT_LUT_F_Y_LEGACY;
 676                 shift_c = SHIFT_LUT_F_C_LEGACY;
 677         } else if (scale < SCALE_MAX_FOR_LEG_LUT_E) {
 678                 coef_y = coef_lut_e_y_legacy;
 679                 coef_c = coef_lut_e_c_legacy;
 680                 shift_y = SHIFT_LUT_E_Y_LEGACY;
 681                 shift_c = SHIFT_LUT_E_C_LEGACY;
 682         } else if (scale < SCALE_MAX_FOR_LEG_LUT_D) {
 683                 coef_y = coef_lut_d_y_legacy;
 684                 coef_c = coef_lut_d_c_legacy;
 685                 shift_y = SHIFT_LUT_D_Y_LEGACY;
 686                 shift_c = SHIFT_LUT_D_C_LEGACY;
 687         } else if (scale < SCALE_MAX_FOR_LEG_LUT_C) {
 688                 coef_y = coef_lut_c_y_legacy;
 689                 coef_c = coef_lut_c_c_legacy;
 690                 shift_y = SHIFT_LUT_C_Y_LEGACY;
 691                 shift_c = SHIFT_LUT_C_C_LEGACY;
 692         } else if (scale == SCALE_MAX_FOR_LEG_LUT_C) {
 693                 coef_y = coef_c = coef_lut_b;
 694                 shift_y = shift_c = SHIFT_LUT_B;
 695         } else {
 696                 coef_y = coef_c = coef_lut_a_legacy;
 697                 shift_y = shift_c = SHIFT_LUT_A_LEGACY;
 698         }
 699 
 700         if (orient == HVSRC_HORI) {
 701                 hvsrc->hori_shift = (shift_c << 16) | shift_y;
 702                 memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef));
 703                 memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef));
 704         } else {
 705                 hvsrc->vert_shift = (shift_c << 16) | shift_y;
 706                 memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef));
 707                 memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef));
 708         }
 709 }
 710 
 711 /**
 712  * sti_hqvdp_check_hw_scaling
 713  * @hqvdp: hqvdp pointer
 714  * @mode: display mode with timing constraints
 715  * @src_w: source width
 716  * @src_h: source height
 717  * @dst_w: destination width
 718  * @dst_h: destination height
 719  *
 720  * Check if the HW is able to perform the scaling request
 721  * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where:
 722  *   Zy = OutputHeight / InputHeight
 723  *   LFW = (Tx * IPClock) / (MaxNbCycles * Cp)
 724  *     Tx : Total video mode horizontal resolution
 725  *     IPClock : HQVDP IP clock (Mhz)
 726  *     MaxNbCycles: max(InputWidth, OutputWidth)
 727  *     Cp: Video mode pixel clock (Mhz)
 728  *
 729  * RETURNS:
 730  * True if the HW can scale.
 731  */
 732 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp *hqvdp,
 733                                        struct drm_display_mode *mode,
 734                                        int src_w, int src_h,
 735                                        int dst_w, int dst_h)
 736 {
 737         unsigned long lfw;
 738         unsigned int inv_zy;
 739 
 740         lfw = mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000);
 741         lfw /= max(src_w, dst_w) * mode->clock / 1000;
 742 
 743         inv_zy = DIV_ROUND_UP(src_h, dst_h);
 744 
 745         return (inv_zy <= lfw) ? true : false;
 746 }
 747 
 748 /**
 749  * sti_hqvdp_disable
 750  * @hqvdp: hqvdp pointer
 751  *
 752  * Disables the HQVDP plane
 753  */
 754 static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp)
 755 {
 756         int i;
 757 
 758         DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp->plane));
 759 
 760         /* Unregister VTG Vsync callback */
 761         if (sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb))
 762                 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
 763 
 764         /* Set next cmd to NULL */
 765         writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 766 
 767         for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
 768                 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
 769                                 & INFO_XP70_FW_READY)
 770                         break;
 771                 msleep(POLL_DELAY_MS);
 772         }
 773 
 774         /* VTG can stop now */
 775         clk_disable_unprepare(hqvdp->clk_pix_main);
 776 
 777         if (i == POLL_MAX_ATTEMPT)
 778                 DRM_ERROR("XP70 could not revert to idle\n");
 779 
 780         hqvdp->plane.status = STI_PLANE_DISABLED;
 781         hqvdp->vtg_registered = false;
 782 }
 783 
 784 /**
 785  * sti_vdp_vtg_cb
 786  * @nb: notifier block
 787  * @evt: event message
 788  * @data: private data
 789  *
 790  * Handle VTG Vsync event, display pending bottom field
 791  *
 792  * RETURNS:
 793  * 0 on success.
 794  */
 795 static int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data)
 796 {
 797         struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb);
 798         int btm_cmd_offset, top_cmd_offest;
 799         struct sti_hqvdp_cmd *btm_cmd, *top_cmd;
 800 
 801         if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) {
 802                 DRM_DEBUG_DRIVER("Unknown event\n");
 803                 return 0;
 804         }
 805 
 806         if (hqvdp->plane.status == STI_PLANE_FLUSHING) {
 807                 /* disable need to be synchronize on vsync event */
 808                 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
 809                                  sti_plane_to_str(&hqvdp->plane));
 810 
 811                 sti_hqvdp_disable(hqvdp);
 812         }
 813 
 814         if (hqvdp->btm_field_pending) {
 815                 /* Create the btm field command from the current one */
 816                 btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
 817                 top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp);
 818                 if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) {
 819                         DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n");
 820                         return -EBUSY;
 821                 }
 822 
 823                 btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset;
 824                 top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest;
 825 
 826                 memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd));
 827 
 828                 btm_cmd->top.config = TOP_CONFIG_INTER_BTM;
 829                 btm_cmd->top.current_luma +=
 830                                 btm_cmd->top.luma_src_pitch / 2;
 831                 btm_cmd->top.current_chroma +=
 832                                 btm_cmd->top.chroma_src_pitch / 2;
 833 
 834                 /* Post the command to mailbox */
 835                 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset,
 836                                 hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 837 
 838                 hqvdp->btm_field_pending = false;
 839 
 840                 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
 841                                 __func__, hqvdp->hqvdp_cmd_paddr);
 842 
 843                 sti_plane_update_fps(&hqvdp->plane, false, true);
 844         }
 845 
 846         return 0;
 847 }
 848 
 849 static void sti_hqvdp_init(struct sti_hqvdp *hqvdp)
 850 {
 851         int size;
 852         dma_addr_t dma_addr;
 853 
 854         hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb;
 855 
 856         /* Allocate memory for the VDP commands */
 857         size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd);
 858         hqvdp->hqvdp_cmd = dma_alloc_wc(hqvdp->dev, size,
 859                                         &dma_addr,
 860                                         GFP_KERNEL | GFP_DMA);
 861         if (!hqvdp->hqvdp_cmd) {
 862                 DRM_ERROR("Failed to allocate memory for VDP cmd\n");
 863                 return;
 864         }
 865 
 866         hqvdp->hqvdp_cmd_paddr = (u32)dma_addr;
 867         memset(hqvdp->hqvdp_cmd, 0, size);
 868 }
 869 
 870 static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp)
 871 {
 872         /* Configure Plugs (same for RD & WR) */
 873         writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE);
 874         writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC);
 875         writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC);
 876         writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK);
 877         writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG);
 878         writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE);
 879         writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL);
 880 
 881         writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE);
 882         writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC);
 883         writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC);
 884         writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK);
 885         writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG);
 886         writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE);
 887         writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL);
 888 }
 889 
 890 /**
 891  * sti_hqvdp_start_xp70
 892  * @hqvdp: hqvdp pointer
 893  *
 894  * Run the xP70 initialization sequence
 895  */
 896 static void sti_hqvdp_start_xp70(struct sti_hqvdp *hqvdp)
 897 {
 898         const struct firmware *firmware;
 899         u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem;
 900         u8 *data;
 901         int i;
 902         struct fw_header {
 903                 int rd_size;
 904                 int wr_size;
 905                 int pmem_size;
 906                 int dmem_size;
 907         } *header;
 908 
 909         DRM_DEBUG_DRIVER("\n");
 910 
 911         if (hqvdp->xp70_initialized) {
 912                 DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n");
 913                 return;
 914         }
 915 
 916         /* Request firmware */
 917         if (request_firmware(&firmware, HQVDP_FMW_NAME, hqvdp->dev)) {
 918                 DRM_ERROR("Can't get HQVDP firmware\n");
 919                 return;
 920         }
 921 
 922         /* Check firmware parts */
 923         if (!firmware) {
 924                 DRM_ERROR("Firmware not available\n");
 925                 return;
 926         }
 927 
 928         header = (struct fw_header *)firmware->data;
 929         if (firmware->size < sizeof(*header)) {
 930                 DRM_ERROR("Invalid firmware size (%d)\n", firmware->size);
 931                 goto out;
 932         }
 933         if ((sizeof(*header) + header->rd_size + header->wr_size +
 934                 header->pmem_size + header->dmem_size) != firmware->size) {
 935                 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n",
 936                           sizeof(*header), header->rd_size, header->wr_size,
 937                           header->pmem_size, header->dmem_size,
 938                           firmware->size);
 939                 goto out;
 940         }
 941 
 942         data = (u8 *)firmware->data;
 943         data += sizeof(*header);
 944         fw_rd_plug = (void *)data;
 945         data += header->rd_size;
 946         fw_wr_plug = (void *)data;
 947         data += header->wr_size;
 948         fw_pmem = (void *)data;
 949         data += header->pmem_size;
 950         fw_dmem = (void *)data;
 951 
 952         /* Enable clock */
 953         if (clk_prepare_enable(hqvdp->clk))
 954                 DRM_ERROR("Failed to prepare/enable HQVDP clk\n");
 955 
 956         /* Reset */
 957         writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL);
 958 
 959         for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
 960                 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
 961                                 & STARTUP_CTRL1_RST_DONE)
 962                         break;
 963                 msleep(POLL_DELAY_MS);
 964         }
 965         if (i == POLL_MAX_ATTEMPT) {
 966                 DRM_ERROR("Could not reset\n");
 967                 clk_disable_unprepare(hqvdp->clk);
 968                 goto out;
 969         }
 970 
 971         /* Init Read & Write plugs */
 972         for (i = 0; i < header->rd_size / 4; i++)
 973                 writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4);
 974         for (i = 0; i < header->wr_size / 4; i++)
 975                 writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4);
 976 
 977         sti_hqvdp_init_plugs(hqvdp);
 978 
 979         /* Authorize Idle Mode */
 980         writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1);
 981 
 982         /* Prevent VTG interruption during the boot */
 983         writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
 984         writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 985 
 986         /* Download PMEM & DMEM */
 987         for (i = 0; i < header->pmem_size / 4; i++)
 988                 writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4);
 989         for (i = 0; i < header->dmem_size / 4; i++)
 990                 writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4);
 991 
 992         /* Enable fetch */
 993         writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2);
 994 
 995         /* Wait end of boot */
 996         for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
 997                 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
 998                                 & INFO_XP70_FW_READY)
 999                         break;
1000                 msleep(POLL_DELAY_MS);
1001         }
1002         if (i == POLL_MAX_ATTEMPT) {
1003                 DRM_ERROR("Could not boot\n");
1004                 clk_disable_unprepare(hqvdp->clk);
1005                 goto out;
1006         }
1007 
1008         /* Launch Vsync */
1009         writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
1010 
1011         DRM_INFO("HQVDP XP70 initialized\n");
1012 
1013         hqvdp->xp70_initialized = true;
1014 
1015 out:
1016         release_firmware(firmware);
1017 }
1018 
1019 static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane,
1020                                   struct drm_plane_state *state)
1021 {
1022         struct sti_plane *plane = to_sti_plane(drm_plane);
1023         struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1024         struct drm_crtc *crtc = state->crtc;
1025         struct drm_framebuffer *fb = state->fb;
1026         struct drm_crtc_state *crtc_state;
1027         struct drm_display_mode *mode;
1028         int dst_x, dst_y, dst_w, dst_h;
1029         int src_x, src_y, src_w, src_h;
1030 
1031         /* no need for further checks if the plane is being disabled */
1032         if (!crtc || !fb)
1033                 return 0;
1034 
1035         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
1036         mode = &crtc_state->mode;
1037         dst_x = state->crtc_x;
1038         dst_y = state->crtc_y;
1039         dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
1040         dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
1041         /* src_x are in 16.16 format */
1042         src_x = state->src_x >> 16;
1043         src_y = state->src_y >> 16;
1044         src_w = state->src_w >> 16;
1045         src_h = state->src_h >> 16;
1046 
1047         if (mode->clock && !sti_hqvdp_check_hw_scaling(hqvdp, mode,
1048                                                        src_w, src_h,
1049                                                        dst_w, dst_h)) {
1050                 DRM_ERROR("Scaling beyond HW capabilities\n");
1051                 return -EINVAL;
1052         }
1053 
1054         if (!drm_fb_cma_get_gem_obj(fb, 0)) {
1055                 DRM_ERROR("Can't get CMA GEM object for fb\n");
1056                 return -EINVAL;
1057         }
1058 
1059         /*
1060          * Input / output size
1061          * Align to upper even value
1062          */
1063         dst_w = ALIGN(dst_w, 2);
1064         dst_h = ALIGN(dst_h, 2);
1065 
1066         if ((src_w > MAX_WIDTH) || (src_w < MIN_WIDTH) ||
1067             (src_h > MAX_HEIGHT) || (src_h < MIN_HEIGHT) ||
1068             (dst_w > MAX_WIDTH) || (dst_w < MIN_WIDTH) ||
1069             (dst_h > MAX_HEIGHT) || (dst_h < MIN_HEIGHT)) {
1070                 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n",
1071                           src_w, src_h,
1072                           dst_w, dst_h);
1073                 return -EINVAL;
1074         }
1075 
1076         if (!hqvdp->xp70_initialized)
1077                 /* Start HQVDP XP70 coprocessor */
1078                 sti_hqvdp_start_xp70(hqvdp);
1079 
1080         if (!hqvdp->vtg_registered) {
1081                 /* Prevent VTG shutdown */
1082                 if (clk_prepare_enable(hqvdp->clk_pix_main)) {
1083                         DRM_ERROR("Failed to prepare/enable pix main clk\n");
1084                         return -EINVAL;
1085                 }
1086 
1087                 /* Register VTG Vsync callback to handle bottom fields */
1088                 if (sti_vtg_register_client(hqvdp->vtg,
1089                                             &hqvdp->vtg_nb,
1090                                             crtc)) {
1091                         DRM_ERROR("Cannot register VTG notifier\n");
1092                         clk_disable_unprepare(hqvdp->clk_pix_main);
1093                         return -EINVAL;
1094                 }
1095                 hqvdp->vtg_registered = true;
1096         }
1097 
1098         DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
1099                       crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)),
1100                       drm_plane->base.id, sti_plane_to_str(plane));
1101         DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
1102                       sti_plane_to_str(plane),
1103                       dst_w, dst_h, dst_x, dst_y,
1104                       src_w, src_h, src_x, src_y);
1105 
1106         return 0;
1107 }
1108 
1109 static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane,
1110                                     struct drm_plane_state *oldstate)
1111 {
1112         struct drm_plane_state *state = drm_plane->state;
1113         struct sti_plane *plane = to_sti_plane(drm_plane);
1114         struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1115         struct drm_crtc *crtc = state->crtc;
1116         struct drm_framebuffer *fb = state->fb;
1117         struct drm_display_mode *mode;
1118         int dst_x, dst_y, dst_w, dst_h;
1119         int src_x, src_y, src_w, src_h;
1120         struct drm_gem_cma_object *cma_obj;
1121         struct sti_hqvdp_cmd *cmd;
1122         int scale_h, scale_v;
1123         int cmd_offset;
1124 
1125         if (!crtc || !fb)
1126                 return;
1127 
1128         if ((oldstate->fb == state->fb) &&
1129             (oldstate->crtc_x == state->crtc_x) &&
1130             (oldstate->crtc_y == state->crtc_y) &&
1131             (oldstate->crtc_w == state->crtc_w) &&
1132             (oldstate->crtc_h == state->crtc_h) &&
1133             (oldstate->src_x == state->src_x) &&
1134             (oldstate->src_y == state->src_y) &&
1135             (oldstate->src_w == state->src_w) &&
1136             (oldstate->src_h == state->src_h)) {
1137                 /* No change since last update, do not post cmd */
1138                 DRM_DEBUG_DRIVER("No change, not posting cmd\n");
1139                 plane->status = STI_PLANE_UPDATED;
1140                 return;
1141         }
1142 
1143         mode = &crtc->mode;
1144         dst_x = state->crtc_x;
1145         dst_y = state->crtc_y;
1146         dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
1147         dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
1148         /* src_x are in 16.16 format */
1149         src_x = state->src_x >> 16;
1150         src_y = state->src_y >> 16;
1151         src_w = state->src_w >> 16;
1152         src_h = state->src_h >> 16;
1153 
1154         cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
1155         if (cmd_offset == -1) {
1156                 DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n");
1157                 return;
1158         }
1159         cmd = hqvdp->hqvdp_cmd + cmd_offset;
1160 
1161         /* Static parameters, defaulting to progressive mode */
1162         cmd->top.config = TOP_CONFIG_PROGRESSIVE;
1163         cmd->top.mem_format = TOP_MEM_FORMAT_DFLT;
1164         cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT;
1165         cmd->csdi.config = CSDI_CONFIG_PROG;
1166 
1167         /* VC1RE, FMD bypassed : keep everything set to 0
1168          * IQI/P2I bypassed */
1169         cmd->iqi.config = IQI_CONFIG_DFLT;
1170         cmd->iqi.con_bri = IQI_CON_BRI_DFLT;
1171         cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT;
1172         cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT;
1173 
1174         cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
1175 
1176         DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
1177                          (char *)&fb->format->format,
1178                          (unsigned long)cma_obj->paddr);
1179 
1180         /* Buffer planes address */
1181         cmd->top.current_luma = (u32)cma_obj->paddr + fb->offsets[0];
1182         cmd->top.current_chroma = (u32)cma_obj->paddr + fb->offsets[1];
1183 
1184         /* Pitches */
1185         cmd->top.luma_processed_pitch = fb->pitches[0];
1186         cmd->top.luma_src_pitch = fb->pitches[0];
1187         cmd->top.chroma_processed_pitch = fb->pitches[1];
1188         cmd->top.chroma_src_pitch = fb->pitches[1];
1189 
1190         /* Input / output size
1191          * Align to upper even value */
1192         dst_w = ALIGN(dst_w, 2);
1193         dst_h = ALIGN(dst_h, 2);
1194 
1195         cmd->top.input_viewport_size = src_h << 16 | src_w;
1196         cmd->top.input_frame_size = src_h << 16 | src_w;
1197         cmd->hvsrc.output_picture_size = dst_h << 16 | dst_w;
1198         cmd->top.input_viewport_ori = src_y << 16 | src_x;
1199 
1200         /* Handle interlaced */
1201         if (fb->flags & DRM_MODE_FB_INTERLACED) {
1202                 /* Top field to display */
1203                 cmd->top.config = TOP_CONFIG_INTER_TOP;
1204 
1205                 /* Update pitches and vert size */
1206                 cmd->top.input_frame_size = (src_h / 2) << 16 | src_w;
1207                 cmd->top.luma_processed_pitch *= 2;
1208                 cmd->top.luma_src_pitch *= 2;
1209                 cmd->top.chroma_processed_pitch *= 2;
1210                 cmd->top.chroma_src_pitch *= 2;
1211 
1212                 /* Enable directional deinterlacing processing */
1213                 cmd->csdi.config = CSDI_CONFIG_INTER_DIR;
1214                 cmd->csdi.config2 = CSDI_CONFIG2_DFLT;
1215                 cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT;
1216         }
1217 
1218         /* Update hvsrc lut coef */
1219         scale_h = SCALE_FACTOR * dst_w / src_w;
1220         sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc);
1221 
1222         scale_v = SCALE_FACTOR * dst_h / src_h;
1223         sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc);
1224 
1225         writel(hqvdp->hqvdp_cmd_paddr + cmd_offset,
1226                hqvdp->regs + HQVDP_MBX_NEXT_CMD);
1227 
1228         /* Interlaced : get ready to display the bottom field at next Vsync */
1229         if (fb->flags & DRM_MODE_FB_INTERLACED)
1230                 hqvdp->btm_field_pending = true;
1231 
1232         dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
1233                 __func__, hqvdp->hqvdp_cmd_paddr + cmd_offset);
1234 
1235         sti_plane_update_fps(plane, true, true);
1236 
1237         plane->status = STI_PLANE_UPDATED;
1238 }
1239 
1240 static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane,
1241                                      struct drm_plane_state *oldstate)
1242 {
1243         struct sti_plane *plane = to_sti_plane(drm_plane);
1244 
1245         if (!oldstate->crtc) {
1246                 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
1247                                  drm_plane->base.id);
1248                 return;
1249         }
1250 
1251         DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
1252                          oldstate->crtc->base.id,
1253                          sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
1254                          drm_plane->base.id, sti_plane_to_str(plane));
1255 
1256         plane->status = STI_PLANE_DISABLING;
1257 }
1258 
1259 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs = {
1260         .atomic_check = sti_hqvdp_atomic_check,
1261         .atomic_update = sti_hqvdp_atomic_update,
1262         .atomic_disable = sti_hqvdp_atomic_disable,
1263 };
1264 
1265 static void sti_hqvdp_destroy(struct drm_plane *drm_plane)
1266 {
1267         DRM_DEBUG_DRIVER("\n");
1268 
1269         drm_plane_cleanup(drm_plane);
1270 }
1271 
1272 static int sti_hqvdp_late_register(struct drm_plane *drm_plane)
1273 {
1274         struct sti_plane *plane = to_sti_plane(drm_plane);
1275         struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1276 
1277         return hqvdp_debugfs_init(hqvdp, drm_plane->dev->primary);
1278 }
1279 
1280 static const struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs = {
1281         .update_plane = drm_atomic_helper_update_plane,
1282         .disable_plane = drm_atomic_helper_disable_plane,
1283         .destroy = sti_hqvdp_destroy,
1284         .reset = sti_plane_reset,
1285         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1286         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1287         .late_register = sti_hqvdp_late_register,
1288 };
1289 
1290 static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev,
1291                                           struct device *dev, int desc)
1292 {
1293         struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
1294         int res;
1295 
1296         hqvdp->plane.desc = desc;
1297         hqvdp->plane.status = STI_PLANE_DISABLED;
1298 
1299         sti_hqvdp_init(hqvdp);
1300 
1301         res = drm_universal_plane_init(drm_dev, &hqvdp->plane.drm_plane, 1,
1302                                        &sti_hqvdp_plane_helpers_funcs,
1303                                        hqvdp_supported_formats,
1304                                        ARRAY_SIZE(hqvdp_supported_formats),
1305                                        NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
1306         if (res) {
1307                 DRM_ERROR("Failed to initialize universal plane\n");
1308                 return NULL;
1309         }
1310 
1311         drm_plane_helper_add(&hqvdp->plane.drm_plane, &sti_hqvdp_helpers_funcs);
1312 
1313         sti_plane_init_property(&hqvdp->plane, DRM_PLANE_TYPE_OVERLAY);
1314 
1315         return &hqvdp->plane.drm_plane;
1316 }
1317 
1318 static int sti_hqvdp_bind(struct device *dev, struct device *master, void *data)
1319 {
1320         struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
1321         struct drm_device *drm_dev = data;
1322         struct drm_plane *plane;
1323 
1324         DRM_DEBUG_DRIVER("\n");
1325 
1326         hqvdp->drm_dev = drm_dev;
1327 
1328         /* Create HQVDP plane once xp70 is initialized */
1329         plane = sti_hqvdp_create(drm_dev, hqvdp->dev, STI_HQVDP_0);
1330         if (!plane)
1331                 DRM_ERROR("Can't create HQVDP plane\n");
1332 
1333         return 0;
1334 }
1335 
1336 static void sti_hqvdp_unbind(struct device *dev,
1337                 struct device *master, void *data)
1338 {
1339         /* do nothing */
1340 }
1341 
1342 static const struct component_ops sti_hqvdp_ops = {
1343         .bind = sti_hqvdp_bind,
1344         .unbind = sti_hqvdp_unbind,
1345 };
1346 
1347 static int sti_hqvdp_probe(struct platform_device *pdev)
1348 {
1349         struct device *dev = &pdev->dev;
1350         struct device_node *vtg_np;
1351         struct sti_hqvdp *hqvdp;
1352         struct resource *res;
1353 
1354         DRM_DEBUG_DRIVER("\n");
1355 
1356         hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL);
1357         if (!hqvdp) {
1358                 DRM_ERROR("Failed to allocate HQVDP context\n");
1359                 return -ENOMEM;
1360         }
1361 
1362         hqvdp->dev = dev;
1363 
1364         /* Get Memory resources */
1365         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1366         if (!res) {
1367                 DRM_ERROR("Get memory resource failed\n");
1368                 return -ENXIO;
1369         }
1370         hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res));
1371         if (!hqvdp->regs) {
1372                 DRM_ERROR("Register mapping failed\n");
1373                 return -ENXIO;
1374         }
1375 
1376         /* Get clock resources */
1377         hqvdp->clk = devm_clk_get(dev, "hqvdp");
1378         hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main");
1379         if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) {
1380                 DRM_ERROR("Cannot get clocks\n");
1381                 return -ENXIO;
1382         }
1383 
1384         /* Get reset resources */
1385         hqvdp->reset = devm_reset_control_get(dev, "hqvdp");
1386         if (!IS_ERR(hqvdp->reset))
1387                 reset_control_deassert(hqvdp->reset);
1388 
1389         vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0);
1390         if (vtg_np)
1391                 hqvdp->vtg = of_vtg_find(vtg_np);
1392         of_node_put(vtg_np);
1393 
1394         platform_set_drvdata(pdev, hqvdp);
1395 
1396         return component_add(&pdev->dev, &sti_hqvdp_ops);
1397 }
1398 
1399 static int sti_hqvdp_remove(struct platform_device *pdev)
1400 {
1401         component_del(&pdev->dev, &sti_hqvdp_ops);
1402         return 0;
1403 }
1404 
1405 static const struct of_device_id hqvdp_of_match[] = {
1406         { .compatible = "st,stih407-hqvdp", },
1407         { /* end node */ }
1408 };
1409 MODULE_DEVICE_TABLE(of, hqvdp_of_match);
1410 
1411 struct platform_driver sti_hqvdp_driver = {
1412         .driver = {
1413                 .name = "sti-hqvdp",
1414                 .owner = THIS_MODULE,
1415                 .of_match_table = hqvdp_of_match,
1416         },
1417         .probe = sti_hqvdp_probe,
1418         .remove = sti_hqvdp_remove,
1419 };
1420 
1421 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1422 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1423 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/sti/sti_hqvdp.c

DEFINITIONS
