drivers/gpu/drm/ast/ast

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This source file includes following definitions.
ast_set_index_reg
ast_open_key
   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial portions
  22  * of the Software.
  23  *
  24  */
  25 /*
  26  * Authors: Dave Airlie <airlied@redhat.com>
  27  */
  28 #ifndef __AST_DRV_H__
  29 #define __AST_DRV_H__
  30 
  31 #include <linux/types.h>
  32 #include <linux/io.h>
  33 #include <linux/i2c.h>
  34 #include <linux/i2c-algo-bit.h>
  35 
  36 #include <drm/drm_connector.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_encoder.h>
  39 #include <drm/drm_mode.h>
  40 #include <drm/drm_framebuffer.h>
  41 #include <drm/drm_fb_helper.h>
  42 
  43 #define DRIVER_AUTHOR           "Dave Airlie"
  44 
  45 #define DRIVER_NAME             "ast"
  46 #define DRIVER_DESC             "AST"
  47 #define DRIVER_DATE             "20120228"
  48 
  49 #define DRIVER_MAJOR            0
  50 #define DRIVER_MINOR            1
  51 #define DRIVER_PATCHLEVEL       0
  52 
  53 #define PCI_CHIP_AST2000 0x2000
  54 #define PCI_CHIP_AST2100 0x2010
  55 #define PCI_CHIP_AST1180 0x1180
  56 
  57 
  58 enum ast_chip {
  59         AST2000,
  60         AST2100,
  61         AST1100,
  62         AST2200,
  63         AST2150,
  64         AST2300,
  65         AST2400,
  66         AST2500,
  67         AST1180,
  68 };
  69 
  70 enum ast_tx_chip {
  71         AST_TX_NONE,
  72         AST_TX_SIL164,
  73         AST_TX_ITE66121,
  74         AST_TX_DP501,
  75 };
  76 
  77 #define AST_DRAM_512Mx16 0
  78 #define AST_DRAM_1Gx16   1
  79 #define AST_DRAM_512Mx32 2
  80 #define AST_DRAM_1Gx32   3
  81 #define AST_DRAM_2Gx16   6
  82 #define AST_DRAM_4Gx16   7
  83 #define AST_DRAM_8Gx16   8
  84 
  85 struct ast_private {
  86         struct drm_device *dev;
  87 
  88         void __iomem *regs;
  89         void __iomem *ioregs;
  90 
  91         enum ast_chip chip;
  92         bool vga2_clone;
  93         uint32_t dram_bus_width;
  94         uint32_t dram_type;
  95         uint32_t mclk;
  96         uint32_t vram_size;
  97 
  98         int fb_mtrr;
  99 
 100         struct drm_gem_object *cursor_cache;
 101         int next_cursor;
 102         bool support_wide_screen;
 103         enum {
 104                 ast_use_p2a,
 105                 ast_use_dt,
 106                 ast_use_defaults
 107         } config_mode;
 108 
 109         enum ast_tx_chip tx_chip_type;
 110         u8 dp501_maxclk;
 111         u8 *dp501_fw_addr;
 112         const struct firmware *dp501_fw;        /* dp501 fw */
 113 };
 114 
 115 int ast_driver_load(struct drm_device *dev, unsigned long flags);
 116 void ast_driver_unload(struct drm_device *dev);
 117 
 118 struct ast_gem_object;
 119 
 120 #define AST_IO_AR_PORT_WRITE            (0x40)
 121 #define AST_IO_MISC_PORT_WRITE          (0x42)
 122 #define AST_IO_VGA_ENABLE_PORT          (0x43)
 123 #define AST_IO_SEQ_PORT                 (0x44)
 124 #define AST_IO_DAC_INDEX_READ           (0x47)
 125 #define AST_IO_DAC_INDEX_WRITE          (0x48)
 126 #define AST_IO_DAC_DATA                 (0x49)
 127 #define AST_IO_GR_PORT                  (0x4E)
 128 #define AST_IO_CRTC_PORT                (0x54)
 129 #define AST_IO_INPUT_STATUS1_READ       (0x5A)
 130 #define AST_IO_MISC_PORT_READ           (0x4C)
 131 
 132 #define AST_IO_MM_OFFSET                (0x380)
 133 
 134 #define __ast_read(x) \
 135 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
 136 u##x val = 0;\
 137 val = ioread##x(ast->regs + reg); \
 138 return val;\
 139 }
 140 
 141 __ast_read(8);
 142 __ast_read(16);
 143 __ast_read(32)
 144 
 145 #define __ast_io_read(x) \
 146 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
 147 u##x val = 0;\
 148 val = ioread##x(ast->ioregs + reg); \
 149 return val;\
 150 }
 151 
 152 __ast_io_read(8);
 153 __ast_io_read(16);
 154 __ast_io_read(32);
 155 
 156 #define __ast_write(x) \
 157 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
 158         iowrite##x(val, ast->regs + reg);\
 159         }
 160 
 161 __ast_write(8);
 162 __ast_write(16);
 163 __ast_write(32);
 164 
 165 #define __ast_io_write(x) \
 166 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
 167         iowrite##x(val, ast->ioregs + reg);\
 168         }
 169 
 170 __ast_io_write(8);
 171 __ast_io_write(16);
 172 #undef __ast_io_write
 173 
 174 static inline void ast_set_index_reg(struct ast_private *ast,
 175                                      uint32_t base, uint8_t index,
 176                                      uint8_t val)
 177 {
 178         ast_io_write16(ast, base, ((u16)val << 8) | index);
 179 }
 180 
 181 void ast_set_index_reg_mask(struct ast_private *ast,
 182                             uint32_t base, uint8_t index,
 183                             uint8_t mask, uint8_t val);
 184 uint8_t ast_get_index_reg(struct ast_private *ast,
 185                           uint32_t base, uint8_t index);
 186 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
 187                                uint32_t base, uint8_t index, uint8_t mask);
 188 
 189 static inline void ast_open_key(struct ast_private *ast)
 190 {
 191         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
 192 }
 193 
 194 #define AST_VIDMEM_SIZE_8M    0x00800000
 195 #define AST_VIDMEM_SIZE_16M   0x01000000
 196 #define AST_VIDMEM_SIZE_32M   0x02000000
 197 #define AST_VIDMEM_SIZE_64M   0x04000000
 198 #define AST_VIDMEM_SIZE_128M  0x08000000
 199 
 200 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
 201 
 202 #define AST_MAX_HWC_WIDTH 64
 203 #define AST_MAX_HWC_HEIGHT 64
 204 
 205 #define AST_HWC_SIZE                (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2)
 206 #define AST_HWC_SIGNATURE_SIZE      32
 207 
 208 #define AST_DEFAULT_HWC_NUM 2
 209 /* define for signature structure */
 210 #define AST_HWC_SIGNATURE_CHECKSUM  0x00
 211 #define AST_HWC_SIGNATURE_SizeX     0x04
 212 #define AST_HWC_SIGNATURE_SizeY     0x08
 213 #define AST_HWC_SIGNATURE_X         0x0C
 214 #define AST_HWC_SIGNATURE_Y         0x10
 215 #define AST_HWC_SIGNATURE_HOTSPOTX  0x14
 216 #define AST_HWC_SIGNATURE_HOTSPOTY  0x18
 217 
 218 
 219 struct ast_i2c_chan {
 220         struct i2c_adapter adapter;
 221         struct drm_device *dev;
 222         struct i2c_algo_bit_data bit;
 223 };
 224 
 225 struct ast_connector {
 226         struct drm_connector base;
 227         struct ast_i2c_chan *i2c;
 228 };
 229 
 230 struct ast_crtc {
 231         struct drm_crtc base;
 232         u8 offset_x, offset_y;
 233 };
 234 
 235 struct ast_encoder {
 236         struct drm_encoder base;
 237 };
 238 
 239 #define to_ast_crtc(x) container_of(x, struct ast_crtc, base)
 240 #define to_ast_connector(x) container_of(x, struct ast_connector, base)
 241 #define to_ast_encoder(x) container_of(x, struct ast_encoder, base)
 242 
 243 struct ast_vbios_stdtable {
 244         u8 misc;
 245         u8 seq[4];
 246         u8 crtc[25];
 247         u8 ar[20];
 248         u8 gr[9];
 249 };
 250 
 251 struct ast_vbios_enhtable {
 252         u32 ht;
 253         u32 hde;
 254         u32 hfp;
 255         u32 hsync;
 256         u32 vt;
 257         u32 vde;
 258         u32 vfp;
 259         u32 vsync;
 260         u32 dclk_index;
 261         u32 flags;
 262         u32 refresh_rate;
 263         u32 refresh_rate_index;
 264         u32 mode_id;
 265 };
 266 
 267 struct ast_vbios_dclk_info {
 268         u8 param1;
 269         u8 param2;
 270         u8 param3;
 271 };
 272 
 273 struct ast_vbios_mode_info {
 274         const struct ast_vbios_stdtable *std_table;
 275         const struct ast_vbios_enhtable *enh_table;
 276 };
 277 
 278 extern int ast_mode_init(struct drm_device *dev);
 279 extern void ast_mode_fini(struct drm_device *dev);
 280 
 281 #define AST_MM_ALIGN_SHIFT 4
 282 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
 283 
 284 int ast_mm_init(struct ast_private *ast);
 285 void ast_mm_fini(struct ast_private *ast);
 286 
 287 int ast_gem_create(struct drm_device *dev,
 288                    u32 size, bool iskernel,
 289                    struct drm_gem_object **obj);
 290 
 291 /* ast post */
 292 void ast_enable_vga(struct drm_device *dev);
 293 void ast_enable_mmio(struct drm_device *dev);
 294 bool ast_is_vga_enabled(struct drm_device *dev);
 295 void ast_post_gpu(struct drm_device *dev);
 296 u32 ast_mindwm(struct ast_private *ast, u32 r);
 297 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
 298 /* ast dp501 */
 299 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
 300 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
 301 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
 302 u8 ast_get_dp501_max_clk(struct drm_device *dev);
 303 void ast_init_3rdtx(struct drm_device *dev);
 304 void ast_release_firmware(struct drm_device *dev);
 305 #endif
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root/drivers/gpu/drm/ast/ast_drv.h

INCLUDED FROM

DEFINITIONS
