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6 #ifndef _MTK_HDMI_REGS_H
7 #define _MTK_HDMI_REGS_H
8
9 #define GRL_INT_MASK 0x18
10 #define GRL_IFM_PORT 0x188
11 #define GRL_CH_SWAP 0x198
12 #define LR_SWAP BIT(0)
13 #define LFE_CC_SWAP BIT(1)
14 #define LSRS_SWAP BIT(2)
15 #define RLS_RRS_SWAP BIT(3)
16 #define LR_STATUS_SWAP BIT(4)
17 #define GRL_I2S_C_STA0 0x140
18 #define GRL_I2S_C_STA1 0x144
19 #define GRL_I2S_C_STA2 0x148
20 #define GRL_I2S_C_STA3 0x14C
21 #define GRL_I2S_C_STA4 0x150
22 #define GRL_I2S_UV 0x154
23 #define I2S_UV_V BIT(0)
24 #define I2S_UV_U BIT(1)
25 #define I2S_UV_CH_EN_MASK 0x3c
26 #define I2S_UV_CH_EN(x) BIT((x) + 2)
27 #define I2S_UV_TMDS_DEBUG BIT(6)
28 #define I2S_UV_NORMAL_INFO_INV BIT(7)
29 #define GRL_ACP_ISRC_CTRL 0x158
30 #define VS_EN BIT(0)
31 #define ACP_EN BIT(1)
32 #define ISRC1_EN BIT(2)
33 #define ISRC2_EN BIT(3)
34 #define GAMUT_EN BIT(4)
35 #define GRL_CTS_CTRL 0x160
36 #define CTS_CTRL_SOFT BIT(0)
37 #define GRL_INT 0x14
38 #define INT_MDI BIT(0)
39 #define INT_HDCP BIT(1)
40 #define INT_FIFO_O BIT(2)
41 #define INT_FIFO_U BIT(3)
42 #define INT_IFM_ERR BIT(4)
43 #define INT_INF_DONE BIT(5)
44 #define INT_NCTS_DONE BIT(6)
45 #define INT_CTRL_PKT_DONE BIT(7)
46 #define GRL_INT_MASK 0x18
47 #define GRL_CTRL 0x1C
48 #define CTRL_GEN_EN BIT(2)
49 #define CTRL_SPD_EN BIT(3)
50 #define CTRL_MPEG_EN BIT(4)
51 #define CTRL_AUDIO_EN BIT(5)
52 #define CTRL_AVI_EN BIT(6)
53 #define CTRL_AVMUTE BIT(7)
54 #define GRL_STATUS 0x20
55 #define STATUS_HTPLG BIT(0)
56 #define STATUS_PORD BIT(1)
57 #define GRL_DIVN 0x170
58 #define NCTS_WRI_ANYTIME BIT(6)
59 #define GRL_AUDIO_CFG 0x17C
60 #define AUDIO_ZERO BIT(0)
61 #define HIGH_BIT_RATE BIT(1)
62 #define SACD_DST BIT(2)
63 #define DST_NORMAL_DOUBLE BIT(3)
64 #define DSD_INV BIT(4)
65 #define LR_INV BIT(5)
66 #define LR_MIX BIT(6)
67 #define DSD_SEL BIT(7)
68 #define GRL_NCTS 0x184
69 #define GRL_CH_SW0 0x18C
70 #define GRL_CH_SW1 0x190
71 #define GRL_CH_SW2 0x194
72 #define CH_SWITCH(from, to) ((from) << ((to) * 3))
73 #define GRL_INFOFRM_VER 0x19C
74 #define GRL_INFOFRM_TYPE 0x1A0
75 #define GRL_INFOFRM_LNG 0x1A4
76 #define GRL_MIX_CTRL 0x1B4
77 #define MIX_CTRL_SRC_EN BIT(0)
78 #define BYPASS_VOLUME BIT(1)
79 #define MIX_CTRL_FLAT BIT(7)
80 #define GRL_AOUT_CFG 0x1C4
81 #define AOUT_BNUM_SEL_MASK 0x03
82 #define AOUT_24BIT 0x00
83 #define AOUT_20BIT 0x02
84 #define AOUT_16BIT 0x03
85 #define AOUT_FIFO_ADAP_CTRL BIT(6)
86 #define AOUT_BURST_PREAMBLE_EN BIT(7)
87 #define HIGH_BIT_RATE_PACKET_ALIGN (AOUT_BURST_PREAMBLE_EN | \
88 AOUT_FIFO_ADAP_CTRL)
89 #define GRL_SHIFT_L1 0x1C0
90 #define GRL_SHIFT_R2 0x1B0
91 #define AUDIO_PACKET_OFF BIT(6)
92 #define GRL_CFG0 0x24
93 #define CFG0_I2S_MODE_MASK 0x3
94 #define CFG0_I2S_MODE_RTJ 0x1
95 #define CFG0_I2S_MODE_LTJ 0x0
96 #define CFG0_I2S_MODE_I2S 0x2
97 #define CFG0_W_LENGTH_MASK 0x30
98 #define CFG0_W_LENGTH_24BIT 0x00
99 #define CFG0_W_LENGTH_16BIT 0x10
100 #define GRL_CFG1 0x28
101 #define CFG1_EDG_SEL BIT(0)
102 #define CFG1_SPDIF BIT(1)
103 #define CFG1_DVI BIT(2)
104 #define CFG1_HDCP_DEBUG BIT(3)
105 #define GRL_CFG2 0x2c
106 #define CFG2_MHL_DE_SEL BIT(3)
107 #define CFG2_MHL_FAKE_DE_SEL BIT(4)
108 #define CFG2_MHL_DATA_REMAP BIT(5)
109 #define CFG2_NOTICE_EN BIT(6)
110 #define CFG2_ACLK_INV BIT(7)
111 #define GRL_CFG3 0x30
112 #define CFG3_AES_KEY_INDEX_MASK 0x3f
113 #define CFG3_CONTROL_PACKET_DELAY BIT(6)
114 #define CFG3_KSV_LOAD_START BIT(7)
115 #define GRL_CFG4 0x34
116 #define CFG4_AES_KEY_LOAD BIT(4)
117 #define CFG4_AV_UNMUTE_EN BIT(5)
118 #define CFG4_AV_UNMUTE_SET BIT(6)
119 #define CFG4_MHL_MODE BIT(7)
120 #define GRL_CFG5 0x38
121 #define CFG5_CD_RATIO_MASK 0x8F
122 #define CFG5_FS128 (0x1 << 4)
123 #define CFG5_FS256 (0x2 << 4)
124 #define CFG5_FS384 (0x3 << 4)
125 #define CFG5_FS512 (0x4 << 4)
126 #define CFG5_FS768 (0x6 << 4)
127 #define DUMMY_304 0x304
128 #define CHMO_SEL (0x3 << 2)
129 #define CHM1_SEL (0x3 << 4)
130 #define CHM2_SEL (0x3 << 6)
131 #define AUDIO_I2S_NCTS_SEL BIT(1)
132 #define AUDIO_I2S_NCTS_SEL_64 (1 << 1)
133 #define AUDIO_I2S_NCTS_SEL_128 (0 << 1)
134 #define NEW_GCP_CTRL BIT(0)
135 #define NEW_GCP_CTRL_MERGE BIT(0)
136 #define GRL_L_STATUS_0 0x200
137 #define GRL_L_STATUS_1 0x204
138 #define GRL_L_STATUS_2 0x208
139 #define GRL_L_STATUS_3 0x20c
140 #define GRL_L_STATUS_4 0x210
141 #define GRL_L_STATUS_5 0x214
142 #define GRL_L_STATUS_6 0x218
143 #define GRL_L_STATUS_7 0x21c
144 #define GRL_L_STATUS_8 0x220
145 #define GRL_L_STATUS_9 0x224
146 #define GRL_L_STATUS_10 0x228
147 #define GRL_L_STATUS_11 0x22c
148 #define GRL_L_STATUS_12 0x230
149 #define GRL_L_STATUS_13 0x234
150 #define GRL_L_STATUS_14 0x238
151 #define GRL_L_STATUS_15 0x23c
152 #define GRL_L_STATUS_16 0x240
153 #define GRL_L_STATUS_17 0x244
154 #define GRL_L_STATUS_18 0x248
155 #define GRL_L_STATUS_19 0x24c
156 #define GRL_L_STATUS_20 0x250
157 #define GRL_L_STATUS_21 0x254
158 #define GRL_L_STATUS_22 0x258
159 #define GRL_L_STATUS_23 0x25c
160 #define GRL_R_STATUS_0 0x260
161 #define GRL_R_STATUS_1 0x264
162 #define GRL_R_STATUS_2 0x268
163 #define GRL_R_STATUS_3 0x26c
164 #define GRL_R_STATUS_4 0x270
165 #define GRL_R_STATUS_5 0x274
166 #define GRL_R_STATUS_6 0x278
167 #define GRL_R_STATUS_7 0x27c
168 #define GRL_R_STATUS_8 0x280
169 #define GRL_R_STATUS_9 0x284
170 #define GRL_R_STATUS_10 0x288
171 #define GRL_R_STATUS_11 0x28c
172 #define GRL_R_STATUS_12 0x290
173 #define GRL_R_STATUS_13 0x294
174 #define GRL_R_STATUS_14 0x298
175 #define GRL_R_STATUS_15 0x29c
176 #define GRL_R_STATUS_16 0x2a0
177 #define GRL_R_STATUS_17 0x2a4
178 #define GRL_R_STATUS_18 0x2a8
179 #define GRL_R_STATUS_19 0x2ac
180 #define GRL_R_STATUS_20 0x2b0
181 #define GRL_R_STATUS_21 0x2b4
182 #define GRL_R_STATUS_22 0x2b8
183 #define GRL_R_STATUS_23 0x2bc
184 #define GRL_ABIST_CTRL0 0x2D4
185 #define GRL_ABIST_CTRL1 0x2D8
186 #define ABIST_EN BIT(7)
187 #define ABIST_DATA_FMT (0x7 << 0)
188 #define VIDEO_CFG_0 0x380
189 #define VIDEO_CFG_1 0x384
190 #define VIDEO_CFG_2 0x388
191 #define VIDEO_CFG_3 0x38c
192 #define VIDEO_CFG_4 0x390
193 #define VIDEO_SOURCE_SEL BIT(7)
194 #define NORMAL_PATH (1 << 7)
195 #define GEN_RGB (0 << 7)
196
197 #define HDMI_SYS_CFG1C 0x000
198 #define HDMI_ON BIT(0)
199 #define HDMI_RST BIT(1)
200 #define ANLG_ON BIT(2)
201 #define CFG10_DVI BIT(3)
202 #define HDMI_TST BIT(3)
203 #define SYS_KEYMASK1 (0xff << 8)
204 #define SYS_KEYMASK2 (0xff << 16)
205 #define AUD_OUTSYNC_EN BIT(24)
206 #define AUD_OUTSYNC_PRE_EN BIT(25)
207 #define I2CM_ON BIT(26)
208 #define E2PROM_TYPE_8BIT BIT(27)
209 #define MCM_E2PROM_ON BIT(28)
210 #define EXT_E2PROM_ON BIT(29)
211 #define HTPLG_PIN_SEL_OFF BIT(30)
212 #define AES_EFUSE_ENABLE BIT(31)
213 #define HDMI_SYS_CFG20 0x004
214 #define DEEP_COLOR_MODE_MASK (3 << 1)
215 #define COLOR_8BIT_MODE (0 << 1)
216 #define COLOR_10BIT_MODE (1 << 1)
217 #define COLOR_12BIT_MODE (2 << 1)
218 #define COLOR_16BIT_MODE (3 << 1)
219 #define DEEP_COLOR_EN BIT(0)
220 #define HDMI_AUDIO_TEST_SEL BIT(8)
221 #define HDMI2P0_EN BIT(11)
222 #define HDMI_OUT_FIFO_EN BIT(16)
223 #define HDMI_OUT_FIFO_CLK_INV BIT(17)
224 #define MHL_MODE_ON BIT(28)
225 #define MHL_PP_MODE BIT(29)
226 #define MHL_SYNC_AUTO_EN BIT(30)
227 #define HDMI_PCLK_FREE_RUN BIT(31)
228
229 #define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
230 #endif