root/drivers/gpu/drm/etnaviv/state_hi.xml.h

INCLUDED FROM

   1 #ifndef STATE_HI_XML
   2 #define STATE_HI_XML
   3 
   4 /* Autogenerated file, DO NOT EDIT manually!
   5 
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://0x04.net/cgit/index.cgi/rules-ng-ng
   8 git clone git://0x04.net/rules-ng-ng
   9 
  10 The rules-ng-ng source files this header was generated from are:
  11 - state.xml     (  26087 bytes, from 2017-12-18 16:51:59)
  12 - common.xml    (  35468 bytes, from 2018-01-22 13:48:54)
  13 - common_3d.xml (  14615 bytes, from 2017-12-18 16:51:59)
  14 - state_hi.xml  (  30232 bytes, from 2018-02-15 15:48:01)
  15 - copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
  16 - state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
  17 - state_3d.xml  (  79992 bytes, from 2017-12-18 16:51:59)
  18 - state_blt.xml (  13405 bytes, from 2017-12-18 16:51:59)
  19 - state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
  20 
  21 Copyright (C) 2012-2018 by the following authors:
  22 - Wladimir J. van der Laan <laanwj@gmail.com>
  23 - Christian Gmeiner <christian.gmeiner@gmail.com>
  24 - Lucas Stach <l.stach@pengutronix.de>
  25 - Russell King <rmk@arm.linux.org.uk>
  26 
  27 Permission is hereby granted, free of charge, to any person obtaining a
  28 copy of this software and associated documentation files (the "Software"),
  29 to deal in the Software without restriction, including without limitation
  30 the rights to use, copy, modify, merge, publish, distribute, sub license,
  31 and/or sell copies of the Software, and to permit persons to whom the
  32 Software is furnished to do so, subject to the following conditions:
  33 
  34 The above copyright notice and this permission notice (including the
  35 next paragraph) shall be included in all copies or substantial portions
  36 of the Software.
  37 
  38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  39 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  40 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  41 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  42 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  44 DEALINGS IN THE SOFTWARE.
  45 */
  46 
  47 
  48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT                         0x00000001
  49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT                          0x00000002
  50 #define MMU_EXCEPTION_WRITE_VIOLATION                           0x00000003
  51 #define VIVS_HI                                                 0x00000000
  52 
  53 #define VIVS_HI_CLOCK_CONTROL                                   0x00000000
  54 #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS                         0x00000001
  55 #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS                         0x00000002
  56 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK                  0x000001fc
  57 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT                 2
  58 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x)                     (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK)
  59 #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD                   0x00000200
  60 #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING            0x00000400
  61 #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS           0x00000800
  62 #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET                        0x00001000
  63 #define VIVS_HI_CLOCK_CONTROL_IDLE_3D                           0x00010000
  64 #define VIVS_HI_CLOCK_CONTROL_IDLE_2D                           0x00020000
  65 #define VIVS_HI_CLOCK_CONTROL_IDLE_VG                           0x00040000
  66 #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU                       0x00080000
  67 #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK            0x00f00000
  68 #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT           20
  69 #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x)               (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK)
  70 
  71 #define VIVS_HI_IDLE_STATE                                      0x00000004
  72 #define VIVS_HI_IDLE_STATE_FE                                   0x00000001
  73 #define VIVS_HI_IDLE_STATE_DE                                   0x00000002
  74 #define VIVS_HI_IDLE_STATE_PE                                   0x00000004
  75 #define VIVS_HI_IDLE_STATE_SH                                   0x00000008
  76 #define VIVS_HI_IDLE_STATE_PA                                   0x00000010
  77 #define VIVS_HI_IDLE_STATE_SE                                   0x00000020
  78 #define VIVS_HI_IDLE_STATE_RA                                   0x00000040
  79 #define VIVS_HI_IDLE_STATE_TX                                   0x00000080
  80 #define VIVS_HI_IDLE_STATE_VG                                   0x00000100
  81 #define VIVS_HI_IDLE_STATE_IM                                   0x00000200
  82 #define VIVS_HI_IDLE_STATE_FP                                   0x00000400
  83 #define VIVS_HI_IDLE_STATE_TS                                   0x00000800
  84 #define VIVS_HI_IDLE_STATE_AXI_LP                               0x80000000
  85 
  86 #define VIVS_HI_AXI_CONFIG                                      0x00000008
  87 #define VIVS_HI_AXI_CONFIG_AWID__MASK                           0x0000000f
  88 #define VIVS_HI_AXI_CONFIG_AWID__SHIFT                          0
  89 #define VIVS_HI_AXI_CONFIG_AWID(x)                              (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK)
  90 #define VIVS_HI_AXI_CONFIG_ARID__MASK                           0x000000f0
  91 #define VIVS_HI_AXI_CONFIG_ARID__SHIFT                          4
  92 #define VIVS_HI_AXI_CONFIG_ARID(x)                              (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK)
  93 #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK                        0x00000f00
  94 #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT                       8
  95 #define VIVS_HI_AXI_CONFIG_AWCACHE(x)                           (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK)
  96 #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK                        0x0000f000
  97 #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT                       12
  98 #define VIVS_HI_AXI_CONFIG_ARCACHE(x)                           (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK)
  99 
 100 #define VIVS_HI_AXI_STATUS                                      0x0000000c
 101 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK                      0x0000000f
 102 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT                     0
 103 #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x)                         (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK)
 104 #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK                      0x000000f0
 105 #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT                     4
 106 #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x)                         (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK)
 107 #define VIVS_HI_AXI_STATUS_DET_WR_ERR                           0x00000100
 108 #define VIVS_HI_AXI_STATUS_DET_RD_ERR                           0x00000200
 109 
 110 #define VIVS_HI_INTR_ACKNOWLEDGE                                0x00000010
 111 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK                 0x3fffffff
 112 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT                0
 113 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x)                    (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)
 114 #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION                  0x40000000
 115 #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR                  0x80000000
 116 
 117 #define VIVS_HI_INTR_ENBL                                       0x00000014
 118 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK                   0xffffffff
 119 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT                  0
 120 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x)                      (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK)
 121 
 122 #define VIVS_HI_CHIP_IDENTITY                                   0x00000018
 123 #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK                      0xff000000
 124 #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT                     24
 125 #define VIVS_HI_CHIP_IDENTITY_FAMILY(x)                         (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK)
 126 #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK                     0x00ff0000
 127 #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT                    16
 128 #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x)                        (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK)
 129 #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK                    0x0000f000
 130 #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT                   12
 131 #define VIVS_HI_CHIP_IDENTITY_REVISION(x)                       (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK)
 132 
 133 #define VIVS_HI_CHIP_FEATURE                                    0x0000001c
 134 
 135 #define VIVS_HI_CHIP_MODEL                                      0x00000020
 136 
 137 #define VIVS_HI_CHIP_REV                                        0x00000024
 138 
 139 #define VIVS_HI_CHIP_DATE                                       0x00000028
 140 
 141 #define VIVS_HI_CHIP_TIME                                       0x0000002c
 142 
 143 #define VIVS_HI_CHIP_MINOR_FEATURE_0                            0x00000034
 144 
 145 #define VIVS_HI_CACHE_CONTROL                                   0x00000038
 146 
 147 #define VIVS_HI_MEMORY_COUNTER_RESET                            0x0000003c
 148 
 149 #define VIVS_HI_PROFILE_READ_BYTES8                             0x00000040
 150 
 151 #define VIVS_HI_PROFILE_WRITE_BYTES8                            0x00000044
 152 
 153 #define VIVS_HI_CHIP_SPECS                                      0x00000048
 154 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK                   0x0000000f
 155 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT                  0
 156 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x)                      (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK)
 157 #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK                   0x000000f0
 158 #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT                  4
 159 #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x)                      (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK)
 160 #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK                   0x00000f00
 161 #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT                  8
 162 #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x)                      (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK)
 163 #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK              0x0001f000
 164 #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT             12
 165 #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x)                 (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK)
 166 #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK              0x01f00000
 167 #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT             20
 168 #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x)                 (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK)
 169 #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK                    0x0e000000
 170 #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT                   25
 171 #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x)                       (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK)
 172 #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK      0xf0000000
 173 #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT     28
 174 #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x)         (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK)
 175 
 176 #define VIVS_HI_PROFILE_WRITE_BURSTS                            0x0000004c
 177 
 178 #define VIVS_HI_PROFILE_WRITE_REQUESTS                          0x00000050
 179 
 180 #define VIVS_HI_PROFILE_READ_BURSTS                             0x00000058
 181 
 182 #define VIVS_HI_PROFILE_READ_REQUESTS                           0x0000005c
 183 
 184 #define VIVS_HI_PROFILE_READ_LASTS                              0x00000060
 185 
 186 #define VIVS_HI_GP_OUT0                                         0x00000064
 187 
 188 #define VIVS_HI_GP_OUT1                                         0x00000068
 189 
 190 #define VIVS_HI_GP_OUT2                                         0x0000006c
 191 
 192 #define VIVS_HI_AXI_CONTROL                                     0x00000070
 193 #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE                  0x00000001
 194 
 195 #define VIVS_HI_CHIP_MINOR_FEATURE_1                            0x00000074
 196 
 197 #define VIVS_HI_PROFILE_TOTAL_CYCLES                            0x00000078
 198 
 199 #define VIVS_HI_PROFILE_IDLE_CYCLES                             0x0000007c
 200 
 201 #define VIVS_HI_CHIP_SPECS_2                                    0x00000080
 202 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK                  0x000000ff
 203 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT                 0
 204 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x)                     (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK)
 205 #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK            0x0000ff00
 206 #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT           8
 207 #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x)               (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK)
 208 #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK                0xffff0000
 209 #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT               16
 210 #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x)                   (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK)
 211 
 212 #define VIVS_HI_CHIP_MINOR_FEATURE_2                            0x00000084
 213 
 214 #define VIVS_HI_CHIP_MINOR_FEATURE_3                            0x00000088
 215 
 216 #define VIVS_HI_CHIP_SPECS_3                                    0x0000008c
 217 #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK               0x000001f0
 218 #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT              4
 219 #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x)                  (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK)
 220 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK               0x00000007
 221 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT              0
 222 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x)                  (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK)
 223 
 224 #define VIVS_HI_COMPRESSION_FLAGS                               0x00000090
 225 #define VIVS_HI_COMPRESSION_FLAGS_DEC300                        0x00000040
 226 
 227 #define VIVS_HI_CHIP_MINOR_FEATURE_4                            0x00000094
 228 
 229 #define VIVS_HI_CHIP_SPECS_4                                    0x0000009c
 230 #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK                 0x0001f000
 231 #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT                12
 232 #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x)                    (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK)
 233 
 234 #define VIVS_HI_CHIP_MINOR_FEATURE_5                            0x000000a0
 235 
 236 #define VIVS_HI_CHIP_PRODUCT_ID                                 0x000000a8
 237 
 238 #define VIVS_HI_BLT_INTR                                        0x000000d4
 239 
 240 #define VIVS_HI_AUXBIT                                          0x000000ec
 241 
 242 #define VIVS_PM                                                 0x00000000
 243 
 244 #define VIVS_PM_POWER_CONTROLS                                  0x00000100
 245 #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING       0x00000001
 246 #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING        0x00000002
 247 #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING       0x00000004
 248 #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK            0x000000f0
 249 #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT           4
 250 #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x)               (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK)
 251 #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK           0xffff0000
 252 #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT          16
 253 #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x)              (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK)
 254 
 255 #define VIVS_PM_MODULE_CONTROLS                                 0x00000104
 256 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE  0x00000001
 257 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE  0x00000002
 258 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE  0x00000004
 259 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH  0x00000008
 260 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA  0x00000010
 261 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE  0x00000020
 262 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA  0x00000040
 263 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX  0x00000080
 264 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ       0x00010000
 265 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ       0x00020000
 266 
 267 #define VIVS_PM_MODULE_STATUS                                   0x00000108
 268 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE             0x00000001
 269 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE             0x00000002
 270 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE             0x00000004
 271 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH             0x00000008
 272 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA             0x00000010
 273 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE             0x00000020
 274 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA             0x00000040
 275 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX             0x00000080
 276 
 277 #define VIVS_PM_PULSE_EATER                                     0x0000010c
 278 #define VIVS_PM_PULSE_EATER_DISABLE                             0x00000001
 279 #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK                   0x0000ff00
 280 #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT                  8
 281 #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x)                      (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK)
 282 #define VIVS_PM_PULSE_EATER_UNK16                               0x00010000
 283 #define VIVS_PM_PULSE_EATER_UNK17                               0x00020000
 284 #define VIVS_PM_PULSE_EATER_INTERNAL_DFS                        0x00040000
 285 #define VIVS_PM_PULSE_EATER_UNK19                               0x00080000
 286 #define VIVS_PM_PULSE_EATER_UNK20                               0x00100000
 287 #define VIVS_PM_PULSE_EATER_UNK22                               0x00400000
 288 #define VIVS_PM_PULSE_EATER_UNK23                               0x00800000
 289 
 290 #define VIVS_MMUv2                                              0x00000000
 291 
 292 #define VIVS_MMUv2_SAFE_ADDRESS                                 0x00000180
 293 
 294 #define VIVS_MMUv2_CONFIGURATION                                0x00000184
 295 #define VIVS_MMUv2_CONFIGURATION_MODE__MASK                     0x00000001
 296 #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT                    0
 297 #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K                   0x00000000
 298 #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K                   0x00000001
 299 #define VIVS_MMUv2_CONFIGURATION_MODE_MASK                      0x00000008
 300 #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK                    0x00000010
 301 #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT                   4
 302 #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH                    0x00000010
 303 #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK                     0x00000080
 304 #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK                   0x00000100
 305 #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK                  0xfffffc00
 306 #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT                 10
 307 #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x)                     (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK)
 308 
 309 #define VIVS_MMUv2_STATUS                                       0x00000188
 310 #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK                      0x00000003
 311 #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT                     0
 312 #define VIVS_MMUv2_STATUS_EXCEPTION0(x)                         (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK)
 313 #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK                      0x00000030
 314 #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT                     4
 315 #define VIVS_MMUv2_STATUS_EXCEPTION1(x)                         (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK)
 316 #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK                      0x00000300
 317 #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT                     8
 318 #define VIVS_MMUv2_STATUS_EXCEPTION2(x)                         (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK)
 319 #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK                      0x00003000
 320 #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT                     12
 321 #define VIVS_MMUv2_STATUS_EXCEPTION3(x)                         (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK)
 322 
 323 #define VIVS_MMUv2_CONTROL                                      0x0000018c
 324 #define VIVS_MMUv2_CONTROL_ENABLE                               0x00000001
 325 
 326 #define VIVS_MMUv2_EXCEPTION_ADDR(i0)                          (0x00000190 + 0x4*(i0))
 327 #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE                        0x00000004
 328 #define VIVS_MMUv2_EXCEPTION_ADDR__LEN                          0x00000004
 329 
 330 #define VIVS_MMUv2_PROFILE_BLT_READ                             0x000001a4
 331 
 332 #define VIVS_MMUv2_PTA_CONFIG                                   0x000001ac
 333 #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK                       0x0000ffff
 334 #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT                      0
 335 #define VIVS_MMUv2_PTA_CONFIG_INDEX(x)                          (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK)
 336 #define VIVS_MMUv2_PTA_CONFIG_UNK16                             0x00010000
 337 
 338 #define VIVS_MMUv2_AXI_POLICY(i0)                              (0x000001c0 + 0x4*(i0))
 339 #define VIVS_MMUv2_AXI_POLICY__ESIZE                            0x00000004
 340 #define VIVS_MMUv2_AXI_POLICY__LEN                              0x00000008
 341 
 342 #define VIVS_MMUv2_SEC_EXCEPTION_ADDR                           0x00000380
 343 
 344 #define VIVS_MMUv2_SEC_STATUS                                   0x00000384
 345 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK                  0x00000003
 346 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT                 0
 347 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK)
 348 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK                  0x00000030
 349 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT                 4
 350 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK)
 351 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK                  0x00000300
 352 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT                 8
 353 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK)
 354 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK                  0x00003000
 355 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT                 12
 356 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK)
 357 
 358 #define VIVS_MMUv2_SEC_CONTROL                                  0x00000388
 359 #define VIVS_MMUv2_SEC_CONTROL_ENABLE                           0x00000001
 360 
 361 #define VIVS_MMUv2_PTA_ADDRESS_LOW                              0x0000038c
 362 
 363 #define VIVS_MMUv2_PTA_ADDRESS_HIGH                             0x00000390
 364 
 365 #define VIVS_MMUv2_PTA_CONTROL                                  0x00000394
 366 #define VIVS_MMUv2_PTA_CONTROL_ENABLE                           0x00000001
 367 
 368 #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW                         0x00000398
 369 
 370 #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW                            0x0000039c
 371 
 372 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG                          0x000003a0
 373 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK     0x000000ff
 374 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT    0
 375 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x)        (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK)
 376 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15                    0x00008000
 377 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000
 378 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT        16
 379 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x)    (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK)
 380 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31                    0x80000000
 381 
 382 #define VIVS_MMUv2_SEC_COMMAND_CONTROL                          0x000003a4
 383 #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK           0x0000ffff
 384 #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT          0
 385 #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x)              (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK)
 386 #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE                   0x00010000
 387 
 388 #define VIVS_MMUv2_AHB_CONTROL                                  0x000003a8
 389 #define VIVS_MMUv2_AHB_CONTROL_RESET                            0x00000001
 390 #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS                    0x00000002
 391 
 392 #define VIVS_MC                                                 0x00000000
 393 
 394 #define VIVS_MC_MMU_FE_PAGE_TABLE                               0x00000400
 395 
 396 #define VIVS_MC_MMU_TX_PAGE_TABLE                               0x00000404
 397 
 398 #define VIVS_MC_MMU_PE_PAGE_TABLE                               0x00000408
 399 
 400 #define VIVS_MC_MMU_PEZ_PAGE_TABLE                              0x0000040c
 401 
 402 #define VIVS_MC_MMU_RA_PAGE_TABLE                               0x00000410
 403 
 404 #define VIVS_MC_DEBUG_MEMORY                                    0x00000414
 405 #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320                0x00000008
 406 #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS                  0x00100000
 407 #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS                 0x00200000
 408 
 409 #define VIVS_MC_MEMORY_BASE_ADDR_RA                             0x00000418
 410 
 411 #define VIVS_MC_MEMORY_BASE_ADDR_FE                             0x0000041c
 412 
 413 #define VIVS_MC_MEMORY_BASE_ADDR_TX                             0x00000420
 414 
 415 #define VIVS_MC_MEMORY_BASE_ADDR_PEZ                            0x00000424
 416 
 417 #define VIVS_MC_MEMORY_BASE_ADDR_PE                             0x00000428
 418 
 419 #define VIVS_MC_MEMORY_TIMING_CONTROL                           0x0000042c
 420 
 421 #define VIVS_MC_MEMORY_FLUSH                                    0x00000430
 422 
 423 #define VIVS_MC_PROFILE_CYCLE_COUNTER                           0x00000438
 424 
 425 #define VIVS_MC_DEBUG_READ0                                     0x0000043c
 426 
 427 #define VIVS_MC_DEBUG_READ1                                     0x00000440
 428 
 429 #define VIVS_MC_DEBUG_WRITE                                     0x00000444
 430 
 431 #define VIVS_MC_PROFILE_RA_READ                                 0x00000448
 432 
 433 #define VIVS_MC_PROFILE_TX_READ                                 0x0000044c
 434 
 435 #define VIVS_MC_PROFILE_FE_READ                                 0x00000450
 436 
 437 #define VIVS_MC_PROFILE_PE_READ                                 0x00000454
 438 
 439 #define VIVS_MC_PROFILE_DE_READ                                 0x00000458
 440 
 441 #define VIVS_MC_PROFILE_SH_READ                                 0x0000045c
 442 
 443 #define VIVS_MC_PROFILE_PA_READ                                 0x00000460
 444 
 445 #define VIVS_MC_PROFILE_SE_READ                                 0x00000464
 446 
 447 #define VIVS_MC_PROFILE_MC_READ                                 0x00000468
 448 
 449 #define VIVS_MC_PROFILE_HI_READ                                 0x0000046c
 450 
 451 #define VIVS_MC_PROFILE_CONFIG0                                 0x00000470
 452 #define VIVS_MC_PROFILE_CONFIG0_FE__MASK                        0x000000ff
 453 #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT                       0
 454 #define VIVS_MC_PROFILE_CONFIG0_FE_RESET                        0x0000000f
 455 #define VIVS_MC_PROFILE_CONFIG0_DE__MASK                        0x0000ff00
 456 #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT                       8
 457 #define VIVS_MC_PROFILE_CONFIG0_DE_RESET                        0x00000f00
 458 #define VIVS_MC_PROFILE_CONFIG0_PE__MASK                        0x00ff0000
 459 #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT                       16
 460 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE     0x00000000
 461 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE     0x00010000
 462 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE      0x00020000
 463 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE      0x00030000
 464 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D           0x000b0000
 465 #define VIVS_MC_PROFILE_CONFIG0_PE_RESET                        0x000f0000
 466 #define VIVS_MC_PROFILE_CONFIG0_SH__MASK                        0xff000000
 467 #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT                       24
 468 #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES                0x04000000
 469 #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER              0x07000000
 470 #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER       0x08000000
 471 #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER              0x09000000
 472 #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER     0x0a000000
 473 #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER      0x0b000000
 474 #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER       0x0c000000
 475 #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER      0x0d000000
 476 #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER       0x0e000000
 477 #define VIVS_MC_PROFILE_CONFIG0_SH_RESET                        0x0f000000
 478 
 479 #define VIVS_MC_PROFILE_CONFIG1                                 0x00000474
 480 #define VIVS_MC_PROFILE_CONFIG1_PA__MASK                        0x000000ff
 481 #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT                       0
 482 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER            0x00000003
 483 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER           0x00000004
 484 #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER          0x00000005
 485 #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER        0x00000006
 486 #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER     0x00000007
 487 #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER               0x00000008
 488 #define VIVS_MC_PROFILE_CONFIG1_PA_RESET                        0x0000000f
 489 #define VIVS_MC_PROFILE_CONFIG1_SE__MASK                        0x0000ff00
 490 #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT                       8
 491 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT        0x00000000
 492 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT           0x00000100
 493 #define VIVS_MC_PROFILE_CONFIG1_SE_RESET                        0x00000f00
 494 #define VIVS_MC_PROFILE_CONFIG1_RA__MASK                        0x00ff0000
 495 #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT                       16
 496 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT            0x00000000
 497 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT             0x00010000
 498 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z       0x00020000
 499 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT        0x00030000
 500 #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER      0x00090000
 501 #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER  0x000a0000
 502 #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT            0x000b0000
 503 #define VIVS_MC_PROFILE_CONFIG1_RA_RESET                        0x000f0000
 504 #define VIVS_MC_PROFILE_CONFIG1_TX__MASK                        0xff000000
 505 #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT                       24
 506 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS      0x00000000
 507 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS     0x01000000
 508 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS     0x02000000
 509 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS       0x03000000
 510 #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN                      0x04000000
 511 #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT               0x05000000
 512 #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT         0x06000000
 513 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT             0x07000000
 514 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT        0x08000000
 515 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT       0x09000000
 516 #define VIVS_MC_PROFILE_CONFIG1_TX_RESET                        0x0f000000
 517 
 518 #define VIVS_MC_PROFILE_CONFIG2                                 0x00000478
 519 #define VIVS_MC_PROFILE_CONFIG2_MC__MASK                        0x000000ff
 520 #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT                       0
 521 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE      0x00000001
 522 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP    0x00000002
 523 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE     0x00000003
 524 #define VIVS_MC_PROFILE_CONFIG2_MC_RESET                        0x0000000f
 525 #define VIVS_MC_PROFILE_CONFIG2_HI__MASK                        0x0000ff00
 526 #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT                       8
 527 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED      0x00000000
 528 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED     0x00000100
 529 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED        0x00000200
 530 #define VIVS_MC_PROFILE_CONFIG2_HI_RESET                        0x00000f00
 531 #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK                       0xff000000
 532 #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT                      24
 533 #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0                        0x00000000
 534 
 535 #define VIVS_MC_PROFILE_CONFIG3                                 0x0000047c
 536 
 537 #define VIVS_MC_BUS_CONFIG                                      0x00000480
 538 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK                  0x0000000f
 539 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT                 0
 540 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x)                     (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK)
 541 #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK                  0x000000f0
 542 #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT                 4
 543 #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x)                     (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK)
 544 
 545 #define VIVS_MC_START_COMPOSITION                               0x00000554
 546 
 547 #define VIVS_MC_FLAGS                                           0x00000558
 548 #define VIVS_MC_FLAGS_128B_MERGE                                0x00000001
 549 #define VIVS_MC_FLAGS_TPCV11_COMPRESSION                        0x08000000
 550 
 551 #define VIVS_MC_L2_CACHE_CONFIG                                 0x0000055c
 552 
 553 #define VIVS_MC_PROFILE_L2_READ                                 0x00000564
 554 
 555 
 556 #endif /* STATE_HI_XML */