root/drivers/gpu/drm/meson/meson_viu.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2016 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6 
   7 /* Video Input Unit */
   8 
   9 #ifndef __MESON_VIU_H
  10 #define __MESON_VIU_H
  11 
  12 /* OSDx_BLKx_CFG */
  13 #define OSD_CANVAS_SEL          16
  14 
  15 #define OSD_ENDIANNESS_LE       BIT(15)
  16 #define OSD_ENDIANNESS_BE       (0)
  17 
  18 #define OSD_BLK_MODE_422        (0x03 << 8)
  19 #define OSD_BLK_MODE_16         (0x04 << 8)
  20 #define OSD_BLK_MODE_32         (0x05 << 8)
  21 #define OSD_BLK_MODE_24         (0x07 << 8)
  22 
  23 #define OSD_OUTPUT_COLOR_RGB    BIT(7)
  24 #define OSD_OUTPUT_COLOR_YUV    (0)
  25 
  26 #define OSD_COLOR_MATRIX_32_RGBA        (0x00 << 2)
  27 #define OSD_COLOR_MATRIX_32_ARGB        (0x01 << 2)
  28 #define OSD_COLOR_MATRIX_32_ABGR        (0x02 << 2)
  29 #define OSD_COLOR_MATRIX_32_BGRA        (0x03 << 2)
  30 
  31 #define OSD_COLOR_MATRIX_24_RGB         (0x00 << 2)
  32 
  33 #define OSD_COLOR_MATRIX_16_RGB655      (0x00 << 2)
  34 #define OSD_COLOR_MATRIX_16_RGB565      (0x04 << 2)
  35 
  36 #define OSD_INTERLACE_ENABLED   BIT(1)
  37 #define OSD_INTERLACE_ODD       BIT(0)
  38 #define OSD_INTERLACE_EVEN      (0)
  39 
  40 /* OSDx_CTRL_STAT */
  41 #define OSD_ENABLE              BIT(21)
  42 #define OSD_BLK0_ENABLE         BIT(0)
  43 
  44 #define OSD_GLOBAL_ALPHA_SHIFT  12
  45 
  46 /* OSDx_CTRL_STAT2 */
  47 #define OSD_REPLACE_EN          BIT(14)
  48 #define OSD_REPLACE_SHIFT       6
  49 
  50 void meson_viu_osd1_reset(struct meson_drm *priv);
  51 void meson_viu_init(struct meson_drm *priv);
  52 
  53 #endif /* __MESON_VIU_H */