This source file includes following definitions.
- hdmi_writeb
- hdmi_readb
- hdmi_modb
- hdmi_mask_writeb
- dw_hdmi_i2c_init
- dw_hdmi_i2c_unwedge
- dw_hdmi_i2c_wait
- dw_hdmi_i2c_read
- dw_hdmi_i2c_write
- dw_hdmi_i2c_xfer
- dw_hdmi_i2c_func
- dw_hdmi_i2c_adapter
- hdmi_set_cts_n
- hdmi_compute_n
- hdmi_set_clk_regenerator
- hdmi_init_clk_regenerator
- hdmi_clk_regenerator_update_pixel_clock
- dw_hdmi_set_sample_rate
- dw_hdmi_set_channel_count
- dw_hdmi_set_channel_allocation
- hdmi_enable_audio_clk
- dw_hdmi_ahb_audio_enable
- dw_hdmi_ahb_audio_disable
- dw_hdmi_i2s_audio_enable
- dw_hdmi_i2s_audio_disable
- dw_hdmi_audio_enable
- dw_hdmi_audio_disable
- hdmi_bus_fmt_is_rgb
- hdmi_bus_fmt_is_yuv444
- hdmi_bus_fmt_is_yuv422
- hdmi_bus_fmt_is_yuv420
- hdmi_bus_fmt_color_depth
- hdmi_video_sample
- is_color_space_conversion
- is_color_space_decimation
- is_color_space_interpolation
- dw_hdmi_update_csc_coeffs
- hdmi_video_csc
- hdmi_video_packetize
- hdmi_phy_test_clear
- hdmi_phy_wait_i2c_done
- dw_hdmi_phy_i2c_write
- dw_hdmi_support_scdc
- dw_hdmi_set_high_tmds_clock_ratio
- dw_hdmi_phy_enable_powerdown
- dw_hdmi_phy_enable_tmds
- dw_hdmi_phy_enable_svsret
- dw_hdmi_phy_gen2_pddq
- dw_hdmi_phy_gen2_txpwron
- dw_hdmi_phy_sel_data_en_pol
- dw_hdmi_phy_sel_interface_control
- dw_hdmi_phy_reset
- dw_hdmi_phy_i2c_set_addr
- dw_hdmi_phy_power_off
- dw_hdmi_phy_power_on
- hdmi_phy_configure_dwc_hdmi_3d_tx
- hdmi_phy_configure
- dw_hdmi_phy_init
- dw_hdmi_phy_disable
- dw_hdmi_phy_read_hpd
- dw_hdmi_phy_update_hpd
- dw_hdmi_phy_setup_hpd
- hdmi_tx_hdcp_config
- hdmi_config_AVI
- hdmi_config_vendor_specific_infoframe
- hdmi_av_composer
- dw_hdmi_enable_video_path
- dw_hdmi_clear_overflow
- hdmi_disable_overflow_interrupts
- dw_hdmi_setup
- initialize_hdmi_ih_mutes
- dw_hdmi_poweron
- dw_hdmi_poweroff
- dw_hdmi_update_power
- dw_hdmi_update_phy_mask
- dw_hdmi_connector_detect
- dw_hdmi_connector_get_modes
- dw_hdmi_connector_force
- dw_hdmi_bridge_attach
- dw_hdmi_bridge_detach
- dw_hdmi_bridge_mode_valid
- dw_hdmi_bridge_mode_set
- dw_hdmi_bridge_disable
- dw_hdmi_bridge_enable
- dw_hdmi_i2c_irq
- dw_hdmi_hardirq
- dw_hdmi_setup_rx_sense
- dw_hdmi_irq
- dw_hdmi_detect_phy
- dw_hdmi_cec_enable
- dw_hdmi_cec_disable
- dw_hdmi_init_hw
- __dw_hdmi_probe
- __dw_hdmi_remove
- dw_hdmi_probe
- dw_hdmi_remove
- dw_hdmi_bind
- dw_hdmi_unbind
- dw_hdmi_resume
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8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/regmap.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spinlock.h>
21
22 #include <media/cec-notifier.h>
23
24 #include <uapi/linux/media-bus-format.h>
25 #include <uapi/linux/videodev2.h>
26
27 #include <drm/bridge/dw_hdmi.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_edid.h>
30 #include <drm/drm_of.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
33 #include <drm/drm_scdc_helper.h>
34
35 #include "dw-hdmi-audio.h"
36 #include "dw-hdmi-cec.h"
37 #include "dw-hdmi.h"
38
39 #define DDC_CI_ADDR 0x37
40 #define DDC_SEGMENT_ADDR 0x30
41
42 #define HDMI_EDID_LEN 512
43
44
45 #define SCDC_MIN_SOURCE_VERSION 0x1
46
47 #define HDMI14_MAX_TMDSCLK 340000000
48
49 enum hdmi_datamap {
50 RGB444_8B = 0x01,
51 RGB444_10B = 0x03,
52 RGB444_12B = 0x05,
53 RGB444_16B = 0x07,
54 YCbCr444_8B = 0x09,
55 YCbCr444_10B = 0x0B,
56 YCbCr444_12B = 0x0D,
57 YCbCr444_16B = 0x0F,
58 YCbCr422_8B = 0x16,
59 YCbCr422_10B = 0x14,
60 YCbCr422_12B = 0x12,
61 };
62
63 static const u16 csc_coeff_default[3][4] = {
64 { 0x2000, 0x0000, 0x0000, 0x0000 },
65 { 0x0000, 0x2000, 0x0000, 0x0000 },
66 { 0x0000, 0x0000, 0x2000, 0x0000 }
67 };
68
69 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
70 { 0x2000, 0x6926, 0x74fd, 0x010e },
71 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
72 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
73 };
74
75 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
76 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
77 { 0x2000, 0x3264, 0x0000, 0x7e6d },
78 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
79 };
80
81 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
82 { 0x2591, 0x1322, 0x074b, 0x0000 },
83 { 0x6535, 0x2000, 0x7acc, 0x0200 },
84 { 0x6acd, 0x7534, 0x2000, 0x0200 }
85 };
86
87 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
88 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
89 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
90 { 0x6756, 0x78ab, 0x2000, 0x0200 }
91 };
92
93 struct hdmi_vmode {
94 bool mdataenablepolarity;
95
96 unsigned int mpixelclock;
97 unsigned int mpixelrepetitioninput;
98 unsigned int mpixelrepetitionoutput;
99 unsigned int mtmdsclock;
100 };
101
102 struct hdmi_data_info {
103 unsigned int enc_in_bus_format;
104 unsigned int enc_out_bus_format;
105 unsigned int enc_in_encoding;
106 unsigned int enc_out_encoding;
107 unsigned int pix_repet_factor;
108 unsigned int hdcp_enable;
109 struct hdmi_vmode video_mode;
110 };
111
112 struct dw_hdmi_i2c {
113 struct i2c_adapter adap;
114
115 struct mutex lock;
116 struct completion cmp;
117 u8 stat;
118
119 u8 slave_reg;
120 bool is_regaddr;
121 bool is_segment;
122 };
123
124 struct dw_hdmi_phy_data {
125 enum dw_hdmi_phy_type type;
126 const char *name;
127 unsigned int gen;
128 bool has_svsret;
129 int (*configure)(struct dw_hdmi *hdmi,
130 const struct dw_hdmi_plat_data *pdata,
131 unsigned long mpixelclock);
132 };
133
134 struct dw_hdmi {
135 struct drm_connector connector;
136 struct drm_bridge bridge;
137
138 unsigned int version;
139
140 struct platform_device *audio;
141 struct platform_device *cec;
142 struct device *dev;
143 struct clk *isfr_clk;
144 struct clk *iahb_clk;
145 struct clk *cec_clk;
146 struct dw_hdmi_i2c *i2c;
147
148 struct hdmi_data_info hdmi_data;
149 const struct dw_hdmi_plat_data *plat_data;
150
151 int vic;
152
153 u8 edid[HDMI_EDID_LEN];
154
155 struct {
156 const struct dw_hdmi_phy_ops *ops;
157 const char *name;
158 void *data;
159 bool enabled;
160 } phy;
161
162 struct drm_display_mode previous_mode;
163
164 struct i2c_adapter *ddc;
165 void __iomem *regs;
166 bool sink_is_hdmi;
167 bool sink_has_audio;
168
169 struct pinctrl *pinctrl;
170 struct pinctrl_state *default_state;
171 struct pinctrl_state *unwedge_state;
172
173 struct mutex mutex;
174 enum drm_connector_force force;
175 bool disabled;
176 bool bridge_is_on;
177 bool rxsense;
178 u8 phy_mask;
179 u8 mc_clkdis;
180
181 spinlock_t audio_lock;
182 struct mutex audio_mutex;
183 unsigned int sample_rate;
184 unsigned int audio_cts;
185 unsigned int audio_n;
186 bool audio_enable;
187
188 unsigned int reg_shift;
189 struct regmap *regm;
190 void (*enable_audio)(struct dw_hdmi *hdmi);
191 void (*disable_audio)(struct dw_hdmi *hdmi);
192
193 struct mutex cec_notifier_mutex;
194 struct cec_notifier *cec_notifier;
195 };
196
197 #define HDMI_IH_PHY_STAT0_RX_SENSE \
198 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
199 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
200
201 #define HDMI_PHY_RX_SENSE \
202 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
203 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
204
205 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
206 {
207 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
208 }
209
210 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
211 {
212 unsigned int val = 0;
213
214 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
215
216 return val;
217 }
218
219 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
220 {
221 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
222 }
223
224 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
225 u8 shift, u8 mask)
226 {
227 hdmi_modb(hdmi, data << shift, mask, reg);
228 }
229
230 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
231 {
232 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
233 HDMI_PHY_I2CM_INT_ADDR);
234
235 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
236 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
237 HDMI_PHY_I2CM_CTLINT_ADDR);
238
239
240 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
241
242
243 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
244
245
246 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
247 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
248 HDMI_I2CM_CTLINT);
249
250
251 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
252 HDMI_IH_I2CM_STAT0);
253
254
255 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
256 HDMI_IH_MUTE_I2CM_STAT0);
257 }
258
259 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
260 {
261
262 if (!hdmi->unwedge_state)
263 return false;
264
265 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
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298
299 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
300 msleep(10);
301 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
302
303 return true;
304 }
305
306 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
307 {
308 struct dw_hdmi_i2c *i2c = hdmi->i2c;
309 int stat;
310
311 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
312 if (!stat) {
313
314 if (!dw_hdmi_i2c_unwedge(hdmi))
315 return -EAGAIN;
316
317
318 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
319 if (!stat)
320 return -EAGAIN;
321 }
322
323
324 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
325 return -EIO;
326
327 return 0;
328 }
329
330 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
331 unsigned char *buf, unsigned int length)
332 {
333 struct dw_hdmi_i2c *i2c = hdmi->i2c;
334 int ret;
335
336 if (!i2c->is_regaddr) {
337 dev_dbg(hdmi->dev, "set read register address to 0\n");
338 i2c->slave_reg = 0x00;
339 i2c->is_regaddr = true;
340 }
341
342 while (length--) {
343 reinit_completion(&i2c->cmp);
344
345 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
346 if (i2c->is_segment)
347 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
348 HDMI_I2CM_OPERATION);
349 else
350 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
351 HDMI_I2CM_OPERATION);
352
353 ret = dw_hdmi_i2c_wait(hdmi);
354 if (ret)
355 return ret;
356
357 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
358 }
359 i2c->is_segment = false;
360
361 return 0;
362 }
363
364 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
365 unsigned char *buf, unsigned int length)
366 {
367 struct dw_hdmi_i2c *i2c = hdmi->i2c;
368 int ret;
369
370 if (!i2c->is_regaddr) {
371
372 i2c->slave_reg = buf[0];
373 length--;
374 buf++;
375 i2c->is_regaddr = true;
376 }
377
378 while (length--) {
379 reinit_completion(&i2c->cmp);
380
381 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
382 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
383 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
384 HDMI_I2CM_OPERATION);
385
386 ret = dw_hdmi_i2c_wait(hdmi);
387 if (ret)
388 return ret;
389 }
390
391 return 0;
392 }
393
394 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
395 struct i2c_msg *msgs, int num)
396 {
397 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
398 struct dw_hdmi_i2c *i2c = hdmi->i2c;
399 u8 addr = msgs[0].addr;
400 int i, ret = 0;
401
402 if (addr == DDC_CI_ADDR)
403
404
405
406
407
408
409 return -EOPNOTSUPP;
410
411 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
412
413 for (i = 0; i < num; i++) {
414 if (msgs[i].len == 0) {
415 dev_dbg(hdmi->dev,
416 "unsupported transfer %d/%d, no data\n",
417 i + 1, num);
418 return -EOPNOTSUPP;
419 }
420 }
421
422 mutex_lock(&i2c->lock);
423
424
425 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
426
427
428 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
429
430
431 i2c->is_regaddr = false;
432
433
434 i2c->is_segment = false;
435
436 for (i = 0; i < num; i++) {
437 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
438 i + 1, num, msgs[i].len, msgs[i].flags);
439 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
440 i2c->is_segment = true;
441 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
442 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
443 } else {
444 if (msgs[i].flags & I2C_M_RD)
445 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
446 msgs[i].len);
447 else
448 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
449 msgs[i].len);
450 }
451 if (ret < 0)
452 break;
453 }
454
455 if (!ret)
456 ret = num;
457
458
459 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
460 HDMI_IH_MUTE_I2CM_STAT0);
461
462 mutex_unlock(&i2c->lock);
463
464 return ret;
465 }
466
467 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
468 {
469 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
470 }
471
472 static const struct i2c_algorithm dw_hdmi_algorithm = {
473 .master_xfer = dw_hdmi_i2c_xfer,
474 .functionality = dw_hdmi_i2c_func,
475 };
476
477 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
478 {
479 struct i2c_adapter *adap;
480 struct dw_hdmi_i2c *i2c;
481 int ret;
482
483 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
484 if (!i2c)
485 return ERR_PTR(-ENOMEM);
486
487 mutex_init(&i2c->lock);
488 init_completion(&i2c->cmp);
489
490 adap = &i2c->adap;
491 adap->class = I2C_CLASS_DDC;
492 adap->owner = THIS_MODULE;
493 adap->dev.parent = hdmi->dev;
494 adap->algo = &dw_hdmi_algorithm;
495 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
496 i2c_set_adapdata(adap, hdmi);
497
498 ret = i2c_add_adapter(adap);
499 if (ret) {
500 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
501 devm_kfree(hdmi->dev, i2c);
502 return ERR_PTR(ret);
503 }
504
505 hdmi->i2c = i2c;
506
507 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
508
509 return adap;
510 }
511
512 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
513 unsigned int n)
514 {
515
516 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
517
518
519 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
520
521
522 if (cts)
523 hdmi_writeb(hdmi, ((cts >> 16) &
524 HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
525 HDMI_AUD_CTS3_CTS_MANUAL,
526 HDMI_AUD_CTS3);
527 else
528 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
529 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
530 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
531
532 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
533 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
534 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
535 }
536
537 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
538 {
539 unsigned int n = (128 * freq) / 1000;
540 unsigned int mult = 1;
541
542 while (freq > 48000) {
543 mult *= 2;
544 freq /= 2;
545 }
546
547 switch (freq) {
548 case 32000:
549 if (pixel_clk == 25175000)
550 n = 4576;
551 else if (pixel_clk == 27027000)
552 n = 4096;
553 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
554 n = 11648;
555 else
556 n = 4096;
557 n *= mult;
558 break;
559
560 case 44100:
561 if (pixel_clk == 25175000)
562 n = 7007;
563 else if (pixel_clk == 74176000)
564 n = 17836;
565 else if (pixel_clk == 148352000)
566 n = 8918;
567 else
568 n = 6272;
569 n *= mult;
570 break;
571
572 case 48000:
573 if (pixel_clk == 25175000)
574 n = 6864;
575 else if (pixel_clk == 27027000)
576 n = 6144;
577 else if (pixel_clk == 74176000)
578 n = 11648;
579 else if (pixel_clk == 148352000)
580 n = 5824;
581 else
582 n = 6144;
583 n *= mult;
584 break;
585
586 default:
587 break;
588 }
589
590 return n;
591 }
592
593 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
594 unsigned long pixel_clk, unsigned int sample_rate)
595 {
596 unsigned long ftdms = pixel_clk;
597 unsigned int n, cts;
598 u8 config3;
599 u64 tmp;
600
601 n = hdmi_compute_n(sample_rate, pixel_clk);
602
603 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
604
605
606 if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
607
608
609
610
611
612
613
614 tmp = (u64)ftdms * n;
615 do_div(tmp, 128 * sample_rate);
616 cts = tmp;
617
618 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
619 __func__, sample_rate,
620 ftdms / 1000000, (ftdms / 1000) % 1000,
621 n, cts);
622 } else {
623 cts = 0;
624 }
625
626 spin_lock_irq(&hdmi->audio_lock);
627 hdmi->audio_n = n;
628 hdmi->audio_cts = cts;
629 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
630 spin_unlock_irq(&hdmi->audio_lock);
631 }
632
633 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
634 {
635 mutex_lock(&hdmi->audio_mutex);
636 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
637 mutex_unlock(&hdmi->audio_mutex);
638 }
639
640 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
641 {
642 mutex_lock(&hdmi->audio_mutex);
643 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
644 hdmi->sample_rate);
645 mutex_unlock(&hdmi->audio_mutex);
646 }
647
648 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
649 {
650 mutex_lock(&hdmi->audio_mutex);
651 hdmi->sample_rate = rate;
652 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
653 hdmi->sample_rate);
654 mutex_unlock(&hdmi->audio_mutex);
655 }
656 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
657
658 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
659 {
660 u8 layout;
661
662 mutex_lock(&hdmi->audio_mutex);
663
664
665
666
667
668 if (cnt > 2)
669 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
670 else
671 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
672
673 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
674 HDMI_FC_AUDSCONF);
675
676
677 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
678 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
679
680 mutex_unlock(&hdmi->audio_mutex);
681 }
682 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
683
684 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
685 {
686 mutex_lock(&hdmi->audio_mutex);
687
688 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
689
690 mutex_unlock(&hdmi->audio_mutex);
691 }
692 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
693
694 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
695 {
696 if (enable)
697 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
698 else
699 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
700 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
701 }
702
703 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
704 {
705 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
706 }
707
708 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
709 {
710 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
711 }
712
713 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
714 {
715 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
716 hdmi_enable_audio_clk(hdmi, true);
717 }
718
719 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
720 {
721 hdmi_enable_audio_clk(hdmi, false);
722 }
723
724 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
725 {
726 unsigned long flags;
727
728 spin_lock_irqsave(&hdmi->audio_lock, flags);
729 hdmi->audio_enable = true;
730 if (hdmi->enable_audio)
731 hdmi->enable_audio(hdmi);
732 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
733 }
734 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
735
736 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
737 {
738 unsigned long flags;
739
740 spin_lock_irqsave(&hdmi->audio_lock, flags);
741 hdmi->audio_enable = false;
742 if (hdmi->disable_audio)
743 hdmi->disable_audio(hdmi);
744 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
745 }
746 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
747
748 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
749 {
750 switch (bus_format) {
751 case MEDIA_BUS_FMT_RGB888_1X24:
752 case MEDIA_BUS_FMT_RGB101010_1X30:
753 case MEDIA_BUS_FMT_RGB121212_1X36:
754 case MEDIA_BUS_FMT_RGB161616_1X48:
755 return true;
756
757 default:
758 return false;
759 }
760 }
761
762 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
763 {
764 switch (bus_format) {
765 case MEDIA_BUS_FMT_YUV8_1X24:
766 case MEDIA_BUS_FMT_YUV10_1X30:
767 case MEDIA_BUS_FMT_YUV12_1X36:
768 case MEDIA_BUS_FMT_YUV16_1X48:
769 return true;
770
771 default:
772 return false;
773 }
774 }
775
776 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
777 {
778 switch (bus_format) {
779 case MEDIA_BUS_FMT_UYVY8_1X16:
780 case MEDIA_BUS_FMT_UYVY10_1X20:
781 case MEDIA_BUS_FMT_UYVY12_1X24:
782 return true;
783
784 default:
785 return false;
786 }
787 }
788
789 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
790 {
791 switch (bus_format) {
792 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
793 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
794 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
795 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
796 return true;
797
798 default:
799 return false;
800 }
801 }
802
803 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
804 {
805 switch (bus_format) {
806 case MEDIA_BUS_FMT_RGB888_1X24:
807 case MEDIA_BUS_FMT_YUV8_1X24:
808 case MEDIA_BUS_FMT_UYVY8_1X16:
809 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
810 return 8;
811
812 case MEDIA_BUS_FMT_RGB101010_1X30:
813 case MEDIA_BUS_FMT_YUV10_1X30:
814 case MEDIA_BUS_FMT_UYVY10_1X20:
815 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
816 return 10;
817
818 case MEDIA_BUS_FMT_RGB121212_1X36:
819 case MEDIA_BUS_FMT_YUV12_1X36:
820 case MEDIA_BUS_FMT_UYVY12_1X24:
821 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
822 return 12;
823
824 case MEDIA_BUS_FMT_RGB161616_1X48:
825 case MEDIA_BUS_FMT_YUV16_1X48:
826 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
827 return 16;
828
829 default:
830 return 0;
831 }
832 }
833
834
835
836
837
838
839
840
841 static void hdmi_video_sample(struct dw_hdmi *hdmi)
842 {
843 int color_format = 0;
844 u8 val;
845
846 switch (hdmi->hdmi_data.enc_in_bus_format) {
847 case MEDIA_BUS_FMT_RGB888_1X24:
848 color_format = 0x01;
849 break;
850 case MEDIA_BUS_FMT_RGB101010_1X30:
851 color_format = 0x03;
852 break;
853 case MEDIA_BUS_FMT_RGB121212_1X36:
854 color_format = 0x05;
855 break;
856 case MEDIA_BUS_FMT_RGB161616_1X48:
857 color_format = 0x07;
858 break;
859
860 case MEDIA_BUS_FMT_YUV8_1X24:
861 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
862 color_format = 0x09;
863 break;
864 case MEDIA_BUS_FMT_YUV10_1X30:
865 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
866 color_format = 0x0B;
867 break;
868 case MEDIA_BUS_FMT_YUV12_1X36:
869 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
870 color_format = 0x0D;
871 break;
872 case MEDIA_BUS_FMT_YUV16_1X48:
873 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
874 color_format = 0x0F;
875 break;
876
877 case MEDIA_BUS_FMT_UYVY8_1X16:
878 color_format = 0x16;
879 break;
880 case MEDIA_BUS_FMT_UYVY10_1X20:
881 color_format = 0x14;
882 break;
883 case MEDIA_BUS_FMT_UYVY12_1X24:
884 color_format = 0x12;
885 break;
886
887 default:
888 return;
889 }
890
891 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
892 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
893 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
894 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
895
896
897 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
898 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
899 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
900 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
901 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
902 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
903 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
904 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
905 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
906 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
907 }
908
909 static int is_color_space_conversion(struct dw_hdmi *hdmi)
910 {
911 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
912 }
913
914 static int is_color_space_decimation(struct dw_hdmi *hdmi)
915 {
916 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
917 return 0;
918
919 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
920 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
921 return 1;
922
923 return 0;
924 }
925
926 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
927 {
928 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
929 return 0;
930
931 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
932 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
933 return 1;
934
935 return 0;
936 }
937
938 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
939 {
940 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
941 unsigned i;
942 u32 csc_scale = 1;
943
944 if (is_color_space_conversion(hdmi)) {
945 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
946 if (hdmi->hdmi_data.enc_out_encoding ==
947 V4L2_YCBCR_ENC_601)
948 csc_coeff = &csc_coeff_rgb_out_eitu601;
949 else
950 csc_coeff = &csc_coeff_rgb_out_eitu709;
951 } else if (hdmi_bus_fmt_is_rgb(
952 hdmi->hdmi_data.enc_in_bus_format)) {
953 if (hdmi->hdmi_data.enc_out_encoding ==
954 V4L2_YCBCR_ENC_601)
955 csc_coeff = &csc_coeff_rgb_in_eitu601;
956 else
957 csc_coeff = &csc_coeff_rgb_in_eitu709;
958 csc_scale = 0;
959 }
960 }
961
962
963 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
964 u16 coeff_a = (*csc_coeff)[0][i];
965 u16 coeff_b = (*csc_coeff)[1][i];
966 u16 coeff_c = (*csc_coeff)[2][i];
967
968 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
969 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
970 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
971 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
972 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
973 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
974 }
975
976 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
977 HDMI_CSC_SCALE);
978 }
979
980 static void hdmi_video_csc(struct dw_hdmi *hdmi)
981 {
982 int color_depth = 0;
983 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
984 int decimation = 0;
985
986
987 if (is_color_space_interpolation(hdmi))
988 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
989 else if (is_color_space_decimation(hdmi))
990 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
991
992 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
993 case 8:
994 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
995 break;
996 case 10:
997 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
998 break;
999 case 12:
1000 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1001 break;
1002 case 16:
1003 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1004 break;
1005
1006 default:
1007 return;
1008 }
1009
1010
1011 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1012 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1013 HDMI_CSC_SCALE);
1014
1015 dw_hdmi_update_csc_coeffs(hdmi);
1016 }
1017
1018
1019
1020
1021
1022
1023 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1024 {
1025 unsigned int color_depth = 0;
1026 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1027 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1028 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1029 u8 val, vp_conf;
1030
1031 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1032 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1033 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1034 switch (hdmi_bus_fmt_color_depth(
1035 hdmi->hdmi_data.enc_out_bus_format)) {
1036 case 8:
1037 color_depth = 4;
1038 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1039 break;
1040 case 10:
1041 color_depth = 5;
1042 break;
1043 case 12:
1044 color_depth = 6;
1045 break;
1046 case 16:
1047 color_depth = 7;
1048 break;
1049 default:
1050 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1051 }
1052 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1053 switch (hdmi_bus_fmt_color_depth(
1054 hdmi->hdmi_data.enc_out_bus_format)) {
1055 case 0:
1056 case 8:
1057 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1058 break;
1059 case 10:
1060 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1061 break;
1062 case 12:
1063 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1064 break;
1065
1066 default:
1067 return;
1068 }
1069 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1070 } else {
1071 return;
1072 }
1073
1074
1075 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1076 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1077 ((hdmi_data->pix_repet_factor <<
1078 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1079 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1080 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1081
1082 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1083 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1084
1085
1086 if (hdmi_data->pix_repet_factor > 1) {
1087 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1088 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1089 } else {
1090 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1091 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1092 }
1093
1094 hdmi_modb(hdmi, vp_conf,
1095 HDMI_VP_CONF_PR_EN_MASK |
1096 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1097
1098 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1099 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1100
1101 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1102
1103 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1104 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1105 HDMI_VP_CONF_PP_EN_ENABLE |
1106 HDMI_VP_CONF_YCC422_EN_DISABLE;
1107 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1108 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1109 HDMI_VP_CONF_PP_EN_DISABLE |
1110 HDMI_VP_CONF_YCC422_EN_ENABLE;
1111 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1112 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1113 HDMI_VP_CONF_PP_EN_DISABLE |
1114 HDMI_VP_CONF_YCC422_EN_DISABLE;
1115 } else {
1116 return;
1117 }
1118
1119 hdmi_modb(hdmi, vp_conf,
1120 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1121 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1122
1123 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1124 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1125 HDMI_VP_STUFF_PP_STUFFING_MASK |
1126 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1127
1128 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1129 HDMI_VP_CONF);
1130 }
1131
1132
1133
1134
1135
1136 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1137 unsigned char bit)
1138 {
1139 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1140 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1141 }
1142
1143 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1144 {
1145 u32 val;
1146
1147 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1148 if (msec-- == 0)
1149 return false;
1150 udelay(1000);
1151 }
1152 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1153
1154 return true;
1155 }
1156
1157 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1158 unsigned char addr)
1159 {
1160 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1161 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1162 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1163 HDMI_PHY_I2CM_DATAO_1_ADDR);
1164 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1165 HDMI_PHY_I2CM_DATAO_0_ADDR);
1166 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1167 HDMI_PHY_I2CM_OPERATION_ADDR);
1168 hdmi_phy_wait_i2c_done(hdmi, 1000);
1169 }
1170 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1171
1172
1173 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1174 {
1175 struct drm_display_info *display = &hdmi->connector.display_info;
1176
1177
1178 if (hdmi->version < 0x200a)
1179 return false;
1180
1181
1182 if (!hdmi->ddc)
1183 return false;
1184
1185
1186 if (!display->hdmi.scdc.supported ||
1187 !display->hdmi.scdc.scrambling.supported)
1188 return false;
1189
1190
1191
1192
1193
1194 if (!display->hdmi.scdc.scrambling.low_rates &&
1195 display->max_tmds_clock <= 340000)
1196 return false;
1197
1198 return true;
1199 }
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1215 {
1216 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1217
1218
1219 if (dw_hdmi_support_scdc(hdmi)) {
1220 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1221 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1222 else
1223 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1224 }
1225 }
1226 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1227
1228 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1229 {
1230 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1231 HDMI_PHY_CONF0_PDZ_OFFSET,
1232 HDMI_PHY_CONF0_PDZ_MASK);
1233 }
1234
1235 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1236 {
1237 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1238 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1239 HDMI_PHY_CONF0_ENTMDS_MASK);
1240 }
1241
1242 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1243 {
1244 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1245 HDMI_PHY_CONF0_SVSRET_OFFSET,
1246 HDMI_PHY_CONF0_SVSRET_MASK);
1247 }
1248
1249 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1250 {
1251 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1252 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1253 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1254 }
1255 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1256
1257 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1258 {
1259 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1260 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1261 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1262 }
1263 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1264
1265 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1266 {
1267 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1268 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1269 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1270 }
1271
1272 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1273 {
1274 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1275 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1276 HDMI_PHY_CONF0_SELDIPIF_MASK);
1277 }
1278
1279 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1280 {
1281
1282 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1283 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1284 }
1285 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1286
1287 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1288 {
1289 hdmi_phy_test_clear(hdmi, 1);
1290 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1291 hdmi_phy_test_clear(hdmi, 0);
1292 }
1293 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1294
1295 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1296 {
1297 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1298 unsigned int i;
1299 u16 val;
1300
1301 if (phy->gen == 1) {
1302 dw_hdmi_phy_enable_tmds(hdmi, 0);
1303 dw_hdmi_phy_enable_powerdown(hdmi, true);
1304 return;
1305 }
1306
1307 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1308
1309
1310
1311
1312
1313 for (i = 0; i < 5; ++i) {
1314 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1315 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1316 break;
1317
1318 usleep_range(1000, 2000);
1319 }
1320
1321 if (val & HDMI_PHY_TX_PHY_LOCK)
1322 dev_warn(hdmi->dev, "PHY failed to power down\n");
1323 else
1324 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1325
1326 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1327 }
1328
1329 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1330 {
1331 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1332 unsigned int i;
1333 u8 val;
1334
1335 if (phy->gen == 1) {
1336 dw_hdmi_phy_enable_powerdown(hdmi, false);
1337
1338
1339 dw_hdmi_phy_enable_tmds(hdmi, 0);
1340 dw_hdmi_phy_enable_tmds(hdmi, 1);
1341 return 0;
1342 }
1343
1344 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1345 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1346
1347
1348 for (i = 0; i < 5; ++i) {
1349 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1350 if (val)
1351 break;
1352
1353 usleep_range(1000, 2000);
1354 }
1355
1356 if (!val) {
1357 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1358 return -ETIMEDOUT;
1359 }
1360
1361 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1362 return 0;
1363 }
1364
1365
1366
1367
1368
1369
1370 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1371 const struct dw_hdmi_plat_data *pdata,
1372 unsigned long mpixelclock)
1373 {
1374 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1375 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1376 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1377
1378
1379
1380
1381 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1382 if (mpixelclock <= mpll_config->mpixelclock)
1383 break;
1384
1385 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1386 if (mpixelclock <= curr_ctrl->mpixelclock)
1387 break;
1388
1389 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1390 if (mpixelclock <= phy_config->mpixelclock)
1391 break;
1392
1393 if (mpll_config->mpixelclock == ~0UL ||
1394 curr_ctrl->mpixelclock == ~0UL ||
1395 phy_config->mpixelclock == ~0UL)
1396 return -EINVAL;
1397
1398 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1399 HDMI_3D_TX_PHY_CPCE_CTRL);
1400 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1401 HDMI_3D_TX_PHY_GMPCTRL);
1402 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1403 HDMI_3D_TX_PHY_CURRCTRL);
1404
1405 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1406 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1407 HDMI_3D_TX_PHY_MSM_CTRL);
1408
1409 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1410 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1411 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1412 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1413 HDMI_3D_TX_PHY_VLEVCTRL);
1414
1415
1416 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1417 HDMI_3D_TX_PHY_CKCALCTRL);
1418
1419 return 0;
1420 }
1421
1422 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1423 {
1424 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1425 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1426 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1427 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1428 int ret;
1429
1430 dw_hdmi_phy_power_off(hdmi);
1431
1432 dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1433
1434
1435 if (phy->has_svsret)
1436 dw_hdmi_phy_enable_svsret(hdmi, 1);
1437
1438 dw_hdmi_phy_reset(hdmi);
1439
1440 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1441
1442 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1443
1444
1445 if (pdata->configure_phy)
1446 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1447 else
1448 ret = phy->configure(hdmi, pdata, mpixelclock);
1449 if (ret) {
1450 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1451 mpixelclock);
1452 return ret;
1453 }
1454
1455
1456 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1457 msleep(100);
1458
1459 return dw_hdmi_phy_power_on(hdmi);
1460 }
1461
1462 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1463 struct drm_display_mode *mode)
1464 {
1465 int i, ret;
1466
1467
1468 for (i = 0; i < 2; i++) {
1469 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1470 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1471
1472 ret = hdmi_phy_configure(hdmi);
1473 if (ret)
1474 return ret;
1475 }
1476
1477 return 0;
1478 }
1479
1480 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1481 {
1482 dw_hdmi_phy_power_off(hdmi);
1483 }
1484
1485 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1486 void *data)
1487 {
1488 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1489 connector_status_connected : connector_status_disconnected;
1490 }
1491 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1492
1493 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1494 bool force, bool disabled, bool rxsense)
1495 {
1496 u8 old_mask = hdmi->phy_mask;
1497
1498 if (force || disabled || !rxsense)
1499 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1500 else
1501 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1502
1503 if (old_mask != hdmi->phy_mask)
1504 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1505 }
1506 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1507
1508 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1509 {
1510
1511
1512
1513
1514 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1515 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1516 HDMI_IH_PHY_STAT0);
1517
1518
1519 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1520
1521
1522 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1523 HDMI_IH_PHY_STAT0);
1524 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1525 HDMI_IH_MUTE_PHY_STAT0);
1526 }
1527 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1528
1529 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1530 .init = dw_hdmi_phy_init,
1531 .disable = dw_hdmi_phy_disable,
1532 .read_hpd = dw_hdmi_phy_read_hpd,
1533 .update_hpd = dw_hdmi_phy_update_hpd,
1534 .setup_hpd = dw_hdmi_phy_setup_hpd,
1535 };
1536
1537
1538
1539
1540
1541 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1542 {
1543 u8 de;
1544
1545 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1546 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1547 else
1548 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1549
1550
1551 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1552 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1553
1554 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1555
1556 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1557 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1558 }
1559
1560 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1561 {
1562 struct hdmi_avi_infoframe frame;
1563 u8 val;
1564
1565
1566 drm_hdmi_avi_infoframe_from_display_mode(&frame,
1567 &hdmi->connector, mode);
1568
1569 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1570 frame.colorspace = HDMI_COLORSPACE_YUV444;
1571 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1572 frame.colorspace = HDMI_COLORSPACE_YUV422;
1573 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1574 frame.colorspace = HDMI_COLORSPACE_YUV420;
1575 else
1576 frame.colorspace = HDMI_COLORSPACE_RGB;
1577
1578
1579 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1580 switch (hdmi->hdmi_data.enc_out_encoding) {
1581 case V4L2_YCBCR_ENC_601:
1582 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1583 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1584 else
1585 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1586 frame.extended_colorimetry =
1587 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1588 break;
1589 case V4L2_YCBCR_ENC_709:
1590 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1591 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1592 else
1593 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1594 frame.extended_colorimetry =
1595 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1596 break;
1597 default:
1598 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1599 frame.extended_colorimetry =
1600 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1601 break;
1602 }
1603 } else {
1604 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1605 frame.extended_colorimetry =
1606 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1607 }
1608
1609 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1623 if (frame.active_aspect & 15)
1624 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1625 if (frame.top_bar || frame.bottom_bar)
1626 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1627 if (frame.left_bar || frame.right_bar)
1628 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1629 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1630
1631
1632 val = ((frame.colorimetry & 0x3) << 6) |
1633 ((frame.picture_aspect & 0x3) << 4) |
1634 (frame.active_aspect & 0xf);
1635 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1636
1637
1638 val = ((frame.extended_colorimetry & 0x7) << 4) |
1639 ((frame.quantization_range & 0x3) << 2) |
1640 (frame.nups & 0x3);
1641 if (frame.itc)
1642 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1643 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1644
1645
1646 val = frame.video_code & 0x7f;
1647 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1648
1649
1650 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1651 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1652 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1653 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1654 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1655 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1656 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1657
1658
1659
1660
1661
1662 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1663 (frame.content_type & 0x3);
1664 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1665
1666
1667 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1668 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1669 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1670 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1671 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1672 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1673 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1674 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1675 }
1676
1677 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1678 struct drm_display_mode *mode)
1679 {
1680 struct hdmi_vendor_infoframe frame;
1681 u8 buffer[10];
1682 ssize_t err;
1683
1684 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1685 &hdmi->connector,
1686 mode);
1687 if (err < 0)
1688
1689
1690
1691
1692
1693
1694 return;
1695
1696 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1697 if (err < 0) {
1698 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1699 err);
1700 return;
1701 }
1702 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1703 HDMI_FC_DATAUTO0_VSD_MASK);
1704
1705
1706 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1707
1708
1709 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1710 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1711 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1712
1713
1714 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1715 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1716
1717 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1718 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1719
1720
1721 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1722
1723
1724 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1725
1726
1727 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1728 HDMI_FC_DATAUTO0_VSD_MASK);
1729 }
1730
1731 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1732 const struct drm_display_mode *mode)
1733 {
1734 u8 inv_val, bytes;
1735 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
1736 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1737 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1738 unsigned int vdisplay, hdisplay;
1739
1740 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
1741
1742 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1743
1744 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1745 vmode->mtmdsclock /= 2;
1746
1747
1748 inv_val = (hdmi->hdmi_data.hdcp_enable ||
1749 (dw_hdmi_support_scdc(hdmi) &&
1750 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1751 hdmi_info->scdc.scrambling.low_rates)) ?
1752 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1753 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1754
1755 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1756 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1757 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1758
1759 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1760 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1761 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1762
1763 inv_val |= (vmode->mdataenablepolarity ?
1764 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1765 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1766
1767 if (hdmi->vic == 39)
1768 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1769 else
1770 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1771 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1772 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1773
1774 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1775 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1776 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1777
1778 inv_val |= hdmi->sink_is_hdmi ?
1779 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1780 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1781
1782 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1783
1784 hdisplay = mode->hdisplay;
1785 hblank = mode->htotal - mode->hdisplay;
1786 h_de_hs = mode->hsync_start - mode->hdisplay;
1787 hsync_len = mode->hsync_end - mode->hsync_start;
1788
1789
1790
1791
1792
1793 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1794 hdisplay /= 2;
1795 hblank /= 2;
1796 h_de_hs /= 2;
1797 hsync_len /= 2;
1798 }
1799
1800 vdisplay = mode->vdisplay;
1801 vblank = mode->vtotal - mode->vdisplay;
1802 v_de_vs = mode->vsync_start - mode->vdisplay;
1803 vsync_len = mode->vsync_end - mode->vsync_start;
1804
1805
1806
1807
1808
1809 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1810 vdisplay /= 2;
1811 vblank /= 2;
1812 v_de_vs /= 2;
1813 vsync_len /= 2;
1814 }
1815
1816
1817 if (dw_hdmi_support_scdc(hdmi)) {
1818 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1819 hdmi_info->scdc.scrambling.low_rates) {
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1830 &bytes);
1831 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1832 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1833
1834
1835 drm_scdc_set_scrambling(hdmi->ddc, 1);
1836
1837
1838
1839
1840
1841
1842
1843
1844 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1845 HDMI_MC_SWRSTZ);
1846 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1847 } else {
1848 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1849 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1850 HDMI_MC_SWRSTZ);
1851 drm_scdc_set_scrambling(hdmi->ddc, 0);
1852 }
1853 }
1854
1855
1856 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1857 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1858
1859
1860 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1861 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1862
1863
1864 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1865 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1866
1867
1868 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1869
1870
1871 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1872 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1873
1874
1875 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1876
1877
1878 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1879 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1880
1881
1882 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1883 }
1884
1885
1886 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1887 {
1888
1889 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1890 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1891 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1892
1893
1894 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1895 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1896 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1897
1898
1899 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1900 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1901 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1902 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1903 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1904 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1905 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1906
1907 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1908 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1909
1910
1911 if (is_color_space_conversion(hdmi)) {
1912 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1913 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1914 }
1915
1916
1917 if (is_color_space_conversion(hdmi))
1918 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1919 HDMI_MC_FLOWCTRL);
1920 else
1921 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1922 HDMI_MC_FLOWCTRL);
1923 }
1924
1925
1926 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1927 {
1928 unsigned int count;
1929 unsigned int i;
1930 u8 val;
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949 switch (hdmi->version) {
1950 case 0x130a:
1951 count = 4;
1952 break;
1953 case 0x131a:
1954 case 0x132a:
1955 case 0x200a:
1956 case 0x201a:
1957 case 0x211a:
1958 case 0x212a:
1959 count = 1;
1960 break;
1961 default:
1962 return;
1963 }
1964
1965
1966 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1967
1968 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1969 for (i = 0; i < count; i++)
1970 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1971 }
1972
1973 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1974 {
1975 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1976 HDMI_IH_MUTE_FC_STAT2);
1977 }
1978
1979 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1980 {
1981 int ret;
1982
1983 hdmi_disable_overflow_interrupts(hdmi);
1984
1985 hdmi->vic = drm_match_cea_mode(mode);
1986
1987 if (!hdmi->vic) {
1988 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1989 } else {
1990 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1991 }
1992
1993 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1994 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1995 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1996 (hdmi->vic == 17) || (hdmi->vic == 18))
1997 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1998 else
1999 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2000
2001 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2002 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2003
2004
2005 if (hdmi->plat_data->input_bus_format)
2006 hdmi->hdmi_data.enc_in_bus_format =
2007 hdmi->plat_data->input_bus_format;
2008 else
2009 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2010
2011
2012 if (hdmi->plat_data->input_bus_encoding)
2013 hdmi->hdmi_data.enc_in_encoding =
2014 hdmi->plat_data->input_bus_encoding;
2015 else
2016 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2017
2018
2019 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2020
2021 hdmi->hdmi_data.pix_repet_factor = 0;
2022 hdmi->hdmi_data.hdcp_enable = 0;
2023 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2024
2025
2026 hdmi_av_composer(hdmi, mode);
2027
2028
2029 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
2030 if (ret)
2031 return ret;
2032 hdmi->phy.enabled = true;
2033
2034
2035 dw_hdmi_enable_video_path(hdmi);
2036
2037 if (hdmi->sink_has_audio) {
2038 dev_dbg(hdmi->dev, "sink has audio support\n");
2039
2040
2041 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2042 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2043 }
2044
2045
2046 if (hdmi->sink_is_hdmi) {
2047 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2048
2049
2050 hdmi_config_AVI(hdmi, mode);
2051 hdmi_config_vendor_specific_infoframe(hdmi, mode);
2052 } else {
2053 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2054 }
2055
2056 hdmi_video_packetize(hdmi);
2057 hdmi_video_csc(hdmi);
2058 hdmi_video_sample(hdmi);
2059 hdmi_tx_hdcp_config(hdmi);
2060
2061 dw_hdmi_clear_overflow(hdmi);
2062
2063 return 0;
2064 }
2065
2066 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2067 {
2068 u8 ih_mute;
2069
2070
2071
2072
2073
2074
2075
2076
2077 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2078 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2079 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2080
2081 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2082
2083
2084 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2085 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2086 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2087 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2088 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2089 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2090 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2091 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2092 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2093 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2094 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2095 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2096 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2097 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2098
2099
2100 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2101 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2102 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2103 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2104 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2105 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2106 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2107 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2108 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2109 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2110
2111
2112 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2113 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2114 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2115 }
2116
2117 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2118 {
2119 hdmi->bridge_is_on = true;
2120 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
2121 }
2122
2123 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2124 {
2125 if (hdmi->phy.enabled) {
2126 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2127 hdmi->phy.enabled = false;
2128 }
2129
2130 hdmi->bridge_is_on = false;
2131 }
2132
2133 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2134 {
2135 int force = hdmi->force;
2136
2137 if (hdmi->disabled) {
2138 force = DRM_FORCE_OFF;
2139 } else if (force == DRM_FORCE_UNSPECIFIED) {
2140 if (hdmi->rxsense)
2141 force = DRM_FORCE_ON;
2142 else
2143 force = DRM_FORCE_OFF;
2144 }
2145
2146 if (force == DRM_FORCE_OFF) {
2147 if (hdmi->bridge_is_on)
2148 dw_hdmi_poweroff(hdmi);
2149 } else {
2150 if (!hdmi->bridge_is_on)
2151 dw_hdmi_poweron(hdmi);
2152 }
2153 }
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2168 {
2169 if (hdmi->phy.ops->update_hpd)
2170 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2171 hdmi->force, hdmi->disabled,
2172 hdmi->rxsense);
2173 }
2174
2175 static enum drm_connector_status
2176 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2177 {
2178 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2179 connector);
2180
2181 mutex_lock(&hdmi->mutex);
2182 hdmi->force = DRM_FORCE_UNSPECIFIED;
2183 dw_hdmi_update_power(hdmi);
2184 dw_hdmi_update_phy_mask(hdmi);
2185 mutex_unlock(&hdmi->mutex);
2186
2187 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2188 }
2189
2190 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2191 {
2192 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2193 connector);
2194 struct edid *edid;
2195 int ret = 0;
2196
2197 if (!hdmi->ddc)
2198 return 0;
2199
2200 edid = drm_get_edid(connector, hdmi->ddc);
2201 if (edid) {
2202 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2203 edid->width_cm, edid->height_cm);
2204
2205 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2206 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2207 drm_connector_update_edid_property(connector, edid);
2208 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2209 ret = drm_add_edid_modes(connector, edid);
2210 kfree(edid);
2211 } else {
2212 dev_dbg(hdmi->dev, "failed to get edid\n");
2213 }
2214
2215 return ret;
2216 }
2217
2218 static void dw_hdmi_connector_force(struct drm_connector *connector)
2219 {
2220 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2221 connector);
2222
2223 mutex_lock(&hdmi->mutex);
2224 hdmi->force = connector->force;
2225 dw_hdmi_update_power(hdmi);
2226 dw_hdmi_update_phy_mask(hdmi);
2227 mutex_unlock(&hdmi->mutex);
2228 }
2229
2230 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2231 .fill_modes = drm_helper_probe_single_connector_modes,
2232 .detect = dw_hdmi_connector_detect,
2233 .destroy = drm_connector_cleanup,
2234 .force = dw_hdmi_connector_force,
2235 .reset = drm_atomic_helper_connector_reset,
2236 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2237 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2238 };
2239
2240 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2241 .get_modes = dw_hdmi_connector_get_modes,
2242 };
2243
2244 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2245 {
2246 struct dw_hdmi *hdmi = bridge->driver_private;
2247 struct drm_encoder *encoder = bridge->encoder;
2248 struct drm_connector *connector = &hdmi->connector;
2249 struct cec_connector_info conn_info;
2250 struct cec_notifier *notifier;
2251
2252 connector->interlace_allowed = 1;
2253 connector->polled = DRM_CONNECTOR_POLL_HPD;
2254
2255 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2256
2257 drm_connector_init_with_ddc(bridge->dev, connector,
2258 &dw_hdmi_connector_funcs,
2259 DRM_MODE_CONNECTOR_HDMIA,
2260 hdmi->ddc);
2261
2262 drm_connector_attach_encoder(connector, encoder);
2263
2264 cec_fill_conn_info_from_drm(&conn_info, connector);
2265
2266 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2267 if (!notifier)
2268 return -ENOMEM;
2269
2270 mutex_lock(&hdmi->cec_notifier_mutex);
2271 hdmi->cec_notifier = notifier;
2272 mutex_unlock(&hdmi->cec_notifier_mutex);
2273
2274 return 0;
2275 }
2276
2277 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2278 {
2279 struct dw_hdmi *hdmi = bridge->driver_private;
2280
2281 mutex_lock(&hdmi->cec_notifier_mutex);
2282 cec_notifier_conn_unregister(hdmi->cec_notifier);
2283 hdmi->cec_notifier = NULL;
2284 mutex_unlock(&hdmi->cec_notifier_mutex);
2285 }
2286
2287 static enum drm_mode_status
2288 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2289 const struct drm_display_mode *mode)
2290 {
2291 struct dw_hdmi *hdmi = bridge->driver_private;
2292 struct drm_connector *connector = &hdmi->connector;
2293 enum drm_mode_status mode_status = MODE_OK;
2294
2295
2296 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2297 return MODE_BAD;
2298
2299 if (hdmi->plat_data->mode_valid)
2300 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2301
2302 return mode_status;
2303 }
2304
2305 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2306 const struct drm_display_mode *orig_mode,
2307 const struct drm_display_mode *mode)
2308 {
2309 struct dw_hdmi *hdmi = bridge->driver_private;
2310
2311 mutex_lock(&hdmi->mutex);
2312
2313
2314 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2315
2316 mutex_unlock(&hdmi->mutex);
2317 }
2318
2319 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2320 {
2321 struct dw_hdmi *hdmi = bridge->driver_private;
2322
2323 mutex_lock(&hdmi->mutex);
2324 hdmi->disabled = true;
2325 dw_hdmi_update_power(hdmi);
2326 dw_hdmi_update_phy_mask(hdmi);
2327 mutex_unlock(&hdmi->mutex);
2328 }
2329
2330 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2331 {
2332 struct dw_hdmi *hdmi = bridge->driver_private;
2333
2334 mutex_lock(&hdmi->mutex);
2335 hdmi->disabled = false;
2336 dw_hdmi_update_power(hdmi);
2337 dw_hdmi_update_phy_mask(hdmi);
2338 mutex_unlock(&hdmi->mutex);
2339 }
2340
2341 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2342 .attach = dw_hdmi_bridge_attach,
2343 .detach = dw_hdmi_bridge_detach,
2344 .enable = dw_hdmi_bridge_enable,
2345 .disable = dw_hdmi_bridge_disable,
2346 .mode_set = dw_hdmi_bridge_mode_set,
2347 .mode_valid = dw_hdmi_bridge_mode_valid,
2348 };
2349
2350 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2351 {
2352 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2353 unsigned int stat;
2354
2355 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2356 if (!stat)
2357 return IRQ_NONE;
2358
2359 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2360
2361 i2c->stat = stat;
2362
2363 complete(&i2c->cmp);
2364
2365 return IRQ_HANDLED;
2366 }
2367
2368 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2369 {
2370 struct dw_hdmi *hdmi = dev_id;
2371 u8 intr_stat;
2372 irqreturn_t ret = IRQ_NONE;
2373
2374 if (hdmi->i2c)
2375 ret = dw_hdmi_i2c_irq(hdmi);
2376
2377 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2378 if (intr_stat) {
2379 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2380 return IRQ_WAKE_THREAD;
2381 }
2382
2383 return ret;
2384 }
2385
2386 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2387 {
2388 mutex_lock(&hdmi->mutex);
2389
2390 if (!hdmi->force) {
2391
2392
2393
2394
2395 if (!rx_sense)
2396 hdmi->rxsense = false;
2397
2398
2399
2400
2401
2402
2403
2404 if (hpd)
2405 hdmi->rxsense = true;
2406
2407 dw_hdmi_update_power(hdmi);
2408 dw_hdmi_update_phy_mask(hdmi);
2409 }
2410 mutex_unlock(&hdmi->mutex);
2411 }
2412 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2413
2414 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2415 {
2416 struct dw_hdmi *hdmi = dev_id;
2417 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2418
2419 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2420 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2421 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2422
2423 phy_pol_mask = 0;
2424 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2425 phy_pol_mask |= HDMI_PHY_HPD;
2426 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2427 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2428 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2429 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2430 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2431 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2432 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2433 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2434
2435 if (phy_pol_mask)
2436 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2437
2438
2439
2440
2441
2442
2443
2444
2445 if (intr_stat &
2446 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2447 dw_hdmi_setup_rx_sense(hdmi,
2448 phy_stat & HDMI_PHY_HPD,
2449 phy_stat & HDMI_PHY_RX_SENSE);
2450
2451 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
2452 mutex_lock(&hdmi->cec_notifier_mutex);
2453 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
2454 mutex_unlock(&hdmi->cec_notifier_mutex);
2455 }
2456 }
2457
2458 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2459 dev_dbg(hdmi->dev, "EVENT=%s\n",
2460 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2461 if (hdmi->bridge.dev)
2462 drm_helper_hpd_irq_event(hdmi->bridge.dev);
2463 }
2464
2465 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2466 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2467 HDMI_IH_MUTE_PHY_STAT0);
2468
2469 return IRQ_HANDLED;
2470 }
2471
2472 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2473 {
2474 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2475 .name = "DWC HDMI TX PHY",
2476 .gen = 1,
2477 }, {
2478 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2479 .name = "DWC MHL PHY + HEAC PHY",
2480 .gen = 2,
2481 .has_svsret = true,
2482 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2483 }, {
2484 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2485 .name = "DWC MHL PHY",
2486 .gen = 2,
2487 .has_svsret = true,
2488 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2489 }, {
2490 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2491 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2492 .gen = 2,
2493 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2494 }, {
2495 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2496 .name = "DWC HDMI 3D TX PHY",
2497 .gen = 2,
2498 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2499 }, {
2500 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2501 .name = "DWC HDMI 2.0 TX PHY",
2502 .gen = 2,
2503 .has_svsret = true,
2504 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2505 }, {
2506 .type = DW_HDMI_PHY_VENDOR_PHY,
2507 .name = "Vendor PHY",
2508 }
2509 };
2510
2511 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2512 {
2513 unsigned int i;
2514 u8 phy_type;
2515
2516 phy_type = hdmi->plat_data->phy_force_vendor ?
2517 DW_HDMI_PHY_VENDOR_PHY :
2518 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2519
2520 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2521
2522 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2523 dev_err(hdmi->dev,
2524 "Vendor HDMI PHY not supported by glue layer\n");
2525 return -ENODEV;
2526 }
2527
2528 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2529 hdmi->phy.data = hdmi->plat_data->phy_data;
2530 hdmi->phy.name = hdmi->plat_data->phy_name;
2531 return 0;
2532 }
2533
2534
2535 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2536 if (dw_hdmi_phys[i].type == phy_type) {
2537 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2538 hdmi->phy.name = dw_hdmi_phys[i].name;
2539 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2540
2541 if (!dw_hdmi_phys[i].configure &&
2542 !hdmi->plat_data->configure_phy) {
2543 dev_err(hdmi->dev, "%s requires platform support\n",
2544 hdmi->phy.name);
2545 return -ENODEV;
2546 }
2547
2548 return 0;
2549 }
2550 }
2551
2552 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2553 return -ENODEV;
2554 }
2555
2556 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2557 {
2558 mutex_lock(&hdmi->mutex);
2559 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2560 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2561 mutex_unlock(&hdmi->mutex);
2562 }
2563
2564 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2565 {
2566 mutex_lock(&hdmi->mutex);
2567 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2568 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2569 mutex_unlock(&hdmi->mutex);
2570 }
2571
2572 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2573 .write = hdmi_writeb,
2574 .read = hdmi_readb,
2575 .enable = dw_hdmi_cec_enable,
2576 .disable = dw_hdmi_cec_disable,
2577 };
2578
2579 static const struct regmap_config hdmi_regmap_8bit_config = {
2580 .reg_bits = 32,
2581 .val_bits = 8,
2582 .reg_stride = 1,
2583 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2584 };
2585
2586 static const struct regmap_config hdmi_regmap_32bit_config = {
2587 .reg_bits = 32,
2588 .val_bits = 32,
2589 .reg_stride = 4,
2590 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2591 };
2592
2593 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
2594 {
2595 initialize_hdmi_ih_mutes(hdmi);
2596
2597
2598
2599
2600
2601
2602 dw_hdmi_i2c_init(hdmi);
2603
2604 if (hdmi->phy.ops->setup_hpd)
2605 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2606 }
2607
2608 static struct dw_hdmi *
2609 __dw_hdmi_probe(struct platform_device *pdev,
2610 const struct dw_hdmi_plat_data *plat_data)
2611 {
2612 struct device *dev = &pdev->dev;
2613 struct device_node *np = dev->of_node;
2614 struct platform_device_info pdevinfo;
2615 struct device_node *ddc_node;
2616 struct dw_hdmi_cec_data cec;
2617 struct dw_hdmi *hdmi;
2618 struct resource *iores = NULL;
2619 int irq;
2620 int ret;
2621 u32 val = 1;
2622 u8 prod_id0;
2623 u8 prod_id1;
2624 u8 config0;
2625 u8 config3;
2626
2627 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2628 if (!hdmi)
2629 return ERR_PTR(-ENOMEM);
2630
2631 hdmi->plat_data = plat_data;
2632 hdmi->dev = dev;
2633 hdmi->sample_rate = 48000;
2634 hdmi->disabled = true;
2635 hdmi->rxsense = true;
2636 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2637 hdmi->mc_clkdis = 0x7f;
2638
2639 mutex_init(&hdmi->mutex);
2640 mutex_init(&hdmi->audio_mutex);
2641 mutex_init(&hdmi->cec_notifier_mutex);
2642 spin_lock_init(&hdmi->audio_lock);
2643
2644 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2645 if (ddc_node) {
2646 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2647 of_node_put(ddc_node);
2648 if (!hdmi->ddc) {
2649 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2650 return ERR_PTR(-EPROBE_DEFER);
2651 }
2652
2653 } else {
2654 dev_dbg(hdmi->dev, "no ddc property found\n");
2655 }
2656
2657 if (!plat_data->regm) {
2658 const struct regmap_config *reg_config;
2659
2660 of_property_read_u32(np, "reg-io-width", &val);
2661 switch (val) {
2662 case 4:
2663 reg_config = &hdmi_regmap_32bit_config;
2664 hdmi->reg_shift = 2;
2665 break;
2666 case 1:
2667 reg_config = &hdmi_regmap_8bit_config;
2668 break;
2669 default:
2670 dev_err(dev, "reg-io-width must be 1 or 4\n");
2671 return ERR_PTR(-EINVAL);
2672 }
2673
2674 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2675 hdmi->regs = devm_ioremap_resource(dev, iores);
2676 if (IS_ERR(hdmi->regs)) {
2677 ret = PTR_ERR(hdmi->regs);
2678 goto err_res;
2679 }
2680
2681 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2682 if (IS_ERR(hdmi->regm)) {
2683 dev_err(dev, "Failed to configure regmap\n");
2684 ret = PTR_ERR(hdmi->regm);
2685 goto err_res;
2686 }
2687 } else {
2688 hdmi->regm = plat_data->regm;
2689 }
2690
2691 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2692 if (IS_ERR(hdmi->isfr_clk)) {
2693 ret = PTR_ERR(hdmi->isfr_clk);
2694 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2695 goto err_res;
2696 }
2697
2698 ret = clk_prepare_enable(hdmi->isfr_clk);
2699 if (ret) {
2700 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2701 goto err_res;
2702 }
2703
2704 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2705 if (IS_ERR(hdmi->iahb_clk)) {
2706 ret = PTR_ERR(hdmi->iahb_clk);
2707 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2708 goto err_isfr;
2709 }
2710
2711 ret = clk_prepare_enable(hdmi->iahb_clk);
2712 if (ret) {
2713 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2714 goto err_isfr;
2715 }
2716
2717 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2718 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2719 hdmi->cec_clk = NULL;
2720 } else if (IS_ERR(hdmi->cec_clk)) {
2721 ret = PTR_ERR(hdmi->cec_clk);
2722 if (ret != -EPROBE_DEFER)
2723 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2724 ret);
2725
2726 hdmi->cec_clk = NULL;
2727 goto err_iahb;
2728 } else {
2729 ret = clk_prepare_enable(hdmi->cec_clk);
2730 if (ret) {
2731 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2732 ret);
2733 goto err_iahb;
2734 }
2735 }
2736
2737
2738 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2739 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2740 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2741 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2742
2743 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2744 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2745 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2746 hdmi->version, prod_id0, prod_id1);
2747 ret = -ENODEV;
2748 goto err_iahb;
2749 }
2750
2751 ret = dw_hdmi_detect_phy(hdmi);
2752 if (ret < 0)
2753 goto err_iahb;
2754
2755 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2756 hdmi->version >> 12, hdmi->version & 0xfff,
2757 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2758 hdmi->phy.name);
2759
2760 dw_hdmi_init_hw(hdmi);
2761
2762 irq = platform_get_irq(pdev, 0);
2763 if (irq < 0) {
2764 ret = irq;
2765 goto err_iahb;
2766 }
2767
2768 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2769 dw_hdmi_irq, IRQF_SHARED,
2770 dev_name(dev), hdmi);
2771 if (ret)
2772 goto err_iahb;
2773
2774
2775
2776
2777
2778 hdmi_init_clk_regenerator(hdmi);
2779
2780
2781 if (!hdmi->ddc) {
2782
2783 hdmi->pinctrl = devm_pinctrl_get(dev);
2784 if (!IS_ERR(hdmi->pinctrl)) {
2785 hdmi->unwedge_state =
2786 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
2787 hdmi->default_state =
2788 pinctrl_lookup_state(hdmi->pinctrl, "default");
2789
2790 if (IS_ERR(hdmi->default_state) ||
2791 IS_ERR(hdmi->unwedge_state)) {
2792 if (!IS_ERR(hdmi->unwedge_state))
2793 dev_warn(dev,
2794 "Unwedge requires default pinctrl\n");
2795 hdmi->default_state = NULL;
2796 hdmi->unwedge_state = NULL;
2797 }
2798 }
2799
2800 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2801 if (IS_ERR(hdmi->ddc))
2802 hdmi->ddc = NULL;
2803 }
2804
2805 hdmi->bridge.driver_private = hdmi;
2806 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2807 #ifdef CONFIG_OF
2808 hdmi->bridge.of_node = pdev->dev.of_node;
2809 #endif
2810
2811 memset(&pdevinfo, 0, sizeof(pdevinfo));
2812 pdevinfo.parent = dev;
2813 pdevinfo.id = PLATFORM_DEVID_AUTO;
2814
2815 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2816 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2817
2818 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2819 struct dw_hdmi_audio_data audio;
2820
2821 audio.phys = iores->start;
2822 audio.base = hdmi->regs;
2823 audio.irq = irq;
2824 audio.hdmi = hdmi;
2825 audio.eld = hdmi->connector.eld;
2826 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2827 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2828
2829 pdevinfo.name = "dw-hdmi-ahb-audio";
2830 pdevinfo.data = &audio;
2831 pdevinfo.size_data = sizeof(audio);
2832 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2833 hdmi->audio = platform_device_register_full(&pdevinfo);
2834 } else if (config0 & HDMI_CONFIG0_I2S) {
2835 struct dw_hdmi_i2s_audio_data audio;
2836
2837 audio.hdmi = hdmi;
2838 audio.eld = hdmi->connector.eld;
2839 audio.write = hdmi_writeb;
2840 audio.read = hdmi_readb;
2841 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2842 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2843
2844 pdevinfo.name = "dw-hdmi-i2s-audio";
2845 pdevinfo.data = &audio;
2846 pdevinfo.size_data = sizeof(audio);
2847 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2848 hdmi->audio = platform_device_register_full(&pdevinfo);
2849 }
2850
2851 if (config0 & HDMI_CONFIG0_CEC) {
2852 cec.hdmi = hdmi;
2853 cec.ops = &dw_hdmi_cec_ops;
2854 cec.irq = irq;
2855
2856 pdevinfo.name = "dw-hdmi-cec";
2857 pdevinfo.data = &cec;
2858 pdevinfo.size_data = sizeof(cec);
2859 pdevinfo.dma_mask = 0;
2860
2861 hdmi->cec = platform_device_register_full(&pdevinfo);
2862 }
2863
2864 return hdmi;
2865
2866 err_iahb:
2867 if (hdmi->i2c) {
2868 i2c_del_adapter(&hdmi->i2c->adap);
2869 hdmi->ddc = NULL;
2870 }
2871
2872 clk_disable_unprepare(hdmi->iahb_clk);
2873 if (hdmi->cec_clk)
2874 clk_disable_unprepare(hdmi->cec_clk);
2875 err_isfr:
2876 clk_disable_unprepare(hdmi->isfr_clk);
2877 err_res:
2878 i2c_put_adapter(hdmi->ddc);
2879
2880 return ERR_PTR(ret);
2881 }
2882
2883 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2884 {
2885 if (hdmi->audio && !IS_ERR(hdmi->audio))
2886 platform_device_unregister(hdmi->audio);
2887 if (!IS_ERR(hdmi->cec))
2888 platform_device_unregister(hdmi->cec);
2889
2890
2891 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2892
2893 clk_disable_unprepare(hdmi->iahb_clk);
2894 clk_disable_unprepare(hdmi->isfr_clk);
2895 if (hdmi->cec_clk)
2896 clk_disable_unprepare(hdmi->cec_clk);
2897
2898 if (hdmi->i2c)
2899 i2c_del_adapter(&hdmi->i2c->adap);
2900 else
2901 i2c_put_adapter(hdmi->ddc);
2902 }
2903
2904
2905
2906
2907 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2908 const struct dw_hdmi_plat_data *plat_data)
2909 {
2910 struct dw_hdmi *hdmi;
2911
2912 hdmi = __dw_hdmi_probe(pdev, plat_data);
2913 if (IS_ERR(hdmi))
2914 return hdmi;
2915
2916 drm_bridge_add(&hdmi->bridge);
2917
2918 return hdmi;
2919 }
2920 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2921
2922 void dw_hdmi_remove(struct dw_hdmi *hdmi)
2923 {
2924 drm_bridge_remove(&hdmi->bridge);
2925
2926 __dw_hdmi_remove(hdmi);
2927 }
2928 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2929
2930
2931
2932
2933 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2934 struct drm_encoder *encoder,
2935 const struct dw_hdmi_plat_data *plat_data)
2936 {
2937 struct dw_hdmi *hdmi;
2938 int ret;
2939
2940 hdmi = __dw_hdmi_probe(pdev, plat_data);
2941 if (IS_ERR(hdmi))
2942 return hdmi;
2943
2944 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2945 if (ret) {
2946 dw_hdmi_remove(hdmi);
2947 DRM_ERROR("Failed to initialize bridge with drm\n");
2948 return ERR_PTR(ret);
2949 }
2950
2951 return hdmi;
2952 }
2953 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2954
2955 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
2956 {
2957 __dw_hdmi_remove(hdmi);
2958 }
2959 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2960
2961 void dw_hdmi_resume(struct dw_hdmi *hdmi)
2962 {
2963 dw_hdmi_init_hw(hdmi);
2964 }
2965 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2966
2967 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2968 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2969 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2970 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2971 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2972 MODULE_LICENSE("GPL");
2973 MODULE_ALIAS("platform:dw-hdmi");