drivers/gpu/drm/vc4/vc4

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This source file includes following definitions.
dsi_dma_workaround_write
to_vc4_dsi_encoder
vc4_dsi_encoder_destroy
vc4_dsi_latch_ulps
vc4_dsi_ulps
dsi_hs_timing
dsi_esc_timing
vc4_dsi_encoder_disable
vc4_dsi_encoder_mode_fixup
vc4_dsi_encoder_enable
vc4_dsi_host_transfer
vc4_dsi_host_attach
vc4_dsi_host_detach
dsi_handle_error
vc4_dsi_irq_defer_to_thread_handler
vc4_dsi_irq_handler
vc4_dsi_init_phy_clocks
vc4_dsi_bind
vc4_dsi_unbind
vc4_dsi_dev_probe
vc4_dsi_dev_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Broadcom
   4  */
   5 
   6 /**
   7  * DOC: VC4 DSI0/DSI1 module
   8  *
   9  * BCM2835 contains two DSI modules, DSI0 and DSI1.  DSI0 is a
  10  * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
  11  * controller.
  12  *
  13  * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
  14  * while the compute module brings both DSI0 and DSI1 out.
  15  *
  16  * This driver has been tested for DSI1 video-mode display only
  17  * currently, with most of the information necessary for DSI0
  18  * hopefully present.
  19  */
  20 
  21 #include <linux/clk-provider.h>
  22 #include <linux/clk.h>
  23 #include <linux/completion.h>
  24 #include <linux/component.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/dmaengine.h>
  27 #include <linux/i2c.h>
  28 #include <linux/io.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/pm_runtime.h>
  32 
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drm_mipi_dsi.h>
  36 #include <drm/drm_of.h>
  37 #include <drm/drm_panel.h>
  38 #include <drm/drm_probe_helper.h>
  39 
  40 #include "vc4_drv.h"
  41 #include "vc4_regs.h"
  42 
  43 #define DSI_CMD_FIFO_DEPTH  16
  44 #define DSI_PIX_FIFO_DEPTH 256
  45 #define DSI_PIX_FIFO_WIDTH   4
  46 
  47 #define DSI0_CTRL               0x00
  48 
  49 /* Command packet control. */
  50 #define DSI0_TXPKT1C            0x04 /* AKA PKTC */
  51 #define DSI1_TXPKT1C            0x04
  52 # define DSI_TXPKT1C_TRIG_CMD_MASK      VC4_MASK(31, 24)
  53 # define DSI_TXPKT1C_TRIG_CMD_SHIFT     24
  54 # define DSI_TXPKT1C_CMD_REPEAT_MASK    VC4_MASK(23, 10)
  55 # define DSI_TXPKT1C_CMD_REPEAT_SHIFT   10
  56 
  57 # define DSI_TXPKT1C_DISPLAY_NO_MASK    VC4_MASK(9, 8)
  58 # define DSI_TXPKT1C_DISPLAY_NO_SHIFT   8
  59 /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
  60 # define DSI_TXPKT1C_DISPLAY_NO_SHORT           0
  61 /* Primary display where cmdfifo provides part of the payload and
  62  * pixelvalve the rest.
  63  */
  64 # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY         1
  65 /* Secondary display where cmdfifo provides part of the payload and
  66  * pixfifo the rest.
  67  */
  68 # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY       2
  69 
  70 # define DSI_TXPKT1C_CMD_TX_TIME_MASK   VC4_MASK(7, 6)
  71 # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT  6
  72 
  73 # define DSI_TXPKT1C_CMD_CTRL_MASK      VC4_MASK(5, 4)
  74 # define DSI_TXPKT1C_CMD_CTRL_SHIFT     4
  75 /* Command only.  Uses TXPKT1H and DISPLAY_NO */
  76 # define DSI_TXPKT1C_CMD_CTRL_TX        0
  77 /* Command with BTA for either ack or read data. */
  78 # define DSI_TXPKT1C_CMD_CTRL_RX        1
  79 /* Trigger according to TRIG_CMD */
  80 # define DSI_TXPKT1C_CMD_CTRL_TRIG      2
  81 /* BTA alone for getting error status after a command, or a TE trigger
  82  * without a previous command.
  83  */
  84 # define DSI_TXPKT1C_CMD_CTRL_BTA       3
  85 
  86 # define DSI_TXPKT1C_CMD_MODE_LP        BIT(3)
  87 # define DSI_TXPKT1C_CMD_TYPE_LONG      BIT(2)
  88 # define DSI_TXPKT1C_CMD_TE_EN          BIT(1)
  89 # define DSI_TXPKT1C_CMD_EN             BIT(0)
  90 
  91 /* Command packet header. */
  92 #define DSI0_TXPKT1H            0x08 /* AKA PKTH */
  93 #define DSI1_TXPKT1H            0x08
  94 # define DSI_TXPKT1H_BC_CMDFIFO_MASK    VC4_MASK(31, 24)
  95 # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT   24
  96 # define DSI_TXPKT1H_BC_PARAM_MASK      VC4_MASK(23, 8)
  97 # define DSI_TXPKT1H_BC_PARAM_SHIFT     8
  98 # define DSI_TXPKT1H_BC_DT_MASK         VC4_MASK(7, 0)
  99 # define DSI_TXPKT1H_BC_DT_SHIFT        0
 100 
 101 #define DSI0_RXPKT1H            0x0c /* AKA RX1_PKTH */
 102 #define DSI1_RXPKT1H            0x14
 103 # define DSI_RXPKT1H_CRC_ERR            BIT(31)
 104 # define DSI_RXPKT1H_DET_ERR            BIT(30)
 105 # define DSI_RXPKT1H_ECC_ERR            BIT(29)
 106 # define DSI_RXPKT1H_COR_ERR            BIT(28)
 107 # define DSI_RXPKT1H_INCOMP_PKT         BIT(25)
 108 # define DSI_RXPKT1H_PKT_TYPE_LONG      BIT(24)
 109 /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
 110 # define DSI_RXPKT1H_BC_PARAM_MASK      VC4_MASK(23, 8)
 111 # define DSI_RXPKT1H_BC_PARAM_SHIFT     8
 112 /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
 113 # define DSI_RXPKT1H_SHORT_1_MASK       VC4_MASK(23, 16)
 114 # define DSI_RXPKT1H_SHORT_1_SHIFT      16
 115 # define DSI_RXPKT1H_SHORT_0_MASK       VC4_MASK(15, 8)
 116 # define DSI_RXPKT1H_SHORT_0_SHIFT      8
 117 # define DSI_RXPKT1H_DT_LP_CMD_MASK     VC4_MASK(7, 0)
 118 # define DSI_RXPKT1H_DT_LP_CMD_SHIFT    0
 119 
 120 #define DSI0_RXPKT2H            0x10 /* AKA RX2_PKTH */
 121 #define DSI1_RXPKT2H            0x18
 122 # define DSI_RXPKT1H_DET_ERR            BIT(30)
 123 # define DSI_RXPKT1H_ECC_ERR            BIT(29)
 124 # define DSI_RXPKT1H_COR_ERR            BIT(28)
 125 # define DSI_RXPKT1H_INCOMP_PKT         BIT(25)
 126 # define DSI_RXPKT1H_BC_PARAM_MASK      VC4_MASK(23, 8)
 127 # define DSI_RXPKT1H_BC_PARAM_SHIFT     8
 128 # define DSI_RXPKT1H_DT_MASK            VC4_MASK(7, 0)
 129 # define DSI_RXPKT1H_DT_SHIFT           0
 130 
 131 #define DSI0_TXPKT_CMD_FIFO     0x14 /* AKA CMD_DATAF */
 132 #define DSI1_TXPKT_CMD_FIFO     0x1c
 133 
 134 #define DSI0_DISP0_CTRL         0x18
 135 # define DSI_DISP0_PIX_CLK_DIV_MASK     VC4_MASK(21, 13)
 136 # define DSI_DISP0_PIX_CLK_DIV_SHIFT    13
 137 # define DSI_DISP0_LP_STOP_CTRL_MASK    VC4_MASK(12, 11)
 138 # define DSI_DISP0_LP_STOP_CTRL_SHIFT   11
 139 # define DSI_DISP0_LP_STOP_DISABLE      0
 140 # define DSI_DISP0_LP_STOP_PERLINE      1
 141 # define DSI_DISP0_LP_STOP_PERFRAME     2
 142 
 143 /* Transmit RGB pixels and null packets only during HACTIVE, instead
 144  * of going to LP-STOP.
 145  */
 146 # define DSI_DISP_HACTIVE_NULL          BIT(10)
 147 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
 148 # define DSI_DISP_VBLP_CTRL             BIT(9)
 149 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
 150 # define DSI_DISP_HFP_CTRL              BIT(8)
 151 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
 152 # define DSI_DISP_HBP_CTRL              BIT(7)
 153 # define DSI_DISP0_CHANNEL_MASK         VC4_MASK(6, 5)
 154 # define DSI_DISP0_CHANNEL_SHIFT        5
 155 /* Enables end events for HSYNC/VSYNC, not just start events. */
 156 # define DSI_DISP0_ST_END               BIT(4)
 157 # define DSI_DISP0_PFORMAT_MASK         VC4_MASK(3, 2)
 158 # define DSI_DISP0_PFORMAT_SHIFT        2
 159 # define DSI_PFORMAT_RGB565             0
 160 # define DSI_PFORMAT_RGB666_PACKED      1
 161 # define DSI_PFORMAT_RGB666             2
 162 # define DSI_PFORMAT_RGB888             3
 163 /* Default is VIDEO mode. */
 164 # define DSI_DISP0_COMMAND_MODE         BIT(1)
 165 # define DSI_DISP0_ENABLE               BIT(0)
 166 
 167 #define DSI0_DISP1_CTRL         0x1c
 168 #define DSI1_DISP1_CTRL         0x2c
 169 /* Format of the data written to TXPKT_PIX_FIFO. */
 170 # define DSI_DISP1_PFORMAT_MASK         VC4_MASK(2, 1)
 171 # define DSI_DISP1_PFORMAT_SHIFT        1
 172 # define DSI_DISP1_PFORMAT_16BIT        0
 173 # define DSI_DISP1_PFORMAT_24BIT        1
 174 # define DSI_DISP1_PFORMAT_32BIT_LE     2
 175 # define DSI_DISP1_PFORMAT_32BIT_BE     3
 176 
 177 /* DISP1 is always command mode. */
 178 # define DSI_DISP1_ENABLE               BIT(0)
 179 
 180 #define DSI0_TXPKT_PIX_FIFO             0x20 /* AKA PIX_FIFO */
 181 
 182 #define DSI0_INT_STAT           0x24
 183 #define DSI0_INT_EN             0x28
 184 # define DSI1_INT_PHY_D3_ULPS           BIT(30)
 185 # define DSI1_INT_PHY_D3_STOP           BIT(29)
 186 # define DSI1_INT_PHY_D2_ULPS           BIT(28)
 187 # define DSI1_INT_PHY_D2_STOP           BIT(27)
 188 # define DSI1_INT_PHY_D1_ULPS           BIT(26)
 189 # define DSI1_INT_PHY_D1_STOP           BIT(25)
 190 # define DSI1_INT_PHY_D0_ULPS           BIT(24)
 191 # define DSI1_INT_PHY_D0_STOP           BIT(23)
 192 # define DSI1_INT_FIFO_ERR              BIT(22)
 193 # define DSI1_INT_PHY_DIR_RTF           BIT(21)
 194 # define DSI1_INT_PHY_RXLPDT            BIT(20)
 195 # define DSI1_INT_PHY_RXTRIG            BIT(19)
 196 # define DSI1_INT_PHY_D0_LPDT           BIT(18)
 197 # define DSI1_INT_PHY_DIR_FTR           BIT(17)
 198 
 199 /* Signaled when the clock lane enters the given state. */
 200 # define DSI1_INT_PHY_CLOCK_ULPS        BIT(16)
 201 # define DSI1_INT_PHY_CLOCK_HS          BIT(15)
 202 # define DSI1_INT_PHY_CLOCK_STOP        BIT(14)
 203 
 204 /* Signaled on timeouts */
 205 # define DSI1_INT_PR_TO                 BIT(13)
 206 # define DSI1_INT_TA_TO                 BIT(12)
 207 # define DSI1_INT_LPRX_TO               BIT(11)
 208 # define DSI1_INT_HSTX_TO               BIT(10)
 209 
 210 /* Contention on a line when trying to drive the line low */
 211 # define DSI1_INT_ERR_CONT_LP1          BIT(9)
 212 # define DSI1_INT_ERR_CONT_LP0          BIT(8)
 213 
 214 /* Control error: incorrect line state sequence on data lane 0. */
 215 # define DSI1_INT_ERR_CONTROL           BIT(7)
 216 /* LPDT synchronization error (bits received not a multiple of 8. */
 217 
 218 # define DSI1_INT_ERR_SYNC_ESC          BIT(6)
 219 /* Signaled after receiving an error packet from the display in
 220  * response to a read.
 221  */
 222 # define DSI1_INT_RXPKT2                BIT(5)
 223 /* Signaled after receiving a packet.  The header and optional short
 224  * response will be in RXPKT1H, and a long response will be in the
 225  * RXPKT_FIFO.
 226  */
 227 # define DSI1_INT_RXPKT1                BIT(4)
 228 # define DSI1_INT_TXPKT2_DONE           BIT(3)
 229 # define DSI1_INT_TXPKT2_END            BIT(2)
 230 /* Signaled after all repeats of TXPKT1 are transferred. */
 231 # define DSI1_INT_TXPKT1_DONE           BIT(1)
 232 /* Signaled after each TXPKT1 repeat is scheduled. */
 233 # define DSI1_INT_TXPKT1_END            BIT(0)
 234 
 235 #define DSI1_INTERRUPTS_ALWAYS_ENABLED  (DSI1_INT_ERR_SYNC_ESC | \
 236                                          DSI1_INT_ERR_CONTROL |  \
 237                                          DSI1_INT_ERR_CONT_LP0 | \
 238                                          DSI1_INT_ERR_CONT_LP1 | \
 239                                          DSI1_INT_HSTX_TO |      \
 240                                          DSI1_INT_LPRX_TO |      \
 241                                          DSI1_INT_TA_TO |        \
 242                                          DSI1_INT_PR_TO)
 243 
 244 #define DSI0_STAT               0x2c
 245 #define DSI0_HSTX_TO_CNT        0x30
 246 #define DSI0_LPRX_TO_CNT        0x34
 247 #define DSI0_TA_TO_CNT          0x38
 248 #define DSI0_PR_TO_CNT          0x3c
 249 #define DSI0_PHYC               0x40
 250 # define DSI1_PHYC_ESC_CLK_LPDT_MASK    VC4_MASK(25, 20)
 251 # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT   20
 252 # define DSI1_PHYC_HS_CLK_CONTINUOUS    BIT(18)
 253 # define DSI0_PHYC_ESC_CLK_LPDT_MASK    VC4_MASK(17, 12)
 254 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT   12
 255 # define DSI1_PHYC_CLANE_ULPS           BIT(17)
 256 # define DSI1_PHYC_CLANE_ENABLE         BIT(16)
 257 # define DSI_PHYC_DLANE3_ULPS           BIT(13)
 258 # define DSI_PHYC_DLANE3_ENABLE         BIT(12)
 259 # define DSI0_PHYC_HS_CLK_CONTINUOUS    BIT(10)
 260 # define DSI0_PHYC_CLANE_ULPS           BIT(9)
 261 # define DSI_PHYC_DLANE2_ULPS           BIT(9)
 262 # define DSI0_PHYC_CLANE_ENABLE         BIT(8)
 263 # define DSI_PHYC_DLANE2_ENABLE         BIT(8)
 264 # define DSI_PHYC_DLANE1_ULPS           BIT(5)
 265 # define DSI_PHYC_DLANE1_ENABLE         BIT(4)
 266 # define DSI_PHYC_DLANE0_FORCE_STOP     BIT(2)
 267 # define DSI_PHYC_DLANE0_ULPS           BIT(1)
 268 # define DSI_PHYC_DLANE0_ENABLE         BIT(0)
 269 
 270 #define DSI0_HS_CLT0            0x44
 271 #define DSI0_HS_CLT1            0x48
 272 #define DSI0_HS_CLT2            0x4c
 273 #define DSI0_HS_DLT3            0x50
 274 #define DSI0_HS_DLT4            0x54
 275 #define DSI0_HS_DLT5            0x58
 276 #define DSI0_HS_DLT6            0x5c
 277 #define DSI0_HS_DLT7            0x60
 278 
 279 #define DSI0_PHY_AFEC0          0x64
 280 # define DSI0_PHY_AFEC0_DDR2CLK_EN              BIT(26)
 281 # define DSI0_PHY_AFEC0_DDRCLK_EN               BIT(25)
 282 # define DSI0_PHY_AFEC0_LATCH_ULPS              BIT(24)
 283 # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK         VC4_MASK(31, 29)
 284 # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT        29
 285 # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK         VC4_MASK(28, 26)
 286 # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT        26
 287 # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK         VC4_MASK(27, 23)
 288 # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT        23
 289 # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK         VC4_MASK(22, 20)
 290 # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT        20
 291 # define DSI1_PHY_AFEC0_IDR_CLANE_MASK          VC4_MASK(19, 17)
 292 # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT         17
 293 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK       VC4_MASK(23, 20)
 294 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT      20
 295 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK       VC4_MASK(19, 16)
 296 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT      16
 297 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK        VC4_MASK(15, 12)
 298 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT       12
 299 # define DSI1_PHY_AFEC0_DDR2CLK_EN              BIT(16)
 300 # define DSI1_PHY_AFEC0_DDRCLK_EN               BIT(15)
 301 # define DSI1_PHY_AFEC0_LATCH_ULPS              BIT(14)
 302 # define DSI1_PHY_AFEC0_RESET                   BIT(13)
 303 # define DSI1_PHY_AFEC0_PD                      BIT(12)
 304 # define DSI0_PHY_AFEC0_RESET                   BIT(11)
 305 # define DSI1_PHY_AFEC0_PD_BG                   BIT(11)
 306 # define DSI0_PHY_AFEC0_PD                      BIT(10)
 307 # define DSI1_PHY_AFEC0_PD_DLANE3               BIT(10)
 308 # define DSI0_PHY_AFEC0_PD_BG                   BIT(9)
 309 # define DSI1_PHY_AFEC0_PD_DLANE2               BIT(9)
 310 # define DSI0_PHY_AFEC0_PD_DLANE1               BIT(8)
 311 # define DSI1_PHY_AFEC0_PD_DLANE1               BIT(8)
 312 # define DSI_PHY_AFEC0_PTATADJ_MASK             VC4_MASK(7, 4)
 313 # define DSI_PHY_AFEC0_PTATADJ_SHIFT            4
 314 # define DSI_PHY_AFEC0_CTATADJ_MASK             VC4_MASK(3, 0)
 315 # define DSI_PHY_AFEC0_CTATADJ_SHIFT            0
 316 
 317 #define DSI0_PHY_AFEC1          0x68
 318 # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK         VC4_MASK(10, 8)
 319 # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT        8
 320 # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK         VC4_MASK(6, 4)
 321 # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT        4
 322 # define DSI0_PHY_AFEC1_IDR_CLANE_MASK          VC4_MASK(2, 0)
 323 # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT         0
 324 
 325 #define DSI0_TST_SEL            0x6c
 326 #define DSI0_TST_MON            0x70
 327 #define DSI0_ID                 0x74
 328 # define DSI_ID_VALUE           0x00647369
 329 
 330 #define DSI1_CTRL               0x00
 331 # define DSI_CTRL_HS_CLKC_MASK          VC4_MASK(15, 14)
 332 # define DSI_CTRL_HS_CLKC_SHIFT         14
 333 # define DSI_CTRL_HS_CLKC_BYTE          0
 334 # define DSI_CTRL_HS_CLKC_DDR2          1
 335 # define DSI_CTRL_HS_CLKC_DDR           2
 336 
 337 # define DSI_CTRL_RX_LPDT_EOT_DISABLE   BIT(13)
 338 # define DSI_CTRL_LPDT_EOT_DISABLE      BIT(12)
 339 # define DSI_CTRL_HSDT_EOT_DISABLE      BIT(11)
 340 # define DSI_CTRL_SOFT_RESET_CFG        BIT(10)
 341 # define DSI_CTRL_CAL_BYTE              BIT(9)
 342 # define DSI_CTRL_INV_BYTE              BIT(8)
 343 # define DSI_CTRL_CLR_LDF               BIT(7)
 344 # define DSI0_CTRL_CLR_PBCF             BIT(6)
 345 # define DSI1_CTRL_CLR_RXF              BIT(6)
 346 # define DSI0_CTRL_CLR_CPBCF            BIT(5)
 347 # define DSI1_CTRL_CLR_PDF              BIT(5)
 348 # define DSI0_CTRL_CLR_PDF              BIT(4)
 349 # define DSI1_CTRL_CLR_CDF              BIT(4)
 350 # define DSI0_CTRL_CLR_CDF              BIT(3)
 351 # define DSI0_CTRL_CTRL2                BIT(2)
 352 # define DSI1_CTRL_DISABLE_DISP_CRCC    BIT(2)
 353 # define DSI0_CTRL_CTRL1                BIT(1)
 354 # define DSI1_CTRL_DISABLE_DISP_ECCC    BIT(1)
 355 # define DSI0_CTRL_CTRL0                BIT(0)
 356 # define DSI1_CTRL_EN                   BIT(0)
 357 # define DSI0_CTRL_RESET_FIFOS          (DSI_CTRL_CLR_LDF | \
 358                                          DSI0_CTRL_CLR_PBCF | \
 359                                          DSI0_CTRL_CLR_CPBCF |  \
 360                                          DSI0_CTRL_CLR_PDF | \
 361                                          DSI0_CTRL_CLR_CDF)
 362 # define DSI1_CTRL_RESET_FIFOS          (DSI_CTRL_CLR_LDF | \
 363                                          DSI1_CTRL_CLR_RXF | \
 364                                          DSI1_CTRL_CLR_PDF | \
 365                                          DSI1_CTRL_CLR_CDF)
 366 
 367 #define DSI1_TXPKT2C            0x0c
 368 #define DSI1_TXPKT2H            0x10
 369 #define DSI1_TXPKT_PIX_FIFO     0x20
 370 #define DSI1_RXPKT_FIFO         0x24
 371 #define DSI1_DISP0_CTRL         0x28
 372 #define DSI1_INT_STAT           0x30
 373 #define DSI1_INT_EN             0x34
 374 /* State reporting bits.  These mostly behave like INT_STAT, where
 375  * writing a 1 clears the bit.
 376  */
 377 #define DSI1_STAT               0x38
 378 # define DSI1_STAT_PHY_D3_ULPS          BIT(31)
 379 # define DSI1_STAT_PHY_D3_STOP          BIT(30)
 380 # define DSI1_STAT_PHY_D2_ULPS          BIT(29)
 381 # define DSI1_STAT_PHY_D2_STOP          BIT(28)
 382 # define DSI1_STAT_PHY_D1_ULPS          BIT(27)
 383 # define DSI1_STAT_PHY_D1_STOP          BIT(26)
 384 # define DSI1_STAT_PHY_D0_ULPS          BIT(25)
 385 # define DSI1_STAT_PHY_D0_STOP          BIT(24)
 386 # define DSI1_STAT_FIFO_ERR             BIT(23)
 387 # define DSI1_STAT_PHY_RXLPDT           BIT(22)
 388 # define DSI1_STAT_PHY_RXTRIG           BIT(21)
 389 # define DSI1_STAT_PHY_D0_LPDT          BIT(20)
 390 /* Set when in forward direction */
 391 # define DSI1_STAT_PHY_DIR              BIT(19)
 392 # define DSI1_STAT_PHY_CLOCK_ULPS       BIT(18)
 393 # define DSI1_STAT_PHY_CLOCK_HS         BIT(17)
 394 # define DSI1_STAT_PHY_CLOCK_STOP       BIT(16)
 395 # define DSI1_STAT_PR_TO                BIT(15)
 396 # define DSI1_STAT_TA_TO                BIT(14)
 397 # define DSI1_STAT_LPRX_TO              BIT(13)
 398 # define DSI1_STAT_HSTX_TO              BIT(12)
 399 # define DSI1_STAT_ERR_CONT_LP1         BIT(11)
 400 # define DSI1_STAT_ERR_CONT_LP0         BIT(10)
 401 # define DSI1_STAT_ERR_CONTROL          BIT(9)
 402 # define DSI1_STAT_ERR_SYNC_ESC         BIT(8)
 403 # define DSI1_STAT_RXPKT2               BIT(7)
 404 # define DSI1_STAT_RXPKT1               BIT(6)
 405 # define DSI1_STAT_TXPKT2_BUSY          BIT(5)
 406 # define DSI1_STAT_TXPKT2_DONE          BIT(4)
 407 # define DSI1_STAT_TXPKT2_END           BIT(3)
 408 # define DSI1_STAT_TXPKT1_BUSY          BIT(2)
 409 # define DSI1_STAT_TXPKT1_DONE          BIT(1)
 410 # define DSI1_STAT_TXPKT1_END           BIT(0)
 411 
 412 #define DSI1_HSTX_TO_CNT        0x3c
 413 #define DSI1_LPRX_TO_CNT        0x40
 414 #define DSI1_TA_TO_CNT          0x44
 415 #define DSI1_PR_TO_CNT          0x48
 416 #define DSI1_PHYC               0x4c
 417 
 418 #define DSI1_HS_CLT0            0x50
 419 # define DSI_HS_CLT0_CZERO_MASK         VC4_MASK(26, 18)
 420 # define DSI_HS_CLT0_CZERO_SHIFT        18
 421 # define DSI_HS_CLT0_CPRE_MASK          VC4_MASK(17, 9)
 422 # define DSI_HS_CLT0_CPRE_SHIFT         9
 423 # define DSI_HS_CLT0_CPREP_MASK         VC4_MASK(8, 0)
 424 # define DSI_HS_CLT0_CPREP_SHIFT        0
 425 
 426 #define DSI1_HS_CLT1            0x54
 427 # define DSI_HS_CLT1_CTRAIL_MASK        VC4_MASK(17, 9)
 428 # define DSI_HS_CLT1_CTRAIL_SHIFT       9
 429 # define DSI_HS_CLT1_CPOST_MASK         VC4_MASK(8, 0)
 430 # define DSI_HS_CLT1_CPOST_SHIFT        0
 431 
 432 #define DSI1_HS_CLT2            0x58
 433 # define DSI_HS_CLT2_WUP_MASK           VC4_MASK(23, 0)
 434 # define DSI_HS_CLT2_WUP_SHIFT          0
 435 
 436 #define DSI1_HS_DLT3            0x5c
 437 # define DSI_HS_DLT3_EXIT_MASK          VC4_MASK(26, 18)
 438 # define DSI_HS_DLT3_EXIT_SHIFT         18
 439 # define DSI_HS_DLT3_ZERO_MASK          VC4_MASK(17, 9)
 440 # define DSI_HS_DLT3_ZERO_SHIFT         9
 441 # define DSI_HS_DLT3_PRE_MASK           VC4_MASK(8, 0)
 442 # define DSI_HS_DLT3_PRE_SHIFT          0
 443 
 444 #define DSI1_HS_DLT4            0x60
 445 # define DSI_HS_DLT4_ANLAT_MASK         VC4_MASK(22, 18)
 446 # define DSI_HS_DLT4_ANLAT_SHIFT        18
 447 # define DSI_HS_DLT4_TRAIL_MASK         VC4_MASK(17, 9)
 448 # define DSI_HS_DLT4_TRAIL_SHIFT        9
 449 # define DSI_HS_DLT4_LPX_MASK           VC4_MASK(8, 0)
 450 # define DSI_HS_DLT4_LPX_SHIFT          0
 451 
 452 #define DSI1_HS_DLT5            0x64
 453 # define DSI_HS_DLT5_INIT_MASK          VC4_MASK(23, 0)
 454 # define DSI_HS_DLT5_INIT_SHIFT         0
 455 
 456 #define DSI1_HS_DLT6            0x68
 457 # define DSI_HS_DLT6_TA_GET_MASK        VC4_MASK(31, 24)
 458 # define DSI_HS_DLT6_TA_GET_SHIFT       24
 459 # define DSI_HS_DLT6_TA_SURE_MASK       VC4_MASK(23, 16)
 460 # define DSI_HS_DLT6_TA_SURE_SHIFT      16
 461 # define DSI_HS_DLT6_TA_GO_MASK         VC4_MASK(15, 8)
 462 # define DSI_HS_DLT6_TA_GO_SHIFT        8
 463 # define DSI_HS_DLT6_LP_LPX_MASK        VC4_MASK(7, 0)
 464 # define DSI_HS_DLT6_LP_LPX_SHIFT       0
 465 
 466 #define DSI1_HS_DLT7            0x6c
 467 # define DSI_HS_DLT7_LP_WUP_MASK        VC4_MASK(23, 0)
 468 # define DSI_HS_DLT7_LP_WUP_SHIFT       0
 469 
 470 #define DSI1_PHY_AFEC0          0x70
 471 
 472 #define DSI1_PHY_AFEC1          0x74
 473 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK       VC4_MASK(19, 16)
 474 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT      16
 475 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK       VC4_MASK(15, 12)
 476 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT      12
 477 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK       VC4_MASK(11, 8)
 478 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT      8
 479 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK       VC4_MASK(7, 4)
 480 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT      4
 481 # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK        VC4_MASK(3, 0)
 482 # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT       0
 483 
 484 #define DSI1_TST_SEL            0x78
 485 #define DSI1_TST_MON            0x7c
 486 #define DSI1_PHY_TST1           0x80
 487 #define DSI1_PHY_TST2           0x84
 488 #define DSI1_PHY_FIFO_STAT      0x88
 489 /* Actually, all registers in the range that aren't otherwise claimed
 490  * will return the ID.
 491  */
 492 #define DSI1_ID                 0x8c
 493 
 494 /* General DSI hardware state. */
 495 struct vc4_dsi {
 496         struct platform_device *pdev;
 497 
 498         struct mipi_dsi_host dsi_host;
 499         struct drm_encoder *encoder;
 500         struct drm_bridge *bridge;
 501 
 502         void __iomem *regs;
 503 
 504         struct dma_chan *reg_dma_chan;
 505         dma_addr_t reg_dma_paddr;
 506         u32 *reg_dma_mem;
 507         dma_addr_t reg_paddr;
 508 
 509         /* Whether we're on bcm2835's DSI0 or DSI1. */
 510         int port;
 511 
 512         /* DSI channel for the panel we're connected to. */
 513         u32 channel;
 514         u32 lanes;
 515         u32 format;
 516         u32 divider;
 517         u32 mode_flags;
 518 
 519         /* Input clock from CPRMAN to the digital PHY, for the DSI
 520          * escape clock.
 521          */
 522         struct clk *escape_clock;
 523 
 524         /* Input clock to the analog PHY, used to generate the DSI bit
 525          * clock.
 526          */
 527         struct clk *pll_phy_clock;
 528 
 529         /* HS Clocks generated within the DSI analog PHY. */
 530         struct clk_fixed_factor phy_clocks[3];
 531 
 532         struct clk_hw_onecell_data *clk_onecell;
 533 
 534         /* Pixel clock output to the pixelvalve, generated from the HS
 535          * clock.
 536          */
 537         struct clk *pixel_clock;
 538 
 539         struct completion xfer_completion;
 540         int xfer_result;
 541 
 542         struct debugfs_regset32 regset;
 543 };
 544 
 545 #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
 546 
 547 static inline void
 548 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
 549 {
 550         struct dma_chan *chan = dsi->reg_dma_chan;
 551         struct dma_async_tx_descriptor *tx;
 552         dma_cookie_t cookie;
 553         int ret;
 554 
 555         /* DSI0 should be able to write normally. */
 556         if (!chan) {
 557                 writel(val, dsi->regs + offset);
 558                 return;
 559         }
 560 
 561         *dsi->reg_dma_mem = val;
 562 
 563         tx = chan->device->device_prep_dma_memcpy(chan,
 564                                                   dsi->reg_paddr + offset,
 565                                                   dsi->reg_dma_paddr,
 566                                                   4, 0);
 567         if (!tx) {
 568                 DRM_ERROR("Failed to set up DMA register write\n");
 569                 return;
 570         }
 571 
 572         cookie = tx->tx_submit(tx);
 573         ret = dma_submit_error(cookie);
 574         if (ret) {
 575                 DRM_ERROR("Failed to submit DMA: %d\n", ret);
 576                 return;
 577         }
 578         ret = dma_sync_wait(chan, cookie);
 579         if (ret)
 580                 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
 581 }
 582 
 583 #define DSI_READ(offset) readl(dsi->regs + (offset))
 584 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
 585 #define DSI_PORT_READ(offset) \
 586         DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
 587 #define DSI_PORT_WRITE(offset, val) \
 588         DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
 589 #define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
 590 
 591 /* VC4 DSI encoder KMS struct */
 592 struct vc4_dsi_encoder {
 593         struct vc4_encoder base;
 594         struct vc4_dsi *dsi;
 595 };
 596 
 597 static inline struct vc4_dsi_encoder *
 598 to_vc4_dsi_encoder(struct drm_encoder *encoder)
 599 {
 600         return container_of(encoder, struct vc4_dsi_encoder, base.base);
 601 }
 602 
 603 static const struct debugfs_reg32 dsi0_regs[] = {
 604         VC4_REG32(DSI0_CTRL),
 605         VC4_REG32(DSI0_STAT),
 606         VC4_REG32(DSI0_HSTX_TO_CNT),
 607         VC4_REG32(DSI0_LPRX_TO_CNT),
 608         VC4_REG32(DSI0_TA_TO_CNT),
 609         VC4_REG32(DSI0_PR_TO_CNT),
 610         VC4_REG32(DSI0_DISP0_CTRL),
 611         VC4_REG32(DSI0_DISP1_CTRL),
 612         VC4_REG32(DSI0_INT_STAT),
 613         VC4_REG32(DSI0_INT_EN),
 614         VC4_REG32(DSI0_PHYC),
 615         VC4_REG32(DSI0_HS_CLT0),
 616         VC4_REG32(DSI0_HS_CLT1),
 617         VC4_REG32(DSI0_HS_CLT2),
 618         VC4_REG32(DSI0_HS_DLT3),
 619         VC4_REG32(DSI0_HS_DLT4),
 620         VC4_REG32(DSI0_HS_DLT5),
 621         VC4_REG32(DSI0_HS_DLT6),
 622         VC4_REG32(DSI0_HS_DLT7),
 623         VC4_REG32(DSI0_PHY_AFEC0),
 624         VC4_REG32(DSI0_PHY_AFEC1),
 625         VC4_REG32(DSI0_ID),
 626 };
 627 
 628 static const struct debugfs_reg32 dsi1_regs[] = {
 629         VC4_REG32(DSI1_CTRL),
 630         VC4_REG32(DSI1_STAT),
 631         VC4_REG32(DSI1_HSTX_TO_CNT),
 632         VC4_REG32(DSI1_LPRX_TO_CNT),
 633         VC4_REG32(DSI1_TA_TO_CNT),
 634         VC4_REG32(DSI1_PR_TO_CNT),
 635         VC4_REG32(DSI1_DISP0_CTRL),
 636         VC4_REG32(DSI1_DISP1_CTRL),
 637         VC4_REG32(DSI1_INT_STAT),
 638         VC4_REG32(DSI1_INT_EN),
 639         VC4_REG32(DSI1_PHYC),
 640         VC4_REG32(DSI1_HS_CLT0),
 641         VC4_REG32(DSI1_HS_CLT1),
 642         VC4_REG32(DSI1_HS_CLT2),
 643         VC4_REG32(DSI1_HS_DLT3),
 644         VC4_REG32(DSI1_HS_DLT4),
 645         VC4_REG32(DSI1_HS_DLT5),
 646         VC4_REG32(DSI1_HS_DLT6),
 647         VC4_REG32(DSI1_HS_DLT7),
 648         VC4_REG32(DSI1_PHY_AFEC0),
 649         VC4_REG32(DSI1_PHY_AFEC1),
 650         VC4_REG32(DSI1_ID),
 651 };
 652 
 653 static void vc4_dsi_encoder_destroy(struct drm_encoder *encoder)
 654 {
 655         drm_encoder_cleanup(encoder);
 656 }
 657 
 658 static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
 659         .destroy = vc4_dsi_encoder_destroy,
 660 };
 661 
 662 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
 663 {
 664         u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
 665 
 666         if (latch)
 667                 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
 668         else
 669                 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
 670 
 671         DSI_PORT_WRITE(PHY_AFEC0, afec0);
 672 }
 673 
 674 /* Enters or exits Ultra Low Power State. */
 675 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
 676 {
 677         bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
 678         u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
 679                          DSI_PHYC_DLANE0_ULPS |
 680                          (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
 681                          (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
 682                          (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
 683         u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
 684                          DSI1_STAT_PHY_D0_ULPS |
 685                          (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
 686                          (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
 687                          (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
 688         u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
 689                          DSI1_STAT_PHY_D0_STOP |
 690                          (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
 691                          (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
 692                          (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
 693         int ret;
 694         bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
 695                                        DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
 696 
 697         if (ulps == ulps_currently_enabled)
 698                 return;
 699 
 700         DSI_PORT_WRITE(STAT, stat_ulps);
 701         DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
 702         ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
 703         if (ret) {
 704                 dev_warn(&dsi->pdev->dev,
 705                          "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
 706                          DSI_PORT_READ(STAT));
 707                 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
 708                 vc4_dsi_latch_ulps(dsi, false);
 709                 return;
 710         }
 711 
 712         /* The DSI module can't be disabled while the module is
 713          * generating ULPS state.  So, to be able to disable the
 714          * module, we have the AFE latch the ULPS state and continue
 715          * on to having the module enter STOP.
 716          */
 717         vc4_dsi_latch_ulps(dsi, ulps);
 718 
 719         DSI_PORT_WRITE(STAT, stat_stop);
 720         DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
 721         ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
 722         if (ret) {
 723                 dev_warn(&dsi->pdev->dev,
 724                          "Timeout waiting for DSI STOP entry: STAT 0x%08x",
 725                          DSI_PORT_READ(STAT));
 726                 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
 727                 return;
 728         }
 729 }
 730 
 731 static u32
 732 dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
 733 {
 734         /* The HS timings have to be rounded up to a multiple of 8
 735          * because we're using the byte clock.
 736          */
 737         return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
 738 }
 739 
 740 /* ESC always runs at 100Mhz. */
 741 #define ESC_TIME_NS 10
 742 
 743 static u32
 744 dsi_esc_timing(u32 ns)
 745 {
 746         return DIV_ROUND_UP(ns, ESC_TIME_NS);
 747 }
 748 
 749 static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
 750 {
 751         struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
 752         struct vc4_dsi *dsi = vc4_encoder->dsi;
 753         struct device *dev = &dsi->pdev->dev;
 754 
 755         drm_bridge_disable(dsi->bridge);
 756         vc4_dsi_ulps(dsi, true);
 757         drm_bridge_post_disable(dsi->bridge);
 758 
 759         clk_disable_unprepare(dsi->pll_phy_clock);
 760         clk_disable_unprepare(dsi->escape_clock);
 761         clk_disable_unprepare(dsi->pixel_clock);
 762 
 763         pm_runtime_put(dev);
 764 }
 765 
 766 /* Extends the mode's blank intervals to handle BCM2835's integer-only
 767  * DSI PLL divider.
 768  *
 769  * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
 770  * driver since most peripherals are hanging off of the PLLD_PER
 771  * divider.  PLLD_DSI1, which drives our DSI bit clock (and therefore
 772  * the pixel clock), only has an integer divider off of DSI.
 773  *
 774  * To get our panel mode to refresh at the expected 60Hz, we need to
 775  * extend the horizontal blank time.  This means we drive a
 776  * higher-than-expected clock rate to the panel, but that's what the
 777  * firmware does too.
 778  */
 779 static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 780                                        const struct drm_display_mode *mode,
 781                                        struct drm_display_mode *adjusted_mode)
 782 {
 783         struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
 784         struct vc4_dsi *dsi = vc4_encoder->dsi;
 785         struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
 786         unsigned long parent_rate = clk_get_rate(phy_parent);
 787         unsigned long pixel_clock_hz = mode->clock * 1000;
 788         unsigned long pll_clock = pixel_clock_hz * dsi->divider;
 789         int divider;
 790 
 791         /* Find what divider gets us a faster clock than the requested
 792          * pixel clock.
 793          */
 794         for (divider = 1; divider < 8; divider++) {
 795                 if (parent_rate / divider < pll_clock) {
 796                         divider--;
 797                         break;
 798                 }
 799         }
 800 
 801         /* Now that we've picked a PLL divider, calculate back to its
 802          * pixel clock.
 803          */
 804         pll_clock = parent_rate / divider;
 805         pixel_clock_hz = pll_clock / dsi->divider;
 806 
 807         adjusted_mode->clock = pixel_clock_hz / 1000;
 808 
 809         /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
 810         adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
 811                                 mode->clock;
 812         adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
 813         adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
 814 
 815         return true;
 816 }
 817 
 818 static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
 819 {
 820         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 821         struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
 822         struct vc4_dsi *dsi = vc4_encoder->dsi;
 823         struct device *dev = &dsi->pdev->dev;
 824         bool debug_dump_regs = false;
 825         unsigned long hs_clock;
 826         u32 ui_ns;
 827         /* Minimum LP state duration in escape clock cycles. */
 828         u32 lpx = dsi_esc_timing(60);
 829         unsigned long pixel_clock_hz = mode->clock * 1000;
 830         unsigned long dsip_clock;
 831         unsigned long phy_clock;
 832         int ret;
 833 
 834         ret = pm_runtime_get_sync(dev);
 835         if (ret) {
 836                 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port);
 837                 return;
 838         }
 839 
 840         if (debug_dump_regs) {
 841                 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
 842                 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
 843                 drm_print_regset32(&p, &dsi->regset);
 844         }
 845 
 846         /* Round up the clk_set_rate() request slightly, since
 847          * PLLD_DSI1 is an integer divider and its rate selection will
 848          * never round up.
 849          */
 850         phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
 851         ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
 852         if (ret) {
 853                 dev_err(&dsi->pdev->dev,
 854                         "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
 855         }
 856 
 857         /* Reset the DSI and all its fifos. */
 858         DSI_PORT_WRITE(CTRL,
 859                        DSI_CTRL_SOFT_RESET_CFG |
 860                        DSI_PORT_BIT(CTRL_RESET_FIFOS));
 861 
 862         DSI_PORT_WRITE(CTRL,
 863                        DSI_CTRL_HSDT_EOT_DISABLE |
 864                        DSI_CTRL_RX_LPDT_EOT_DISABLE);
 865 
 866         /* Clear all stat bits so we see what has happened during enable. */
 867         DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
 868 
 869         /* Set AFE CTR00/CTR1 to release powerdown of analog. */
 870         if (dsi->port == 0) {
 871                 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
 872                              VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
 873 
 874                 if (dsi->lanes < 2)
 875                         afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
 876 
 877                 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
 878                         afec0 |= DSI0_PHY_AFEC0_RESET;
 879 
 880                 DSI_PORT_WRITE(PHY_AFEC0, afec0);
 881 
 882                 DSI_PORT_WRITE(PHY_AFEC1,
 883                                VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_DLANE1) |
 884                                VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_DLANE0) |
 885                                VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_CLANE));
 886         } else {
 887                 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
 888                              VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
 889                              VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
 890                              VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
 891                              VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
 892                              VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
 893                              VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
 894 
 895                 if (dsi->lanes < 4)
 896                         afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
 897                 if (dsi->lanes < 3)
 898                         afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
 899                 if (dsi->lanes < 2)
 900                         afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
 901 
 902                 afec0 |= DSI1_PHY_AFEC0_RESET;
 903 
 904                 DSI_PORT_WRITE(PHY_AFEC0, afec0);
 905 
 906                 DSI_PORT_WRITE(PHY_AFEC1, 0);
 907 
 908                 /* AFEC reset hold time */
 909                 mdelay(1);
 910         }
 911 
 912         ret = clk_prepare_enable(dsi->escape_clock);
 913         if (ret) {
 914                 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
 915                 return;
 916         }
 917 
 918         ret = clk_prepare_enable(dsi->pll_phy_clock);
 919         if (ret) {
 920                 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
 921                 return;
 922         }
 923 
 924         hs_clock = clk_get_rate(dsi->pll_phy_clock);
 925 
 926         /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
 927          * not the pixel clock rate.  DSIxP take from the APHY's byte,
 928          * DDR2, or DDR4 clock (we use byte) and feed into the PV at
 929          * that rate.  Separately, a value derived from PIX_CLK_DIV
 930          * and HS_CLKC is fed into the PV to divide down to the actual
 931          * pixel clock for pushing pixels into DSI.
 932          */
 933         dsip_clock = phy_clock / 8;
 934         ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
 935         if (ret) {
 936                 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
 937                         dsip_clock, ret);
 938         }
 939 
 940         ret = clk_prepare_enable(dsi->pixel_clock);
 941         if (ret) {
 942                 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
 943                 return;
 944         }
 945 
 946         /* How many ns one DSI unit interval is.  Note that the clock
 947          * is DDR, so there's an extra divide by 2.
 948          */
 949         ui_ns = DIV_ROUND_UP(500000000, hs_clock);
 950 
 951         DSI_PORT_WRITE(HS_CLT0,
 952                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
 953                                      DSI_HS_CLT0_CZERO) |
 954                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
 955                                      DSI_HS_CLT0_CPRE) |
 956                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
 957                                      DSI_HS_CLT0_CPREP));
 958 
 959         DSI_PORT_WRITE(HS_CLT1,
 960                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
 961                                      DSI_HS_CLT1_CTRAIL) |
 962                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
 963                                      DSI_HS_CLT1_CPOST));
 964 
 965         DSI_PORT_WRITE(HS_CLT2,
 966                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
 967                                      DSI_HS_CLT2_WUP));
 968 
 969         DSI_PORT_WRITE(HS_DLT3,
 970                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
 971                                      DSI_HS_DLT3_EXIT) |
 972                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
 973                                      DSI_HS_DLT3_ZERO) |
 974                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
 975                                      DSI_HS_DLT3_PRE));
 976 
 977         DSI_PORT_WRITE(HS_DLT4,
 978                        VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
 979                                      DSI_HS_DLT4_LPX) |
 980                        VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
 981                                          dsi_hs_timing(ui_ns, 60, 4)),
 982                                      DSI_HS_DLT4_TRAIL) |
 983                        VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
 984 
 985         /* T_INIT is how long STOP is driven after power-up to
 986          * indicate to the slave (also coming out of power-up) that
 987          * master init is complete, and should be greater than the
 988          * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE.  The
 989          * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
 990          * T_INIT,SLAVE, while allowing protocols on top of it to give
 991          * greater minimums.  The vc4 firmware uses an extremely
 992          * conservative 5ms, and we maintain that here.
 993          */
 994         DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
 995                                                             5 * 1000 * 1000, 0),
 996                                               DSI_HS_DLT5_INIT));
 997 
 998         DSI_PORT_WRITE(HS_DLT6,
 999                        VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1000                        VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1001                        VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1002                        VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1003 
1004         DSI_PORT_WRITE(HS_DLT7,
1005                        VC4_SET_FIELD(dsi_esc_timing(1000000),
1006                                      DSI_HS_DLT7_LP_WUP));
1007 
1008         DSI_PORT_WRITE(PHYC,
1009                        DSI_PHYC_DLANE0_ENABLE |
1010                        (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1011                        (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1012                        (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1013                        DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1014                        ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1015                         0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1016                        (dsi->port == 0 ?
1017                         VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1018                         VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1019 
1020         DSI_PORT_WRITE(CTRL,
1021                        DSI_PORT_READ(CTRL) |
1022                        DSI_CTRL_CAL_BYTE);
1023 
1024         /* HS timeout in HS clock cycles: disabled. */
1025         DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1026         /* LP receive timeout in HS clocks. */
1027         DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1028         /* Bus turnaround timeout */
1029         DSI_PORT_WRITE(TA_TO_CNT, 100000);
1030         /* Display reset sequence timeout */
1031         DSI_PORT_WRITE(PR_TO_CNT, 100000);
1032 
1033         /* Set up DISP1 for transferring long command payloads through
1034          * the pixfifo.
1035          */
1036         DSI_PORT_WRITE(DISP1_CTRL,
1037                        VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1038                                      DSI_DISP1_PFORMAT) |
1039                        DSI_DISP1_ENABLE);
1040 
1041         /* Ungate the block. */
1042         if (dsi->port == 0)
1043                 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1044         else
1045                 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1046 
1047         /* Bring AFE out of reset. */
1048         if (dsi->port == 0) {
1049         } else {
1050                 DSI_PORT_WRITE(PHY_AFEC0,
1051                                DSI_PORT_READ(PHY_AFEC0) &
1052                                ~DSI1_PHY_AFEC0_RESET);
1053         }
1054 
1055         vc4_dsi_ulps(dsi, false);
1056 
1057         drm_bridge_pre_enable(dsi->bridge);
1058 
1059         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1060                 DSI_PORT_WRITE(DISP0_CTRL,
1061                                VC4_SET_FIELD(dsi->divider,
1062                                              DSI_DISP0_PIX_CLK_DIV) |
1063                                VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1064                                VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1065                                              DSI_DISP0_LP_STOP_CTRL) |
1066                                DSI_DISP0_ST_END |
1067                                DSI_DISP0_ENABLE);
1068         } else {
1069                 DSI_PORT_WRITE(DISP0_CTRL,
1070                                DSI_DISP0_COMMAND_MODE |
1071                                DSI_DISP0_ENABLE);
1072         }
1073 
1074         drm_bridge_enable(dsi->bridge);
1075 
1076         if (debug_dump_regs) {
1077                 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1078                 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1079                 drm_print_regset32(&p, &dsi->regset);
1080         }
1081 }
1082 
1083 static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1084                                      const struct mipi_dsi_msg *msg)
1085 {
1086         struct vc4_dsi *dsi = host_to_dsi(host);
1087         struct mipi_dsi_packet packet;
1088         u32 pkth = 0, pktc = 0;
1089         int i, ret;
1090         bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1091         u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1092 
1093         mipi_dsi_create_packet(&packet, msg);
1094 
1095         pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1096         pkth |= VC4_SET_FIELD(packet.header[1] |
1097                               (packet.header[2] << 8),
1098                               DSI_TXPKT1H_BC_PARAM);
1099         if (is_long) {
1100                 /* Divide data across the various FIFOs we have available.
1101                  * The command FIFO takes byte-oriented data, but is of
1102                  * limited size. The pixel FIFO (never actually used for
1103                  * pixel data in reality) is word oriented, and substantially
1104                  * larger. So, we use the pixel FIFO for most of the data,
1105                  * sending the residual bytes in the command FIFO at the start.
1106                  *
1107                  * With this arrangement, the command FIFO will never get full.
1108                  */
1109                 if (packet.payload_length <= 16) {
1110                         cmd_fifo_len = packet.payload_length;
1111                         pix_fifo_len = 0;
1112                 } else {
1113                         cmd_fifo_len = (packet.payload_length %
1114                                         DSI_PIX_FIFO_WIDTH);
1115                         pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1116                                         DSI_PIX_FIFO_WIDTH);
1117                 }
1118 
1119                 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1120 
1121                 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1122         }
1123 
1124         if (msg->rx_len) {
1125                 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1126                                       DSI_TXPKT1C_CMD_CTRL);
1127         } else {
1128                 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1129                                       DSI_TXPKT1C_CMD_CTRL);
1130         }
1131 
1132         for (i = 0; i < cmd_fifo_len; i++)
1133                 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1134         for (i = 0; i < pix_fifo_len; i++) {
1135                 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1136 
1137                 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1138                                pix[0] |
1139                                pix[1] << 8 |
1140                                pix[2] << 16 |
1141                                pix[3] << 24);
1142         }
1143 
1144         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1145                 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1146         if (is_long)
1147                 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1148 
1149         /* Send one copy of the packet.  Larger repeats are used for pixel
1150          * data in command mode.
1151          */
1152         pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1153 
1154         pktc |= DSI_TXPKT1C_CMD_EN;
1155         if (pix_fifo_len) {
1156                 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1157                                       DSI_TXPKT1C_DISPLAY_NO);
1158         } else {
1159                 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1160                                       DSI_TXPKT1C_DISPLAY_NO);
1161         }
1162 
1163         /* Enable the appropriate interrupt for the transfer completion. */
1164         dsi->xfer_result = 0;
1165         reinit_completion(&dsi->xfer_completion);
1166         DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1167         if (msg->rx_len) {
1168                 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1169                                         DSI1_INT_PHY_DIR_RTF));
1170         } else {
1171                 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1172                                         DSI1_INT_TXPKT1_DONE));
1173         }
1174 
1175         /* Send the packet. */
1176         DSI_PORT_WRITE(TXPKT1H, pkth);
1177         DSI_PORT_WRITE(TXPKT1C, pktc);
1178 
1179         if (!wait_for_completion_timeout(&dsi->xfer_completion,
1180                                          msecs_to_jiffies(1000))) {
1181                 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1182                 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1183                         DSI_PORT_READ(INT_STAT));
1184                 ret = -ETIMEDOUT;
1185         } else {
1186                 ret = dsi->xfer_result;
1187         }
1188 
1189         DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1190 
1191         if (ret)
1192                 goto reset_fifo_and_return;
1193 
1194         if (ret == 0 && msg->rx_len) {
1195                 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1196                 u8 *msg_rx = msg->rx_buf;
1197 
1198                 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1199                         u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1200                                                   DSI_RXPKT1H_BC_PARAM);
1201 
1202                         if (rxlen != msg->rx_len) {
1203                                 DRM_ERROR("DSI returned %db, expecting %db\n",
1204                                           rxlen, (int)msg->rx_len);
1205                                 ret = -ENXIO;
1206                                 goto reset_fifo_and_return;
1207                         }
1208 
1209                         for (i = 0; i < msg->rx_len; i++)
1210                                 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1211                 } else {
1212                         /* FINISHME: Handle AWER */
1213 
1214                         msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1215                                                   DSI_RXPKT1H_SHORT_0);
1216                         if (msg->rx_len > 1) {
1217                                 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1218                                                           DSI_RXPKT1H_SHORT_1);
1219                         }
1220                 }
1221         }
1222 
1223         return ret;
1224 
1225 reset_fifo_and_return:
1226         DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1227 
1228         DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1229         udelay(1);
1230         DSI_PORT_WRITE(CTRL,
1231                        DSI_PORT_READ(CTRL) |
1232                        DSI_PORT_BIT(CTRL_RESET_FIFOS));
1233 
1234         DSI_PORT_WRITE(TXPKT1C, 0);
1235         DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1236         return ret;
1237 }
1238 
1239 static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1240                                struct mipi_dsi_device *device)
1241 {
1242         struct vc4_dsi *dsi = host_to_dsi(host);
1243 
1244         dsi->lanes = device->lanes;
1245         dsi->channel = device->channel;
1246         dsi->mode_flags = device->mode_flags;
1247 
1248         switch (device->format) {
1249         case MIPI_DSI_FMT_RGB888:
1250                 dsi->format = DSI_PFORMAT_RGB888;
1251                 dsi->divider = 24 / dsi->lanes;
1252                 break;
1253         case MIPI_DSI_FMT_RGB666:
1254                 dsi->format = DSI_PFORMAT_RGB666;
1255                 dsi->divider = 24 / dsi->lanes;
1256                 break;
1257         case MIPI_DSI_FMT_RGB666_PACKED:
1258                 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1259                 dsi->divider = 18 / dsi->lanes;
1260                 break;
1261         case MIPI_DSI_FMT_RGB565:
1262                 dsi->format = DSI_PFORMAT_RGB565;
1263                 dsi->divider = 16 / dsi->lanes;
1264                 break;
1265         default:
1266                 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1267                         dsi->format);
1268                 return 0;
1269         }
1270 
1271         if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1272                 dev_err(&dsi->pdev->dev,
1273                         "Only VIDEO mode panels supported currently.\n");
1274                 return 0;
1275         }
1276 
1277         return 0;
1278 }
1279 
1280 static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1281                                struct mipi_dsi_device *device)
1282 {
1283         return 0;
1284 }
1285 
1286 static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1287         .attach = vc4_dsi_host_attach,
1288         .detach = vc4_dsi_host_detach,
1289         .transfer = vc4_dsi_host_transfer,
1290 };
1291 
1292 static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1293         .disable = vc4_dsi_encoder_disable,
1294         .enable = vc4_dsi_encoder_enable,
1295         .mode_fixup = vc4_dsi_encoder_mode_fixup,
1296 };
1297 
1298 static const struct of_device_id vc4_dsi_dt_match[] = {
1299         { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 },
1300         {}
1301 };
1302 
1303 static void dsi_handle_error(struct vc4_dsi *dsi,
1304                              irqreturn_t *ret, u32 stat, u32 bit,
1305                              const char *type)
1306 {
1307         if (!(stat & bit))
1308                 return;
1309 
1310         DRM_ERROR("DSI%d: %s error\n", dsi->port, type);
1311         *ret = IRQ_HANDLED;
1312 }
1313 
1314 /*
1315  * Initial handler for port 1 where we need the reg_dma workaround.
1316  * The register DMA writes sleep, so we can't do it in the top half.
1317  * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1318  * parent interrupt contrller until our interrupt thread is done.
1319  */
1320 static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1321 {
1322         struct vc4_dsi *dsi = data;
1323         u32 stat = DSI_PORT_READ(INT_STAT);
1324 
1325         if (!stat)
1326                 return IRQ_NONE;
1327 
1328         return IRQ_WAKE_THREAD;
1329 }
1330 
1331 /*
1332  * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1333  * 1 where we need the reg_dma workaround.
1334  */
1335 static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1336 {
1337         struct vc4_dsi *dsi = data;
1338         u32 stat = DSI_PORT_READ(INT_STAT);
1339         irqreturn_t ret = IRQ_NONE;
1340 
1341         DSI_PORT_WRITE(INT_STAT, stat);
1342 
1343         dsi_handle_error(dsi, &ret, stat,
1344                          DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
1345         dsi_handle_error(dsi, &ret, stat,
1346                          DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
1347         dsi_handle_error(dsi, &ret, stat,
1348                          DSI1_INT_ERR_CONT_LP0, "LP0 contention");
1349         dsi_handle_error(dsi, &ret, stat,
1350                          DSI1_INT_ERR_CONT_LP1, "LP1 contention");
1351         dsi_handle_error(dsi, &ret, stat,
1352                          DSI1_INT_HSTX_TO, "HSTX timeout");
1353         dsi_handle_error(dsi, &ret, stat,
1354                          DSI1_INT_LPRX_TO, "LPRX timeout");
1355         dsi_handle_error(dsi, &ret, stat,
1356                          DSI1_INT_TA_TO, "turnaround timeout");
1357         dsi_handle_error(dsi, &ret, stat,
1358                          DSI1_INT_PR_TO, "peripheral reset timeout");
1359 
1360         if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
1361                 complete(&dsi->xfer_completion);
1362                 ret = IRQ_HANDLED;
1363         } else if (stat & DSI1_INT_HSTX_TO) {
1364                 complete(&dsi->xfer_completion);
1365                 dsi->xfer_result = -ETIMEDOUT;
1366                 ret = IRQ_HANDLED;
1367         }
1368 
1369         return ret;
1370 }
1371 
1372 /**
1373  * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1374  * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1375  * @dsi: DSI encoder
1376  */
1377 static int
1378 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1379 {
1380         struct device *dev = &dsi->pdev->dev;
1381         const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1382         static const struct {
1383                 const char *dsi0_name, *dsi1_name;
1384                 int div;
1385         } phy_clocks[] = {
1386                 { "dsi0_byte", "dsi1_byte", 8 },
1387                 { "dsi0_ddr2", "dsi1_ddr2", 4 },
1388                 { "dsi0_ddr", "dsi1_ddr", 2 },
1389         };
1390         int i;
1391 
1392         dsi->clk_onecell = devm_kzalloc(dev,
1393                                         sizeof(*dsi->clk_onecell) +
1394                                         ARRAY_SIZE(phy_clocks) *
1395                                         sizeof(struct clk_hw *),
1396                                         GFP_KERNEL);
1397         if (!dsi->clk_onecell)
1398                 return -ENOMEM;
1399         dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1400 
1401         for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1402                 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1403                 struct clk_init_data init;
1404                 int ret;
1405 
1406                 /* We just use core fixed factor clock ops for the PHY
1407                  * clocks.  The clocks are actually gated by the
1408                  * PHY_AFEC0_DDRCLK_EN bits, which we should be
1409                  * setting if we use the DDR/DDR2 clocks.  However,
1410                  * vc4_dsi_encoder_enable() is setting up both AFEC0,
1411                  * setting both our parent DSI PLL's rate and this
1412                  * clock's rate, so it knows if DDR/DDR2 are going to
1413                  * be used and could enable the gates itself.
1414                  */
1415                 fix->mult = 1;
1416                 fix->div = phy_clocks[i].div;
1417                 fix->hw.init = &init;
1418 
1419                 memset(&init, 0, sizeof(init));
1420                 init.parent_names = &parent_name;
1421                 init.num_parents = 1;
1422                 if (dsi->port == 1)
1423                         init.name = phy_clocks[i].dsi1_name;
1424                 else
1425                         init.name = phy_clocks[i].dsi0_name;
1426                 init.ops = &clk_fixed_factor_ops;
1427 
1428                 ret = devm_clk_hw_register(dev, &fix->hw);
1429                 if (ret)
1430                         return ret;
1431 
1432                 dsi->clk_onecell->hws[i] = &fix->hw;
1433         }
1434 
1435         return of_clk_add_hw_provider(dev->of_node,
1436                                       of_clk_hw_onecell_get,
1437                                       dsi->clk_onecell);
1438 }
1439 
1440 static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1441 {
1442         struct platform_device *pdev = to_platform_device(dev);
1443         struct drm_device *drm = dev_get_drvdata(master);
1444         struct vc4_dev *vc4 = to_vc4_dev(drm);
1445         struct vc4_dsi *dsi = dev_get_drvdata(dev);
1446         struct vc4_dsi_encoder *vc4_dsi_encoder;
1447         struct drm_panel *panel;
1448         const struct of_device_id *match;
1449         dma_cap_mask_t dma_mask;
1450         int ret;
1451 
1452         match = of_match_device(vc4_dsi_dt_match, dev);
1453         if (!match)
1454                 return -ENODEV;
1455 
1456         dsi->port = (uintptr_t)match->data;
1457 
1458         vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),
1459                                        GFP_KERNEL);
1460         if (!vc4_dsi_encoder)
1461                 return -ENOMEM;
1462         vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;
1463         vc4_dsi_encoder->dsi = dsi;
1464         dsi->encoder = &vc4_dsi_encoder->base.base;
1465 
1466         dsi->regs = vc4_ioremap_regs(pdev, 0);
1467         if (IS_ERR(dsi->regs))
1468                 return PTR_ERR(dsi->regs);
1469 
1470         dsi->regset.base = dsi->regs;
1471         if (dsi->port == 0) {
1472                 dsi->regset.regs = dsi0_regs;
1473                 dsi->regset.nregs = ARRAY_SIZE(dsi0_regs);
1474         } else {
1475                 dsi->regset.regs = dsi1_regs;
1476                 dsi->regset.nregs = ARRAY_SIZE(dsi1_regs);
1477         }
1478 
1479         if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1480                 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1481                         DSI_PORT_READ(ID), DSI_ID_VALUE);
1482                 return -ENODEV;
1483         }
1484 
1485         /* DSI1 has a broken AXI slave that doesn't respond to writes
1486          * from the ARM.  It does handle writes from the DMA engine,
1487          * so set up a channel for talking to it.
1488          */
1489         if (dsi->port == 1) {
1490                 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1491                                                       &dsi->reg_dma_paddr,
1492                                                       GFP_KERNEL);
1493                 if (!dsi->reg_dma_mem) {
1494                         DRM_ERROR("Failed to get DMA memory\n");
1495                         return -ENOMEM;
1496                 }
1497 
1498                 dma_cap_zero(dma_mask);
1499                 dma_cap_set(DMA_MEMCPY, dma_mask);
1500                 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1501                 if (IS_ERR(dsi->reg_dma_chan)) {
1502                         ret = PTR_ERR(dsi->reg_dma_chan);
1503                         if (ret != -EPROBE_DEFER)
1504                                 DRM_ERROR("Failed to get DMA channel: %d\n",
1505                                           ret);
1506                         return ret;
1507                 }
1508 
1509                 /* Get the physical address of the device's registers.  The
1510                  * struct resource for the regs gives us the bus address
1511                  * instead.
1512                  */
1513                 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1514                                                              0, NULL, NULL));
1515         }
1516 
1517         init_completion(&dsi->xfer_completion);
1518         /* At startup enable error-reporting interrupts and nothing else. */
1519         DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1520         /* Clear any existing interrupt state. */
1521         DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1522 
1523         if (dsi->reg_dma_mem)
1524                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1525                                                 vc4_dsi_irq_defer_to_thread_handler,
1526                                                 vc4_dsi_irq_handler,
1527                                                 IRQF_ONESHOT,
1528                                                 "vc4 dsi", dsi);
1529         else
1530                 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1531                                        vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1532         if (ret) {
1533                 if (ret != -EPROBE_DEFER)
1534                         dev_err(dev, "Failed to get interrupt: %d\n", ret);
1535                 return ret;
1536         }
1537 
1538         dsi->escape_clock = devm_clk_get(dev, "escape");
1539         if (IS_ERR(dsi->escape_clock)) {
1540                 ret = PTR_ERR(dsi->escape_clock);
1541                 if (ret != -EPROBE_DEFER)
1542                         dev_err(dev, "Failed to get escape clock: %d\n", ret);
1543                 return ret;
1544         }
1545 
1546         dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1547         if (IS_ERR(dsi->pll_phy_clock)) {
1548                 ret = PTR_ERR(dsi->pll_phy_clock);
1549                 if (ret != -EPROBE_DEFER)
1550                         dev_err(dev, "Failed to get phy clock: %d\n", ret);
1551                 return ret;
1552         }
1553 
1554         dsi->pixel_clock = devm_clk_get(dev, "pixel");
1555         if (IS_ERR(dsi->pixel_clock)) {
1556                 ret = PTR_ERR(dsi->pixel_clock);
1557                 if (ret != -EPROBE_DEFER)
1558                         dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1559                 return ret;
1560         }
1561 
1562         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1563                                           &panel, &dsi->bridge);
1564         if (ret) {
1565                 /* If the bridge or panel pointed by dev->of_node is not
1566                  * enabled, just return 0 here so that we don't prevent the DRM
1567                  * dev from being registered. Of course that means the DSI
1568                  * encoder won't be exposed, but that's not a problem since
1569                  * nothing is connected to it.
1570                  */
1571                 if (ret == -ENODEV)
1572                         return 0;
1573 
1574                 return ret;
1575         }
1576 
1577         if (panel) {
1578                 dsi->bridge = devm_drm_panel_bridge_add(dev, panel,
1579                                                         DRM_MODE_CONNECTOR_DSI);
1580                 if (IS_ERR(dsi->bridge))
1581                         return PTR_ERR(dsi->bridge);
1582         }
1583 
1584         /* The esc clock rate is supposed to always be 100Mhz. */
1585         ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1586         if (ret) {
1587                 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1588                 return ret;
1589         }
1590 
1591         ret = vc4_dsi_init_phy_clocks(dsi);
1592         if (ret)
1593                 return ret;
1594 
1595         if (dsi->port == 1)
1596                 vc4->dsi1 = dsi;
1597 
1598         drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs,
1599                          DRM_MODE_ENCODER_DSI, NULL);
1600         drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
1601 
1602         ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL);
1603         if (ret) {
1604                 dev_err(dev, "bridge attach failed: %d\n", ret);
1605                 return ret;
1606         }
1607         /* Disable the atomic helper calls into the bridge.  We
1608          * manually call the bridge pre_enable / enable / etc. calls
1609          * from our driver, since we need to sequence them within the
1610          * encoder's enable/disable paths.
1611          */
1612         dsi->encoder->bridge = NULL;
1613 
1614         if (dsi->port == 0)
1615                 vc4_debugfs_add_regset32(drm, "dsi0_regs", &dsi->regset);
1616         else
1617                 vc4_debugfs_add_regset32(drm, "dsi1_regs", &dsi->regset);
1618 
1619         pm_runtime_enable(dev);
1620 
1621         return 0;
1622 }
1623 
1624 static void vc4_dsi_unbind(struct device *dev, struct device *master,
1625                            void *data)
1626 {
1627         struct drm_device *drm = dev_get_drvdata(master);
1628         struct vc4_dev *vc4 = to_vc4_dev(drm);
1629         struct vc4_dsi *dsi = dev_get_drvdata(dev);
1630 
1631         if (dsi->bridge)
1632                 pm_runtime_disable(dev);
1633 
1634         vc4_dsi_encoder_destroy(dsi->encoder);
1635 
1636         if (dsi->port == 1)
1637                 vc4->dsi1 = NULL;
1638 }
1639 
1640 static const struct component_ops vc4_dsi_ops = {
1641         .bind   = vc4_dsi_bind,
1642         .unbind = vc4_dsi_unbind,
1643 };
1644 
1645 static int vc4_dsi_dev_probe(struct platform_device *pdev)
1646 {
1647         struct device *dev = &pdev->dev;
1648         struct vc4_dsi *dsi;
1649         int ret;
1650 
1651         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1652         if (!dsi)
1653                 return -ENOMEM;
1654         dev_set_drvdata(dev, dsi);
1655 
1656         dsi->pdev = pdev;
1657 
1658         /* Note, the initialization sequence for DSI and panels is
1659          * tricky.  The component bind above won't get past its
1660          * -EPROBE_DEFER until the panel/bridge probes.  The
1661          * panel/bridge will return -EPROBE_DEFER until it has a
1662          * mipi_dsi_host to register its device to.  So, we register
1663          * the host during pdev probe time, so vc4 as a whole can then
1664          * -EPROBE_DEFER its component bind process until the panel
1665          * successfully attaches.
1666          */
1667         dsi->dsi_host.ops = &vc4_dsi_host_ops;
1668         dsi->dsi_host.dev = dev;
1669         mipi_dsi_host_register(&dsi->dsi_host);
1670 
1671         ret = component_add(&pdev->dev, &vc4_dsi_ops);
1672         if (ret) {
1673                 mipi_dsi_host_unregister(&dsi->dsi_host);
1674                 return ret;
1675         }
1676 
1677         return 0;
1678 }
1679 
1680 static int vc4_dsi_dev_remove(struct platform_device *pdev)
1681 {
1682         struct device *dev = &pdev->dev;
1683         struct vc4_dsi *dsi = dev_get_drvdata(dev);
1684 
1685         component_del(&pdev->dev, &vc4_dsi_ops);
1686         mipi_dsi_host_unregister(&dsi->dsi_host);
1687 
1688         return 0;
1689 }
1690 
1691 struct platform_driver vc4_dsi_driver = {
1692         .probe = vc4_dsi_dev_probe,
1693         .remove = vc4_dsi_dev_remove,
1694         .driver = {
1695                 .name = "vc4_dsi",
1696                 .of_match_table = vc4_dsi_dt_match,
1697         },
1698 };
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/vc4/vc4_dsi.c

DEFINITIONS
