This source file includes following definitions.
- virtio_gpu_object_ref
- virtio_gpu_object_unref
- virtio_gpu_object_mmap_offset
- virtio_gpu_object_reserve
- virtio_gpu_object_unreserve
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 #ifndef VIRTIO_DRV_H
27 #define VIRTIO_DRV_H
28
29 #include <linux/virtio.h>
30 #include <linux/virtio_ids.h>
31 #include <linux/virtio_config.h>
32 #include <linux/virtio_gpu.h>
33
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_fb_helper.h>
37 #include <drm/drm_gem.h>
38 #include <drm/drm_ioctl.h>
39 #include <drm/drm_probe_helper.h>
40 #include <drm/ttm/ttm_bo_api.h>
41 #include <drm/ttm/ttm_bo_driver.h>
42 #include <drm/ttm/ttm_module.h>
43 #include <drm/ttm/ttm_placement.h>
44
45 #define DRIVER_NAME "virtio_gpu"
46 #define DRIVER_DESC "virtio GPU"
47 #define DRIVER_DATE "0"
48
49 #define DRIVER_MAJOR 0
50 #define DRIVER_MINOR 1
51 #define DRIVER_PATCHLEVEL 0
52
53 struct virtio_gpu_object_params {
54 uint32_t format;
55 uint32_t width;
56 uint32_t height;
57 unsigned long size;
58 bool dumb;
59
60 bool virgl;
61 uint32_t target;
62 uint32_t bind;
63 uint32_t depth;
64 uint32_t array_size;
65 uint32_t last_level;
66 uint32_t nr_samples;
67 uint32_t flags;
68 };
69
70 struct virtio_gpu_object {
71 struct drm_gem_object gem_base;
72 uint32_t hw_res_handle;
73
74 struct sg_table *pages;
75 uint32_t mapped;
76 void *vmap;
77 bool dumb;
78 struct ttm_place placement_code;
79 struct ttm_placement placement;
80 struct ttm_buffer_object tbo;
81 struct ttm_bo_kmap_obj kmap;
82 bool created;
83 };
84 #define gem_to_virtio_gpu_obj(gobj) \
85 container_of((gobj), struct virtio_gpu_object, gem_base)
86
87 struct virtio_gpu_vbuffer;
88 struct virtio_gpu_device;
89
90 typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
91 struct virtio_gpu_vbuffer *vbuf);
92
93 struct virtio_gpu_fence_driver {
94 atomic64_t last_seq;
95 uint64_t sync_seq;
96 uint64_t context;
97 struct list_head fences;
98 spinlock_t lock;
99 };
100
101 struct virtio_gpu_fence {
102 struct dma_fence f;
103 struct virtio_gpu_fence_driver *drv;
104 struct list_head node;
105 };
106 #define to_virtio_fence(x) \
107 container_of(x, struct virtio_gpu_fence, f)
108
109 struct virtio_gpu_vbuffer {
110 char *buf;
111 int size;
112
113 void *data_buf;
114 uint32_t data_size;
115
116 char *resp_buf;
117 int resp_size;
118
119 virtio_gpu_resp_cb resp_cb;
120
121 struct list_head list;
122 };
123
124 struct virtio_gpu_output {
125 int index;
126 struct drm_crtc crtc;
127 struct drm_connector conn;
128 struct drm_encoder enc;
129 struct virtio_gpu_display_one info;
130 struct virtio_gpu_update_cursor cursor;
131 struct edid *edid;
132 int cur_x;
133 int cur_y;
134 bool enabled;
135 };
136 #define drm_crtc_to_virtio_gpu_output(x) \
137 container_of(x, struct virtio_gpu_output, crtc)
138 #define drm_connector_to_virtio_gpu_output(x) \
139 container_of(x, struct virtio_gpu_output, conn)
140 #define drm_encoder_to_virtio_gpu_output(x) \
141 container_of(x, struct virtio_gpu_output, enc)
142
143 struct virtio_gpu_framebuffer {
144 struct drm_framebuffer base;
145 struct virtio_gpu_fence *fence;
146 };
147 #define to_virtio_gpu_framebuffer(x) \
148 container_of(x, struct virtio_gpu_framebuffer, base)
149
150 struct virtio_gpu_mman {
151 struct ttm_bo_device bdev;
152 };
153
154 struct virtio_gpu_queue {
155 struct virtqueue *vq;
156 spinlock_t qlock;
157 wait_queue_head_t ack_queue;
158 struct work_struct dequeue_work;
159 };
160
161 struct virtio_gpu_drv_capset {
162 uint32_t id;
163 uint32_t max_version;
164 uint32_t max_size;
165 };
166
167 struct virtio_gpu_drv_cap_cache {
168 struct list_head head;
169 void *caps_cache;
170 uint32_t id;
171 uint32_t version;
172 uint32_t size;
173 atomic_t is_valid;
174 };
175
176 struct virtio_gpu_device {
177 struct device *dev;
178 struct drm_device *ddev;
179
180 struct virtio_device *vdev;
181
182 struct virtio_gpu_mman mman;
183
184 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
185 uint32_t num_scanouts;
186
187 struct virtio_gpu_queue ctrlq;
188 struct virtio_gpu_queue cursorq;
189 struct kmem_cache *vbufs;
190 bool vqs_ready;
191
192 struct ida resource_ida;
193
194 wait_queue_head_t resp_wq;
195
196 spinlock_t display_info_lock;
197 bool display_info_pending;
198
199 struct virtio_gpu_fence_driver fence_drv;
200
201 struct ida ctx_id_ida;
202
203 bool has_virgl_3d;
204 bool has_edid;
205
206 struct work_struct config_changed_work;
207
208 struct virtio_gpu_drv_capset *capsets;
209 uint32_t num_capsets;
210 struct list_head cap_cache;
211 };
212
213 struct virtio_gpu_fpriv {
214 uint32_t ctx_id;
215 };
216
217
218 #define DRM_VIRTIO_NUM_IOCTLS 10
219 extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
220 int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
221 struct list_head *head);
222 void virtio_gpu_unref_list(struct list_head *head);
223
224
225 int virtio_gpu_init(struct drm_device *dev);
226 void virtio_gpu_deinit(struct drm_device *dev);
227 int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
228 void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
229
230
231 void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj);
232 int virtio_gpu_gem_init(struct virtio_gpu_device *vgdev);
233 void virtio_gpu_gem_fini(struct virtio_gpu_device *vgdev);
234 int virtio_gpu_gem_create(struct drm_file *file,
235 struct drm_device *dev,
236 struct virtio_gpu_object_params *params,
237 struct drm_gem_object **obj_p,
238 uint32_t *handle_p);
239 int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
240 struct drm_file *file);
241 void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
242 struct drm_file *file);
243 struct virtio_gpu_object*
244 virtio_gpu_alloc_object(struct drm_device *dev,
245 struct virtio_gpu_object_params *params,
246 struct virtio_gpu_fence *fence);
247 int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
248 struct drm_device *dev,
249 struct drm_mode_create_dumb *args);
250 int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
251 struct drm_device *dev,
252 uint32_t handle, uint64_t *offset_p);
253
254
255 int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
256 void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
257 void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
258 struct virtio_gpu_object *bo,
259 struct virtio_gpu_object_params *params,
260 struct virtio_gpu_fence *fence);
261 void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
262 uint32_t resource_id);
263 void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
264 struct virtio_gpu_object *bo,
265 uint64_t offset,
266 __le32 width, __le32 height,
267 __le32 x, __le32 y,
268 struct virtio_gpu_fence *fence);
269 void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
270 uint32_t resource_id,
271 uint32_t x, uint32_t y,
272 uint32_t width, uint32_t height);
273 void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
274 uint32_t scanout_id, uint32_t resource_id,
275 uint32_t width, uint32_t height,
276 uint32_t x, uint32_t y);
277 int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
278 struct virtio_gpu_object *obj,
279 struct virtio_gpu_fence *fence);
280 void virtio_gpu_object_detach(struct virtio_gpu_device *vgdev,
281 struct virtio_gpu_object *obj);
282 int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
283 int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
284 void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
285 struct virtio_gpu_output *output);
286 int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
287 int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
288 int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
289 int idx, int version,
290 struct virtio_gpu_drv_cap_cache **cache_p);
291 int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
292 void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
293 uint32_t nlen, const char *name);
294 void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
295 uint32_t id);
296 void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
297 uint32_t ctx_id,
298 uint32_t resource_id);
299 void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
300 uint32_t ctx_id,
301 uint32_t resource_id);
302 void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
303 void *data, uint32_t data_size,
304 uint32_t ctx_id, struct virtio_gpu_fence *fence);
305 void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
306 uint32_t resource_id, uint32_t ctx_id,
307 uint64_t offset, uint32_t level,
308 struct virtio_gpu_box *box,
309 struct virtio_gpu_fence *fence);
310 void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
311 struct virtio_gpu_object *bo,
312 uint32_t ctx_id,
313 uint64_t offset, uint32_t level,
314 struct virtio_gpu_box *box,
315 struct virtio_gpu_fence *fence);
316 void
317 virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
318 struct virtio_gpu_object *bo,
319 struct virtio_gpu_object_params *params,
320 struct virtio_gpu_fence *fence);
321 void virtio_gpu_ctrl_ack(struct virtqueue *vq);
322 void virtio_gpu_cursor_ack(struct virtqueue *vq);
323 void virtio_gpu_fence_ack(struct virtqueue *vq);
324 void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
325 void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
326 void virtio_gpu_dequeue_fence_func(struct work_struct *work);
327
328
329 int virtio_gpu_framebuffer_init(struct drm_device *dev,
330 struct virtio_gpu_framebuffer *vgfb,
331 const struct drm_mode_fb_cmd2 *mode_cmd,
332 struct drm_gem_object *obj);
333 void virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
334 void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
335
336
337 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
338 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
339 enum drm_plane_type type,
340 int index);
341
342
343 int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev);
344 void virtio_gpu_ttm_fini(struct virtio_gpu_device *vgdev);
345 int virtio_gpu_mmap(struct file *filp, struct vm_area_struct *vma);
346
347
348 bool virtio_fence_signaled(struct dma_fence *f);
349 struct virtio_gpu_fence *virtio_gpu_fence_alloc(
350 struct virtio_gpu_device *vgdev);
351 void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
352 struct virtio_gpu_ctrl_hdr *cmd_hdr,
353 struct virtio_gpu_fence *fence);
354 void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
355 u64 last_seq);
356
357
358 int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
359 struct virtio_gpu_object_params *params,
360 struct virtio_gpu_object **bo_ptr,
361 struct virtio_gpu_fence *fence);
362 void virtio_gpu_object_kunmap(struct virtio_gpu_object *bo);
363 int virtio_gpu_object_kmap(struct virtio_gpu_object *bo);
364 int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
365 struct virtio_gpu_object *bo);
366 void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo);
367 int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait);
368
369
370 struct sg_table *virtgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
371 struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
372 struct drm_device *dev, struct dma_buf_attachment *attach,
373 struct sg_table *sgt);
374 void *virtgpu_gem_prime_vmap(struct drm_gem_object *obj);
375 void virtgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
376 int virtgpu_gem_prime_mmap(struct drm_gem_object *obj,
377 struct vm_area_struct *vma);
378
379 static inline struct virtio_gpu_object*
380 virtio_gpu_object_ref(struct virtio_gpu_object *bo)
381 {
382 ttm_bo_get(&bo->tbo);
383 return bo;
384 }
385
386 static inline void virtio_gpu_object_unref(struct virtio_gpu_object **bo)
387 {
388 struct ttm_buffer_object *tbo;
389
390 if ((*bo) == NULL)
391 return;
392 tbo = &((*bo)->tbo);
393 ttm_bo_put(tbo);
394 *bo = NULL;
395 }
396
397 static inline u64 virtio_gpu_object_mmap_offset(struct virtio_gpu_object *bo)
398 {
399 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
400 }
401
402 static inline int virtio_gpu_object_reserve(struct virtio_gpu_object *bo,
403 bool no_wait)
404 {
405 int r;
406
407 r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
408 if (unlikely(r != 0)) {
409 if (r != -ERESTARTSYS) {
410 struct virtio_gpu_device *qdev =
411 bo->gem_base.dev->dev_private;
412 dev_err(qdev->dev, "%p reserve failed\n", bo);
413 }
414 return r;
415 }
416 return 0;
417 }
418
419 static inline void virtio_gpu_object_unreserve(struct virtio_gpu_object *bo)
420 {
421 ttm_bo_unreserve(&bo->tbo);
422 }
423
424
425 int virtio_gpu_debugfs_init(struct drm_minor *minor);
426
427 #endif