root/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c

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DEFINITIONS

This source file includes following definitions.
  1. panel_to_otm8009a
  2. otm8009a_dcs_write_buf
  3. otm8009a_dcs_write_buf_hs
  4. otm8009a_init_sequence
  5. otm8009a_disable
  6. otm8009a_unprepare
  7. otm8009a_prepare
  8. otm8009a_enable
  9. otm8009a_get_modes
  10. otm8009a_backlight_update_status
  11. otm8009a_probe
  12. otm8009a_remove

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2017
   4  *
   5  * Authors: Philippe Cornu <philippe.cornu@st.com>
   6  *          Yannick Fertre <yannick.fertre@st.com>
   7  */
   8 
   9 #include <linux/backlight.h>
  10 #include <linux/delay.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/module.h>
  13 #include <linux/regulator/consumer.h>
  14 
  15 #include <video/mipi_display.h>
  16 
  17 #include <drm/drm_mipi_dsi.h>
  18 #include <drm/drm_modes.h>
  19 #include <drm/drm_panel.h>
  20 #include <drm/drm_print.h>
  21 
  22 #define OTM8009A_BACKLIGHT_DEFAULT      240
  23 #define OTM8009A_BACKLIGHT_MAX          255
  24 
  25 /* Manufacturer Command Set */
  26 #define MCS_ADRSFT      0x0000  /* Address Shift Function */
  27 #define MCS_PANSET      0xB3A6  /* Panel Type Setting */
  28 #define MCS_SD_CTRL     0xC0A2  /* Source Driver Timing Setting */
  29 #define MCS_P_DRV_M     0xC0B4  /* Panel Driving Mode */
  30 #define MCS_OSC_ADJ     0xC181  /* Oscillator Adjustment for Idle/Normal mode */
  31 #define MCS_RGB_VID_SET 0xC1A1  /* RGB Video Mode Setting */
  32 #define MCS_SD_PCH_CTRL 0xC480  /* Source Driver Precharge Control */
  33 #define MCS_NO_DOC1     0xC48A  /* Command not documented */
  34 #define MCS_PWR_CTRL1   0xC580  /* Power Control Setting 1 */
  35 #define MCS_PWR_CTRL2   0xC590  /* Power Control Setting 2 for Normal Mode */
  36 #define MCS_PWR_CTRL4   0xC5B0  /* Power Control Setting 4 for DC Voltage */
  37 #define MCS_PANCTRLSET1 0xCB80  /* Panel Control Setting 1 */
  38 #define MCS_PANCTRLSET2 0xCB90  /* Panel Control Setting 2 */
  39 #define MCS_PANCTRLSET3 0xCBA0  /* Panel Control Setting 3 */
  40 #define MCS_PANCTRLSET4 0xCBB0  /* Panel Control Setting 4 */
  41 #define MCS_PANCTRLSET5 0xCBC0  /* Panel Control Setting 5 */
  42 #define MCS_PANCTRLSET6 0xCBD0  /* Panel Control Setting 6 */
  43 #define MCS_PANCTRLSET7 0xCBE0  /* Panel Control Setting 7 */
  44 #define MCS_PANCTRLSET8 0xCBF0  /* Panel Control Setting 8 */
  45 #define MCS_PANU2D1     0xCC80  /* Panel U2D Setting 1 */
  46 #define MCS_PANU2D2     0xCC90  /* Panel U2D Setting 2 */
  47 #define MCS_PANU2D3     0xCCA0  /* Panel U2D Setting 3 */
  48 #define MCS_PAND2U1     0xCCB0  /* Panel D2U Setting 1 */
  49 #define MCS_PAND2U2     0xCCC0  /* Panel D2U Setting 2 */
  50 #define MCS_PAND2U3     0xCCD0  /* Panel D2U Setting 3 */
  51 #define MCS_GOAVST      0xCE80  /* GOA VST Setting */
  52 #define MCS_GOACLKA1    0xCEA0  /* GOA CLKA1 Setting */
  53 #define MCS_GOACLKA3    0xCEB0  /* GOA CLKA3 Setting */
  54 #define MCS_GOAECLK     0xCFC0  /* GOA ECLK Setting */
  55 #define MCS_NO_DOC2     0xCFD0  /* Command not documented */
  56 #define MCS_GVDDSET     0xD800  /* GVDD/NGVDD */
  57 #define MCS_VCOMDC      0xD900  /* VCOM Voltage Setting */
  58 #define MCS_GMCT2_2P    0xE100  /* Gamma Correction 2.2+ Setting */
  59 #define MCS_GMCT2_2N    0xE200  /* Gamma Correction 2.2- Setting */
  60 #define MCS_NO_DOC3     0xF5B6  /* Command not documented */
  61 #define MCS_CMD2_ENA1   0xFF00  /* Enable Access Command2 "CMD2" */
  62 #define MCS_CMD2_ENA2   0xFF80  /* Enable Access Orise Command2 */
  63 
  64 struct otm8009a {
  65         struct device *dev;
  66         struct drm_panel panel;
  67         struct backlight_device *bl_dev;
  68         struct gpio_desc *reset_gpio;
  69         struct regulator *supply;
  70         bool prepared;
  71         bool enabled;
  72 };
  73 
  74 static const struct drm_display_mode default_mode = {
  75         .clock = 29700,
  76         .hdisplay = 480,
  77         .hsync_start = 480 + 98,
  78         .hsync_end = 480 + 98 + 32,
  79         .htotal = 480 + 98 + 32 + 98,
  80         .vdisplay = 800,
  81         .vsync_start = 800 + 15,
  82         .vsync_end = 800 + 15 + 10,
  83         .vtotal = 800 + 15 + 10 + 14,
  84         .vrefresh = 50,
  85         .flags = 0,
  86         .width_mm = 52,
  87         .height_mm = 86,
  88 };
  89 
  90 static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)
  91 {
  92         return container_of(panel, struct otm8009a, panel);
  93 }
  94 
  95 static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data,
  96                                    size_t len)
  97 {
  98         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  99 
 100         if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0)
 101                 DRM_WARN("mipi dsi dcs write buffer failed\n");
 102 }
 103 
 104 static void otm8009a_dcs_write_buf_hs(struct otm8009a *ctx, const void *data,
 105                                       size_t len)
 106 {
 107         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 108 
 109         /* data will be sent in dsi hs mode (ie. no lpm) */
 110         dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
 111 
 112         otm8009a_dcs_write_buf(ctx, data, len);
 113 
 114         /* restore back the dsi lpm mode */
 115         dsi->mode_flags |= MIPI_DSI_MODE_LPM;
 116 }
 117 
 118 #define dcs_write_seq(ctx, seq...)                      \
 119 ({                                                      \
 120         static const u8 d[] = { seq };                  \
 121         otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d));  \
 122 })
 123 
 124 #define dcs_write_cmd_at(ctx, cmd, seq...)              \
 125 ({                                                      \
 126         dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF);   \
 127         dcs_write_seq(ctx, (cmd) >> 8, seq);            \
 128 })
 129 
 130 static int otm8009a_init_sequence(struct otm8009a *ctx)
 131 {
 132         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 133         int ret;
 134 
 135         /* Enter CMD2 */
 136         dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
 137 
 138         /* Enter Orise Command2 */
 139         dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09);
 140 
 141         dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30);
 142         mdelay(10);
 143 
 144         dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40);
 145         mdelay(10);
 146 
 147         dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9);
 148         dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34);
 149         dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50);
 150         dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E);
 151         dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */
 152         dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01);
 153         dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34);
 154         dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33);
 155         dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79);
 156         dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B);
 157         dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83);
 158         dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83);
 159         dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E);
 160         dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01);
 161 
 162         dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
 163         dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
 164                          0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
 165         dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
 166                          0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
 167         dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
 168                          0x01, 0x02, 0x00, 0x00);
 169 
 170         dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00);
 171 
 172         dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 173         dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 174                          0, 0, 0, 0, 0);
 175         dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 176                          0, 0, 0, 0, 0);
 177         dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 178         dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
 179                          0, 0, 0, 0, 0);
 180         dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
 181                          4, 0, 0, 0, 0);
 182         dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 183         dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 184                          0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
 185 
 186         dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
 187                          0x00, 0x00, 0x00, 0x00);
 188         dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 189                          0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
 190         dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
 191                          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 192         dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
 193                          0x00, 0x00, 0x00, 0x00);
 194         dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 195                          0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
 196         dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
 197                          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 198 
 199         dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66);
 200 
 201         dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06);
 202 
 203         dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
 204                          0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
 205                          0x01);
 206         dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
 207                          0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
 208                          0x01);
 209 
 210         /* Exit CMD2 */
 211         dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
 212 
 213         ret = mipi_dsi_dcs_nop(dsi);
 214         if (ret)
 215                 return ret;
 216 
 217         ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 218         if (ret)
 219                 return ret;
 220 
 221         /* Wait for sleep out exit */
 222         mdelay(120);
 223 
 224         /* Default portrait 480x800 rgb24 */
 225         dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
 226 
 227         ret = mipi_dsi_dcs_set_column_address(dsi, 0,
 228                                               default_mode.hdisplay - 1);
 229         if (ret)
 230                 return ret;
 231 
 232         ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1);
 233         if (ret)
 234                 return ret;
 235 
 236         /* See otm8009a driver documentation for pixel format descriptions */
 237         ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT |
 238                                             MIPI_DCS_PIXEL_FMT_24BIT << 4);
 239         if (ret)
 240                 return ret;
 241 
 242         /* Disable CABC feature */
 243         dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
 244 
 245         ret = mipi_dsi_dcs_set_display_on(dsi);
 246         if (ret)
 247                 return ret;
 248 
 249         ret = mipi_dsi_dcs_nop(dsi);
 250         if (ret)
 251                 return ret;
 252 
 253         /* Send Command GRAM memory write (no parameters) */
 254         dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START);
 255 
 256         /* Wait a short while to let the panel be ready before the 1st frame */
 257         mdelay(10);
 258 
 259         return 0;
 260 }
 261 
 262 static int otm8009a_disable(struct drm_panel *panel)
 263 {
 264         struct otm8009a *ctx = panel_to_otm8009a(panel);
 265         struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 266         int ret;
 267 
 268         if (!ctx->enabled)
 269                 return 0; /* This is not an issue so we return 0 here */
 270 
 271         backlight_disable(ctx->bl_dev);
 272 
 273         ret = mipi_dsi_dcs_set_display_off(dsi);
 274         if (ret)
 275                 return ret;
 276 
 277         ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
 278         if (ret)
 279                 return ret;
 280 
 281         msleep(120);
 282 
 283         ctx->enabled = false;
 284 
 285         return 0;
 286 }
 287 
 288 static int otm8009a_unprepare(struct drm_panel *panel)
 289 {
 290         struct otm8009a *ctx = panel_to_otm8009a(panel);
 291 
 292         if (!ctx->prepared)
 293                 return 0;
 294 
 295         if (ctx->reset_gpio) {
 296                 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 297                 msleep(20);
 298         }
 299 
 300         regulator_disable(ctx->supply);
 301 
 302         ctx->prepared = false;
 303 
 304         return 0;
 305 }
 306 
 307 static int otm8009a_prepare(struct drm_panel *panel)
 308 {
 309         struct otm8009a *ctx = panel_to_otm8009a(panel);
 310         int ret;
 311 
 312         if (ctx->prepared)
 313                 return 0;
 314 
 315         ret = regulator_enable(ctx->supply);
 316         if (ret < 0) {
 317                 DRM_ERROR("failed to enable supply: %d\n", ret);
 318                 return ret;
 319         }
 320 
 321         if (ctx->reset_gpio) {
 322                 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
 323                 gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 324                 msleep(20);
 325                 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
 326                 msleep(100);
 327         }
 328 
 329         ret = otm8009a_init_sequence(ctx);
 330         if (ret)
 331                 return ret;
 332 
 333         ctx->prepared = true;
 334 
 335         return 0;
 336 }
 337 
 338 static int otm8009a_enable(struct drm_panel *panel)
 339 {
 340         struct otm8009a *ctx = panel_to_otm8009a(panel);
 341 
 342         if (ctx->enabled)
 343                 return 0;
 344 
 345         backlight_enable(ctx->bl_dev);
 346 
 347         ctx->enabled = true;
 348 
 349         return 0;
 350 }
 351 
 352 static int otm8009a_get_modes(struct drm_panel *panel)
 353 {
 354         struct drm_display_mode *mode;
 355 
 356         mode = drm_mode_duplicate(panel->drm, &default_mode);
 357         if (!mode) {
 358                 DRM_ERROR("failed to add mode %ux%ux@%u\n",
 359                           default_mode.hdisplay, default_mode.vdisplay,
 360                           default_mode.vrefresh);
 361                 return -ENOMEM;
 362         }
 363 
 364         drm_mode_set_name(mode);
 365 
 366         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 367         drm_mode_probed_add(panel->connector, mode);
 368 
 369         panel->connector->display_info.width_mm = mode->width_mm;
 370         panel->connector->display_info.height_mm = mode->height_mm;
 371 
 372         return 1;
 373 }
 374 
 375 static const struct drm_panel_funcs otm8009a_drm_funcs = {
 376         .disable   = otm8009a_disable,
 377         .unprepare = otm8009a_unprepare,
 378         .prepare   = otm8009a_prepare,
 379         .enable    = otm8009a_enable,
 380         .get_modes = otm8009a_get_modes,
 381 };
 382 
 383 /*
 384  * DSI-BASED BACKLIGHT
 385  */
 386 
 387 static int otm8009a_backlight_update_status(struct backlight_device *bd)
 388 {
 389         struct otm8009a *ctx = bl_get_data(bd);
 390         u8 data[2];
 391 
 392         if (!ctx->prepared) {
 393                 DRM_DEBUG("lcd not ready yet for setting its backlight!\n");
 394                 return -ENXIO;
 395         }
 396 
 397         if (bd->props.power <= FB_BLANK_NORMAL) {
 398                 /* Power on the backlight with the requested brightness
 399                  * Note We can not use mipi_dsi_dcs_set_display_brightness()
 400                  * as otm8009a driver support only 8-bit brightness (1 param).
 401                  */
 402                 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;
 403                 data[1] = bd->props.brightness;
 404                 otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
 405 
 406                 /* set Brightness Control & Backlight on */
 407                 data[1] = 0x24;
 408 
 409         } else {
 410                 /* Power off the backlight: set Brightness Control & Bl off */
 411                 data[1] = 0;
 412         }
 413 
 414         /* Update Brightness Control & Backlight */
 415         data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;
 416         otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
 417 
 418         return 0;
 419 }
 420 
 421 static const struct backlight_ops otm8009a_backlight_ops = {
 422         .update_status = otm8009a_backlight_update_status,
 423 };
 424 
 425 static int otm8009a_probe(struct mipi_dsi_device *dsi)
 426 {
 427         struct device *dev = &dsi->dev;
 428         struct otm8009a *ctx;
 429         int ret;
 430 
 431         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 432         if (!ctx)
 433                 return -ENOMEM;
 434 
 435         ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
 436         if (IS_ERR(ctx->reset_gpio)) {
 437                 dev_err(dev, "cannot get reset-gpio\n");
 438                 return PTR_ERR(ctx->reset_gpio);
 439         }
 440 
 441         ctx->supply = devm_regulator_get(dev, "power");
 442         if (IS_ERR(ctx->supply)) {
 443                 ret = PTR_ERR(ctx->supply);
 444                 if (ret != -EPROBE_DEFER)
 445                         dev_err(dev, "failed to request regulator: %d\n", ret);
 446                 return ret;
 447         }
 448 
 449         mipi_dsi_set_drvdata(dsi, ctx);
 450 
 451         ctx->dev = dev;
 452 
 453         dsi->lanes = 2;
 454         dsi->format = MIPI_DSI_FMT_RGB888;
 455         dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
 456                           MIPI_DSI_MODE_LPM;
 457 
 458         drm_panel_init(&ctx->panel);
 459         ctx->panel.dev = dev;
 460         ctx->panel.funcs = &otm8009a_drm_funcs;
 461 
 462         ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev),
 463                                                      dsi->host->dev, ctx,
 464                                                      &otm8009a_backlight_ops,
 465                                                      NULL);
 466         if (IS_ERR(ctx->bl_dev)) {
 467                 ret = PTR_ERR(ctx->bl_dev);
 468                 dev_err(dev, "failed to register backlight: %d\n", ret);
 469                 return ret;
 470         }
 471 
 472         ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX;
 473         ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT;
 474         ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
 475         ctx->bl_dev->props.type = BACKLIGHT_RAW;
 476 
 477         drm_panel_add(&ctx->panel);
 478 
 479         ret = mipi_dsi_attach(dsi);
 480         if (ret < 0) {
 481                 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n");
 482                 drm_panel_remove(&ctx->panel);
 483                 backlight_device_unregister(ctx->bl_dev);
 484                 return ret;
 485         }
 486 
 487         return 0;
 488 }
 489 
 490 static int otm8009a_remove(struct mipi_dsi_device *dsi)
 491 {
 492         struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi);
 493 
 494         mipi_dsi_detach(dsi);
 495         drm_panel_remove(&ctx->panel);
 496 
 497         return 0;
 498 }
 499 
 500 static const struct of_device_id orisetech_otm8009a_of_match[] = {
 501         { .compatible = "orisetech,otm8009a" },
 502         { }
 503 };
 504 MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match);
 505 
 506 static struct mipi_dsi_driver orisetech_otm8009a_driver = {
 507         .probe  = otm8009a_probe,
 508         .remove = otm8009a_remove,
 509         .driver = {
 510                 .name = "panel-orisetech-otm8009a",
 511                 .of_match_table = orisetech_otm8009a_of_match,
 512         },
 513 };
 514 module_mipi_dsi_driver(orisetech_otm8009a_driver);
 515 
 516 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
 517 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
 518 MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel");
 519 MODULE_LICENSE("GPL v2");

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