root/drivers/gpu/drm/panel/panel-simple.c

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DEFINITIONS

This source file includes following definitions.
  1. to_panel_simple
  2. panel_simple_get_timings_modes
  3. panel_simple_get_display_modes
  4. panel_simple_get_non_edid_modes
  5. panel_simple_disable
  6. panel_simple_unprepare
  7. panel_simple_prepare
  8. panel_simple_enable
  9. panel_simple_get_modes
  10. panel_simple_get_timings
  11. panel_simple_parse_panel_timing_node
  12. panel_simple_probe
  13. panel_simple_remove
  14. panel_simple_shutdown
  15. panel_simple_platform_probe
  16. panel_simple_platform_remove
  17. panel_simple_platform_shutdown
  18. panel_simple_dsi_probe
  19. panel_simple_dsi_remove
  20. panel_simple_dsi_shutdown
  21. panel_simple_init
  22. panel_simple_exit

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23 
  24 #include <linux/backlight.h>
  25 #include <linux/delay.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/module.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/regulator/consumer.h>
  31 
  32 #include <video/display_timing.h>
  33 #include <video/of_display_timing.h>
  34 #include <video/videomode.h>
  35 
  36 #include <drm/drm_crtc.h>
  37 #include <drm/drm_device.h>
  38 #include <drm/drm_mipi_dsi.h>
  39 #include <drm/drm_panel.h>
  40 
  41 /**
  42  * @modes: Pointer to array of fixed modes appropriate for this panel.  If
  43  *         only one mode then this can just be the address of this the mode.
  44  *         NOTE: cannot be used with "timings" and also if this is specified
  45  *         then you cannot override the mode in the device tree.
  46  * @num_modes: Number of elements in modes array.
  47  * @timings: Pointer to array of display timings.  NOTE: cannot be used with
  48  *           "modes" and also these will be used to validate a device tree
  49  *           override if one is present.
  50  * @num_timings: Number of elements in timings array.
  51  * @bpc: Bits per color.
  52  * @size: Structure containing the physical size of this panel.
  53  * @delay: Structure containing various delay values for this panel.
  54  * @bus_format: See MEDIA_BUS_FMT_... defines.
  55  * @bus_flags: See DRM_BUS_FLAG_... defines.
  56  */
  57 struct panel_desc {
  58         const struct drm_display_mode *modes;
  59         unsigned int num_modes;
  60         const struct display_timing *timings;
  61         unsigned int num_timings;
  62 
  63         unsigned int bpc;
  64 
  65         /**
  66          * @width: width (in millimeters) of the panel's active display area
  67          * @height: height (in millimeters) of the panel's active display area
  68          */
  69         struct {
  70                 unsigned int width;
  71                 unsigned int height;
  72         } size;
  73 
  74         /**
  75          * @prepare: the time (in milliseconds) that it takes for the panel to
  76          *           become ready and start receiving video data
  77          * @hpd_absent_delay: Add this to the prepare delay if we know Hot
  78          *                    Plug Detect isn't used.
  79          * @enable: the time (in milliseconds) that it takes for the panel to
  80          *          display the first valid frame after starting to receive
  81          *          video data
  82          * @disable: the time (in milliseconds) that it takes for the panel to
  83          *           turn the display off (no content is visible)
  84          * @unprepare: the time (in milliseconds) that it takes for the panel
  85          *             to power itself down completely
  86          */
  87         struct {
  88                 unsigned int prepare;
  89                 unsigned int hpd_absent_delay;
  90                 unsigned int enable;
  91                 unsigned int disable;
  92                 unsigned int unprepare;
  93         } delay;
  94 
  95         u32 bus_format;
  96         u32 bus_flags;
  97 };
  98 
  99 struct panel_simple {
 100         struct drm_panel base;
 101         bool prepared;
 102         bool enabled;
 103         bool no_hpd;
 104 
 105         const struct panel_desc *desc;
 106 
 107         struct backlight_device *backlight;
 108         struct regulator *supply;
 109         struct i2c_adapter *ddc;
 110 
 111         struct gpio_desc *enable_gpio;
 112 
 113         struct drm_display_mode override_mode;
 114 };
 115 
 116 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 117 {
 118         return container_of(panel, struct panel_simple, base);
 119 }
 120 
 121 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel)
 122 {
 123         struct drm_connector *connector = panel->base.connector;
 124         struct drm_device *drm = panel->base.drm;
 125         struct drm_display_mode *mode;
 126         unsigned int i, num = 0;
 127 
 128         for (i = 0; i < panel->desc->num_timings; i++) {
 129                 const struct display_timing *dt = &panel->desc->timings[i];
 130                 struct videomode vm;
 131 
 132                 videomode_from_timing(dt, &vm);
 133                 mode = drm_mode_create(drm);
 134                 if (!mode) {
 135                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 136                                 dt->hactive.typ, dt->vactive.typ);
 137                         continue;
 138                 }
 139 
 140                 drm_display_mode_from_videomode(&vm, mode);
 141 
 142                 mode->type |= DRM_MODE_TYPE_DRIVER;
 143 
 144                 if (panel->desc->num_timings == 1)
 145                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 146 
 147                 drm_mode_probed_add(connector, mode);
 148                 num++;
 149         }
 150 
 151         return num;
 152 }
 153 
 154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel)
 155 {
 156         struct drm_connector *connector = panel->base.connector;
 157         struct drm_device *drm = panel->base.drm;
 158         struct drm_display_mode *mode;
 159         unsigned int i, num = 0;
 160 
 161         for (i = 0; i < panel->desc->num_modes; i++) {
 162                 const struct drm_display_mode *m = &panel->desc->modes[i];
 163 
 164                 mode = drm_mode_duplicate(drm, m);
 165                 if (!mode) {
 166                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 167                                 m->hdisplay, m->vdisplay, m->vrefresh);
 168                         continue;
 169                 }
 170 
 171                 mode->type |= DRM_MODE_TYPE_DRIVER;
 172 
 173                 if (panel->desc->num_modes == 1)
 174                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 175 
 176                 drm_mode_set_name(mode);
 177 
 178                 drm_mode_probed_add(connector, mode);
 179                 num++;
 180         }
 181 
 182         return num;
 183 }
 184 
 185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel)
 186 {
 187         struct drm_connector *connector = panel->base.connector;
 188         struct drm_device *drm = panel->base.drm;
 189         struct drm_display_mode *mode;
 190         bool has_override = panel->override_mode.type;
 191         unsigned int num = 0;
 192 
 193         if (!panel->desc)
 194                 return 0;
 195 
 196         if (has_override) {
 197                 mode = drm_mode_duplicate(drm, &panel->override_mode);
 198                 if (mode) {
 199                         drm_mode_probed_add(connector, mode);
 200                         num = 1;
 201                 } else {
 202                         dev_err(drm->dev, "failed to add override mode\n");
 203                 }
 204         }
 205 
 206         /* Only add timings if override was not there or failed to validate */
 207         if (num == 0 && panel->desc->num_timings)
 208                 num = panel_simple_get_timings_modes(panel);
 209 
 210         /*
 211          * Only add fixed modes if timings/override added no mode.
 212          *
 213          * We should only ever have either the display timings specified
 214          * or a fixed mode. Anything else is rather bogus.
 215          */
 216         WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
 217         if (num == 0)
 218                 num = panel_simple_get_display_modes(panel);
 219 
 220         connector->display_info.bpc = panel->desc->bpc;
 221         connector->display_info.width_mm = panel->desc->size.width;
 222         connector->display_info.height_mm = panel->desc->size.height;
 223         if (panel->desc->bus_format)
 224                 drm_display_info_set_bus_formats(&connector->display_info,
 225                                                  &panel->desc->bus_format, 1);
 226         connector->display_info.bus_flags = panel->desc->bus_flags;
 227 
 228         return num;
 229 }
 230 
 231 static int panel_simple_disable(struct drm_panel *panel)
 232 {
 233         struct panel_simple *p = to_panel_simple(panel);
 234 
 235         if (!p->enabled)
 236                 return 0;
 237 
 238         if (p->backlight) {
 239                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 240                 p->backlight->props.state |= BL_CORE_FBBLANK;
 241                 backlight_update_status(p->backlight);
 242         }
 243 
 244         if (p->desc->delay.disable)
 245                 msleep(p->desc->delay.disable);
 246 
 247         p->enabled = false;
 248 
 249         return 0;
 250 }
 251 
 252 static int panel_simple_unprepare(struct drm_panel *panel)
 253 {
 254         struct panel_simple *p = to_panel_simple(panel);
 255 
 256         if (!p->prepared)
 257                 return 0;
 258 
 259         gpiod_set_value_cansleep(p->enable_gpio, 0);
 260 
 261         regulator_disable(p->supply);
 262 
 263         if (p->desc->delay.unprepare)
 264                 msleep(p->desc->delay.unprepare);
 265 
 266         p->prepared = false;
 267 
 268         return 0;
 269 }
 270 
 271 static int panel_simple_prepare(struct drm_panel *panel)
 272 {
 273         struct panel_simple *p = to_panel_simple(panel);
 274         unsigned int delay;
 275         int err;
 276 
 277         if (p->prepared)
 278                 return 0;
 279 
 280         err = regulator_enable(p->supply);
 281         if (err < 0) {
 282                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 283                 return err;
 284         }
 285 
 286         gpiod_set_value_cansleep(p->enable_gpio, 1);
 287 
 288         delay = p->desc->delay.prepare;
 289         if (p->no_hpd)
 290                 delay += p->desc->delay.hpd_absent_delay;
 291         if (delay)
 292                 msleep(delay);
 293 
 294         p->prepared = true;
 295 
 296         return 0;
 297 }
 298 
 299 static int panel_simple_enable(struct drm_panel *panel)
 300 {
 301         struct panel_simple *p = to_panel_simple(panel);
 302 
 303         if (p->enabled)
 304                 return 0;
 305 
 306         if (p->desc->delay.enable)
 307                 msleep(p->desc->delay.enable);
 308 
 309         if (p->backlight) {
 310                 p->backlight->props.state &= ~BL_CORE_FBBLANK;
 311                 p->backlight->props.power = FB_BLANK_UNBLANK;
 312                 backlight_update_status(p->backlight);
 313         }
 314 
 315         p->enabled = true;
 316 
 317         return 0;
 318 }
 319 
 320 static int panel_simple_get_modes(struct drm_panel *panel)
 321 {
 322         struct panel_simple *p = to_panel_simple(panel);
 323         int num = 0;
 324 
 325         /* probe EDID if a DDC bus is available */
 326         if (p->ddc) {
 327                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 328                 drm_connector_update_edid_property(panel->connector, edid);
 329                 if (edid) {
 330                         num += drm_add_edid_modes(panel->connector, edid);
 331                         kfree(edid);
 332                 }
 333         }
 334 
 335         /* add hard-coded panel modes */
 336         num += panel_simple_get_non_edid_modes(p);
 337 
 338         return num;
 339 }
 340 
 341 static int panel_simple_get_timings(struct drm_panel *panel,
 342                                     unsigned int num_timings,
 343                                     struct display_timing *timings)
 344 {
 345         struct panel_simple *p = to_panel_simple(panel);
 346         unsigned int i;
 347 
 348         if (p->desc->num_timings < num_timings)
 349                 num_timings = p->desc->num_timings;
 350 
 351         if (timings)
 352                 for (i = 0; i < num_timings; i++)
 353                         timings[i] = p->desc->timings[i];
 354 
 355         return p->desc->num_timings;
 356 }
 357 
 358 static const struct drm_panel_funcs panel_simple_funcs = {
 359         .disable = panel_simple_disable,
 360         .unprepare = panel_simple_unprepare,
 361         .prepare = panel_simple_prepare,
 362         .enable = panel_simple_enable,
 363         .get_modes = panel_simple_get_modes,
 364         .get_timings = panel_simple_get_timings,
 365 };
 366 
 367 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
 368         (to_check->field.typ >= bounds->field.min && \
 369          to_check->field.typ <= bounds->field.max)
 370 static void panel_simple_parse_panel_timing_node(struct device *dev,
 371                                                  struct panel_simple *panel,
 372                                                  const struct display_timing *ot)
 373 {
 374         const struct panel_desc *desc = panel->desc;
 375         struct videomode vm;
 376         unsigned int i;
 377 
 378         if (WARN_ON(desc->num_modes)) {
 379                 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
 380                 return;
 381         }
 382         if (WARN_ON(!desc->num_timings)) {
 383                 dev_err(dev, "Reject override mode: no timings specified\n");
 384                 return;
 385         }
 386 
 387         for (i = 0; i < panel->desc->num_timings; i++) {
 388                 const struct display_timing *dt = &panel->desc->timings[i];
 389 
 390                 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
 391                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
 392                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
 393                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
 394                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
 395                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
 396                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
 397                     !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
 398                         continue;
 399 
 400                 if (ot->flags != dt->flags)
 401                         continue;
 402 
 403                 videomode_from_timing(ot, &vm);
 404                 drm_display_mode_from_videomode(&vm, &panel->override_mode);
 405                 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
 406                                              DRM_MODE_TYPE_PREFERRED;
 407                 break;
 408         }
 409 
 410         if (WARN_ON(!panel->override_mode.type))
 411                 dev_err(dev, "Reject override mode: No display_timing found\n");
 412 }
 413 
 414 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 415 {
 416         struct device_node *backlight, *ddc;
 417         struct panel_simple *panel;
 418         struct display_timing dt;
 419         int err;
 420 
 421         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 422         if (!panel)
 423                 return -ENOMEM;
 424 
 425         panel->enabled = false;
 426         panel->prepared = false;
 427         panel->desc = desc;
 428 
 429         panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
 430 
 431         panel->supply = devm_regulator_get(dev, "power");
 432         if (IS_ERR(panel->supply))
 433                 return PTR_ERR(panel->supply);
 434 
 435         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
 436                                                      GPIOD_OUT_LOW);
 437         if (IS_ERR(panel->enable_gpio)) {
 438                 err = PTR_ERR(panel->enable_gpio);
 439                 if (err != -EPROBE_DEFER)
 440                         dev_err(dev, "failed to request GPIO: %d\n", err);
 441                 return err;
 442         }
 443 
 444         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 445         if (backlight) {
 446                 panel->backlight = of_find_backlight_by_node(backlight);
 447                 of_node_put(backlight);
 448 
 449                 if (!panel->backlight)
 450                         return -EPROBE_DEFER;
 451         }
 452 
 453         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 454         if (ddc) {
 455                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 456                 of_node_put(ddc);
 457 
 458                 if (!panel->ddc) {
 459                         err = -EPROBE_DEFER;
 460                         goto free_backlight;
 461                 }
 462         }
 463 
 464         if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
 465                 panel_simple_parse_panel_timing_node(dev, panel, &dt);
 466 
 467         drm_panel_init(&panel->base);
 468         panel->base.dev = dev;
 469         panel->base.funcs = &panel_simple_funcs;
 470 
 471         err = drm_panel_add(&panel->base);
 472         if (err < 0)
 473                 goto free_ddc;
 474 
 475         dev_set_drvdata(dev, panel);
 476 
 477         return 0;
 478 
 479 free_ddc:
 480         if (panel->ddc)
 481                 put_device(&panel->ddc->dev);
 482 free_backlight:
 483         if (panel->backlight)
 484                 put_device(&panel->backlight->dev);
 485 
 486         return err;
 487 }
 488 
 489 static int panel_simple_remove(struct device *dev)
 490 {
 491         struct panel_simple *panel = dev_get_drvdata(dev);
 492 
 493         drm_panel_remove(&panel->base);
 494 
 495         panel_simple_disable(&panel->base);
 496         panel_simple_unprepare(&panel->base);
 497 
 498         if (panel->ddc)
 499                 put_device(&panel->ddc->dev);
 500 
 501         if (panel->backlight)
 502                 put_device(&panel->backlight->dev);
 503 
 504         return 0;
 505 }
 506 
 507 static void panel_simple_shutdown(struct device *dev)
 508 {
 509         struct panel_simple *panel = dev_get_drvdata(dev);
 510 
 511         panel_simple_disable(&panel->base);
 512         panel_simple_unprepare(&panel->base);
 513 }
 514 
 515 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
 516         .clock = 9000,
 517         .hdisplay = 480,
 518         .hsync_start = 480 + 2,
 519         .hsync_end = 480 + 2 + 41,
 520         .htotal = 480 + 2 + 41 + 2,
 521         .vdisplay = 272,
 522         .vsync_start = 272 + 2,
 523         .vsync_end = 272 + 2 + 10,
 524         .vtotal = 272 + 2 + 10 + 2,
 525         .vrefresh = 60,
 526         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 527 };
 528 
 529 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
 530         .modes = &ampire_am_480272h3tmqw_t01h_mode,
 531         .num_modes = 1,
 532         .bpc = 8,
 533         .size = {
 534                 .width = 105,
 535                 .height = 67,
 536         },
 537         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
 538 };
 539 
 540 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 541         .clock = 33333,
 542         .hdisplay = 800,
 543         .hsync_start = 800 + 0,
 544         .hsync_end = 800 + 0 + 255,
 545         .htotal = 800 + 0 + 255 + 0,
 546         .vdisplay = 480,
 547         .vsync_start = 480 + 2,
 548         .vsync_end = 480 + 2 + 45,
 549         .vtotal = 480 + 2 + 45 + 0,
 550         .vrefresh = 60,
 551         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 552 };
 553 
 554 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 555         .modes = &ampire_am800480r3tmqwa1h_mode,
 556         .num_modes = 1,
 557         .bpc = 6,
 558         .size = {
 559                 .width = 152,
 560                 .height = 91,
 561         },
 562         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 563 };
 564 
 565 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
 566         .pixelclock = { 26400000, 33300000, 46800000 },
 567         .hactive = { 800, 800, 800 },
 568         .hfront_porch = { 16, 210, 354 },
 569         .hback_porch = { 45, 36, 6 },
 570         .hsync_len = { 1, 10, 40 },
 571         .vactive = { 480, 480, 480 },
 572         .vfront_porch = { 7, 22, 147 },
 573         .vback_porch = { 22, 13, 3 },
 574         .vsync_len = { 1, 10, 20 },
 575         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
 576                 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
 577 };
 578 
 579 static const struct panel_desc armadeus_st0700_adapt = {
 580         .timings = &santek_st0700i5y_rbslw_f_timing,
 581         .num_timings = 1,
 582         .bpc = 6,
 583         .size = {
 584                 .width = 154,
 585                 .height = 86,
 586         },
 587         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 588         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
 589 };
 590 
 591 static const struct drm_display_mode auo_b101aw03_mode = {
 592         .clock = 51450,
 593         .hdisplay = 1024,
 594         .hsync_start = 1024 + 156,
 595         .hsync_end = 1024 + 156 + 8,
 596         .htotal = 1024 + 156 + 8 + 156,
 597         .vdisplay = 600,
 598         .vsync_start = 600 + 16,
 599         .vsync_end = 600 + 16 + 6,
 600         .vtotal = 600 + 16 + 6 + 16,
 601         .vrefresh = 60,
 602 };
 603 
 604 static const struct panel_desc auo_b101aw03 = {
 605         .modes = &auo_b101aw03_mode,
 606         .num_modes = 1,
 607         .bpc = 6,
 608         .size = {
 609                 .width = 223,
 610                 .height = 125,
 611         },
 612 };
 613 
 614 static const struct display_timing auo_b101ean01_timing = {
 615         .pixelclock = { 65300000, 72500000, 75000000 },
 616         .hactive = { 1280, 1280, 1280 },
 617         .hfront_porch = { 18, 119, 119 },
 618         .hback_porch = { 21, 21, 21 },
 619         .hsync_len = { 32, 32, 32 },
 620         .vactive = { 800, 800, 800 },
 621         .vfront_porch = { 4, 4, 4 },
 622         .vback_porch = { 8, 8, 8 },
 623         .vsync_len = { 18, 20, 20 },
 624 };
 625 
 626 static const struct panel_desc auo_b101ean01 = {
 627         .timings = &auo_b101ean01_timing,
 628         .num_timings = 1,
 629         .bpc = 6,
 630         .size = {
 631                 .width = 217,
 632                 .height = 136,
 633         },
 634 };
 635 
 636 static const struct drm_display_mode auo_b101xtn01_mode = {
 637         .clock = 72000,
 638         .hdisplay = 1366,
 639         .hsync_start = 1366 + 20,
 640         .hsync_end = 1366 + 20 + 70,
 641         .htotal = 1366 + 20 + 70,
 642         .vdisplay = 768,
 643         .vsync_start = 768 + 14,
 644         .vsync_end = 768 + 14 + 42,
 645         .vtotal = 768 + 14 + 42,
 646         .vrefresh = 60,
 647         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 648 };
 649 
 650 static const struct panel_desc auo_b101xtn01 = {
 651         .modes = &auo_b101xtn01_mode,
 652         .num_modes = 1,
 653         .bpc = 6,
 654         .size = {
 655                 .width = 223,
 656                 .height = 125,
 657         },
 658 };
 659 
 660 static const struct drm_display_mode auo_b116xw03_mode = {
 661         .clock = 70589,
 662         .hdisplay = 1366,
 663         .hsync_start = 1366 + 40,
 664         .hsync_end = 1366 + 40 + 40,
 665         .htotal = 1366 + 40 + 40 + 32,
 666         .vdisplay = 768,
 667         .vsync_start = 768 + 10,
 668         .vsync_end = 768 + 10 + 12,
 669         .vtotal = 768 + 10 + 12 + 6,
 670         .vrefresh = 60,
 671 };
 672 
 673 static const struct panel_desc auo_b116xw03 = {
 674         .modes = &auo_b116xw03_mode,
 675         .num_modes = 1,
 676         .bpc = 6,
 677         .size = {
 678                 .width = 256,
 679                 .height = 144,
 680         },
 681 };
 682 
 683 static const struct drm_display_mode auo_b133xtn01_mode = {
 684         .clock = 69500,
 685         .hdisplay = 1366,
 686         .hsync_start = 1366 + 48,
 687         .hsync_end = 1366 + 48 + 32,
 688         .htotal = 1366 + 48 + 32 + 20,
 689         .vdisplay = 768,
 690         .vsync_start = 768 + 3,
 691         .vsync_end = 768 + 3 + 6,
 692         .vtotal = 768 + 3 + 6 + 13,
 693         .vrefresh = 60,
 694 };
 695 
 696 static const struct panel_desc auo_b133xtn01 = {
 697         .modes = &auo_b133xtn01_mode,
 698         .num_modes = 1,
 699         .bpc = 6,
 700         .size = {
 701                 .width = 293,
 702                 .height = 165,
 703         },
 704 };
 705 
 706 static const struct drm_display_mode auo_b133htn01_mode = {
 707         .clock = 150660,
 708         .hdisplay = 1920,
 709         .hsync_start = 1920 + 172,
 710         .hsync_end = 1920 + 172 + 80,
 711         .htotal = 1920 + 172 + 80 + 60,
 712         .vdisplay = 1080,
 713         .vsync_start = 1080 + 25,
 714         .vsync_end = 1080 + 25 + 10,
 715         .vtotal = 1080 + 25 + 10 + 10,
 716         .vrefresh = 60,
 717 };
 718 
 719 static const struct panel_desc auo_b133htn01 = {
 720         .modes = &auo_b133htn01_mode,
 721         .num_modes = 1,
 722         .bpc = 6,
 723         .size = {
 724                 .width = 293,
 725                 .height = 165,
 726         },
 727         .delay = {
 728                 .prepare = 105,
 729                 .enable = 20,
 730                 .unprepare = 50,
 731         },
 732 };
 733 
 734 static const struct display_timing auo_g070vvn01_timings = {
 735         .pixelclock = { 33300000, 34209000, 45000000 },
 736         .hactive = { 800, 800, 800 },
 737         .hfront_porch = { 20, 40, 200 },
 738         .hback_porch = { 87, 40, 1 },
 739         .hsync_len = { 1, 48, 87 },
 740         .vactive = { 480, 480, 480 },
 741         .vfront_porch = { 5, 13, 200 },
 742         .vback_porch = { 31, 31, 29 },
 743         .vsync_len = { 1, 1, 3 },
 744 };
 745 
 746 static const struct panel_desc auo_g070vvn01 = {
 747         .timings = &auo_g070vvn01_timings,
 748         .num_timings = 1,
 749         .bpc = 8,
 750         .size = {
 751                 .width = 152,
 752                 .height = 91,
 753         },
 754         .delay = {
 755                 .prepare = 200,
 756                 .enable = 50,
 757                 .disable = 50,
 758                 .unprepare = 1000,
 759         },
 760 };
 761 
 762 static const struct drm_display_mode auo_g101evn010_mode = {
 763         .clock = 68930,
 764         .hdisplay = 1280,
 765         .hsync_start = 1280 + 82,
 766         .hsync_end = 1280 + 82 + 2,
 767         .htotal = 1280 + 82 + 2 + 84,
 768         .vdisplay = 800,
 769         .vsync_start = 800 + 8,
 770         .vsync_end = 800 + 8 + 2,
 771         .vtotal = 800 + 8 + 2 + 6,
 772         .vrefresh = 60,
 773 };
 774 
 775 static const struct panel_desc auo_g101evn010 = {
 776         .modes = &auo_g101evn010_mode,
 777         .num_modes = 1,
 778         .bpc = 6,
 779         .size = {
 780                 .width = 216,
 781                 .height = 135,
 782         },
 783         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 784 };
 785 
 786 static const struct drm_display_mode auo_g104sn02_mode = {
 787         .clock = 40000,
 788         .hdisplay = 800,
 789         .hsync_start = 800 + 40,
 790         .hsync_end = 800 + 40 + 216,
 791         .htotal = 800 + 40 + 216 + 128,
 792         .vdisplay = 600,
 793         .vsync_start = 600 + 10,
 794         .vsync_end = 600 + 10 + 35,
 795         .vtotal = 600 + 10 + 35 + 2,
 796         .vrefresh = 60,
 797 };
 798 
 799 static const struct panel_desc auo_g104sn02 = {
 800         .modes = &auo_g104sn02_mode,
 801         .num_modes = 1,
 802         .bpc = 8,
 803         .size = {
 804                 .width = 211,
 805                 .height = 158,
 806         },
 807 };
 808 
 809 static const struct display_timing auo_g133han01_timings = {
 810         .pixelclock = { 134000000, 141200000, 149000000 },
 811         .hactive = { 1920, 1920, 1920 },
 812         .hfront_porch = { 39, 58, 77 },
 813         .hback_porch = { 59, 88, 117 },
 814         .hsync_len = { 28, 42, 56 },
 815         .vactive = { 1080, 1080, 1080 },
 816         .vfront_porch = { 3, 8, 11 },
 817         .vback_porch = { 5, 14, 19 },
 818         .vsync_len = { 4, 14, 19 },
 819 };
 820 
 821 static const struct panel_desc auo_g133han01 = {
 822         .timings = &auo_g133han01_timings,
 823         .num_timings = 1,
 824         .bpc = 8,
 825         .size = {
 826                 .width = 293,
 827                 .height = 165,
 828         },
 829         .delay = {
 830                 .prepare = 200,
 831                 .enable = 50,
 832                 .disable = 50,
 833                 .unprepare = 1000,
 834         },
 835         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 836 };
 837 
 838 static const struct display_timing auo_g185han01_timings = {
 839         .pixelclock = { 120000000, 144000000, 175000000 },
 840         .hactive = { 1920, 1920, 1920 },
 841         .hfront_porch = { 36, 120, 148 },
 842         .hback_porch = { 24, 88, 108 },
 843         .hsync_len = { 20, 48, 64 },
 844         .vactive = { 1080, 1080, 1080 },
 845         .vfront_porch = { 6, 10, 40 },
 846         .vback_porch = { 2, 5, 20 },
 847         .vsync_len = { 2, 5, 20 },
 848 };
 849 
 850 static const struct panel_desc auo_g185han01 = {
 851         .timings = &auo_g185han01_timings,
 852         .num_timings = 1,
 853         .bpc = 8,
 854         .size = {
 855                 .width = 409,
 856                 .height = 230,
 857         },
 858         .delay = {
 859                 .prepare = 50,
 860                 .enable = 200,
 861                 .disable = 110,
 862                 .unprepare = 1000,
 863         },
 864         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 865 };
 866 
 867 static const struct display_timing auo_p320hvn03_timings = {
 868         .pixelclock = { 106000000, 148500000, 164000000 },
 869         .hactive = { 1920, 1920, 1920 },
 870         .hfront_porch = { 25, 50, 130 },
 871         .hback_porch = { 25, 50, 130 },
 872         .hsync_len = { 20, 40, 105 },
 873         .vactive = { 1080, 1080, 1080 },
 874         .vfront_porch = { 8, 17, 150 },
 875         .vback_porch = { 8, 17, 150 },
 876         .vsync_len = { 4, 11, 100 },
 877 };
 878 
 879 static const struct panel_desc auo_p320hvn03 = {
 880         .timings = &auo_p320hvn03_timings,
 881         .num_timings = 1,
 882         .bpc = 8,
 883         .size = {
 884                 .width = 698,
 885                 .height = 393,
 886         },
 887         .delay = {
 888                 .prepare = 1,
 889                 .enable = 450,
 890                 .unprepare = 500,
 891         },
 892         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
 893 };
 894 
 895 static const struct drm_display_mode auo_t215hvn01_mode = {
 896         .clock = 148800,
 897         .hdisplay = 1920,
 898         .hsync_start = 1920 + 88,
 899         .hsync_end = 1920 + 88 + 44,
 900         .htotal = 1920 + 88 + 44 + 148,
 901         .vdisplay = 1080,
 902         .vsync_start = 1080 + 4,
 903         .vsync_end = 1080 + 4 + 5,
 904         .vtotal = 1080 + 4 + 5 + 36,
 905         .vrefresh = 60,
 906 };
 907 
 908 static const struct panel_desc auo_t215hvn01 = {
 909         .modes = &auo_t215hvn01_mode,
 910         .num_modes = 1,
 911         .bpc = 8,
 912         .size = {
 913                 .width = 430,
 914                 .height = 270,
 915         },
 916         .delay = {
 917                 .disable = 5,
 918                 .unprepare = 1000,
 919         }
 920 };
 921 
 922 static const struct drm_display_mode avic_tm070ddh03_mode = {
 923         .clock = 51200,
 924         .hdisplay = 1024,
 925         .hsync_start = 1024 + 160,
 926         .hsync_end = 1024 + 160 + 4,
 927         .htotal = 1024 + 160 + 4 + 156,
 928         .vdisplay = 600,
 929         .vsync_start = 600 + 17,
 930         .vsync_end = 600 + 17 + 1,
 931         .vtotal = 600 + 17 + 1 + 17,
 932         .vrefresh = 60,
 933 };
 934 
 935 static const struct panel_desc avic_tm070ddh03 = {
 936         .modes = &avic_tm070ddh03_mode,
 937         .num_modes = 1,
 938         .bpc = 8,
 939         .size = {
 940                 .width = 154,
 941                 .height = 90,
 942         },
 943         .delay = {
 944                 .prepare = 20,
 945                 .enable = 200,
 946                 .disable = 200,
 947         },
 948 };
 949 
 950 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
 951         .clock = 30000,
 952         .hdisplay = 800,
 953         .hsync_start = 800 + 40,
 954         .hsync_end = 800 + 40 + 48,
 955         .htotal = 800 + 40 + 48 + 40,
 956         .vdisplay = 480,
 957         .vsync_start = 480 + 13,
 958         .vsync_end = 480 + 13 + 3,
 959         .vtotal = 480 + 13 + 3 + 29,
 960 };
 961 
 962 static const struct panel_desc bananapi_s070wv20_ct16 = {
 963         .modes = &bananapi_s070wv20_ct16_mode,
 964         .num_modes = 1,
 965         .bpc = 6,
 966         .size = {
 967                 .width = 154,
 968                 .height = 86,
 969         },
 970 };
 971 
 972 static const struct drm_display_mode boe_hv070wsa_mode = {
 973         .clock = 42105,
 974         .hdisplay = 1024,
 975         .hsync_start = 1024 + 30,
 976         .hsync_end = 1024 + 30 + 30,
 977         .htotal = 1024 + 30 + 30 + 30,
 978         .vdisplay = 600,
 979         .vsync_start = 600 + 10,
 980         .vsync_end = 600 + 10 + 10,
 981         .vtotal = 600 + 10 + 10 + 10,
 982         .vrefresh = 60,
 983 };
 984 
 985 static const struct panel_desc boe_hv070wsa = {
 986         .modes = &boe_hv070wsa_mode,
 987         .num_modes = 1,
 988         .size = {
 989                 .width = 154,
 990                 .height = 90,
 991         },
 992 };
 993 
 994 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
 995         {
 996                 .clock = 71900,
 997                 .hdisplay = 1280,
 998                 .hsync_start = 1280 + 48,
 999                 .hsync_end = 1280 + 48 + 32,
1000                 .htotal = 1280 + 48 + 32 + 80,
1001                 .vdisplay = 800,
1002                 .vsync_start = 800 + 3,
1003                 .vsync_end = 800 + 3 + 5,
1004                 .vtotal = 800 + 3 + 5 + 24,
1005                 .vrefresh = 60,
1006         },
1007         {
1008                 .clock = 57500,
1009                 .hdisplay = 1280,
1010                 .hsync_start = 1280 + 48,
1011                 .hsync_end = 1280 + 48 + 32,
1012                 .htotal = 1280 + 48 + 32 + 80,
1013                 .vdisplay = 800,
1014                 .vsync_start = 800 + 3,
1015                 .vsync_end = 800 + 3 + 5,
1016                 .vtotal = 800 + 3 + 5 + 24,
1017                 .vrefresh = 48,
1018         },
1019 };
1020 
1021 static const struct panel_desc boe_nv101wxmn51 = {
1022         .modes = boe_nv101wxmn51_modes,
1023         .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1024         .bpc = 8,
1025         .size = {
1026                 .width = 217,
1027                 .height = 136,
1028         },
1029         .delay = {
1030                 .prepare = 210,
1031                 .enable = 50,
1032                 .unprepare = 160,
1033         },
1034 };
1035 
1036 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1037         .clock = 9000,
1038         .hdisplay = 480,
1039         .hsync_start = 480 + 5,
1040         .hsync_end = 480 + 5 + 5,
1041         .htotal = 480 + 5 + 5 + 40,
1042         .vdisplay = 272,
1043         .vsync_start = 272 + 8,
1044         .vsync_end = 272 + 8 + 8,
1045         .vtotal = 272 + 8 + 8 + 8,
1046         .vrefresh = 60,
1047         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1048 };
1049 
1050 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1051         .modes = &cdtech_s043wq26h_ct7_mode,
1052         .num_modes = 1,
1053         .bpc = 8,
1054         .size = {
1055                 .width = 95,
1056                 .height = 54,
1057         },
1058         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1059 };
1060 
1061 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1062         .clock = 35000,
1063         .hdisplay = 800,
1064         .hsync_start = 800 + 40,
1065         .hsync_end = 800 + 40 + 40,
1066         .htotal = 800 + 40 + 40 + 48,
1067         .vdisplay = 480,
1068         .vsync_start = 480 + 29,
1069         .vsync_end = 480 + 29 + 13,
1070         .vtotal = 480 + 29 + 13 + 3,
1071         .vrefresh = 60,
1072         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1073 };
1074 
1075 static const struct panel_desc cdtech_s070wv95_ct16 = {
1076         .modes = &cdtech_s070wv95_ct16_mode,
1077         .num_modes = 1,
1078         .bpc = 8,
1079         .size = {
1080                 .width = 154,
1081                 .height = 85,
1082         },
1083 };
1084 
1085 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1086         .clock = 66770,
1087         .hdisplay = 800,
1088         .hsync_start = 800 + 49,
1089         .hsync_end = 800 + 49 + 33,
1090         .htotal = 800 + 49 + 33 + 17,
1091         .vdisplay = 1280,
1092         .vsync_start = 1280 + 1,
1093         .vsync_end = 1280 + 1 + 7,
1094         .vtotal = 1280 + 1 + 7 + 15,
1095         .vrefresh = 60,
1096         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1097 };
1098 
1099 static const struct panel_desc chunghwa_claa070wp03xg = {
1100         .modes = &chunghwa_claa070wp03xg_mode,
1101         .num_modes = 1,
1102         .bpc = 6,
1103         .size = {
1104                 .width = 94,
1105                 .height = 150,
1106         },
1107 };
1108 
1109 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1110         .clock = 72070,
1111         .hdisplay = 1366,
1112         .hsync_start = 1366 + 58,
1113         .hsync_end = 1366 + 58 + 58,
1114         .htotal = 1366 + 58 + 58 + 58,
1115         .vdisplay = 768,
1116         .vsync_start = 768 + 4,
1117         .vsync_end = 768 + 4 + 4,
1118         .vtotal = 768 + 4 + 4 + 4,
1119         .vrefresh = 60,
1120 };
1121 
1122 static const struct panel_desc chunghwa_claa101wa01a = {
1123         .modes = &chunghwa_claa101wa01a_mode,
1124         .num_modes = 1,
1125         .bpc = 6,
1126         .size = {
1127                 .width = 220,
1128                 .height = 120,
1129         },
1130 };
1131 
1132 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1133         .clock = 69300,
1134         .hdisplay = 1366,
1135         .hsync_start = 1366 + 48,
1136         .hsync_end = 1366 + 48 + 32,
1137         .htotal = 1366 + 48 + 32 + 20,
1138         .vdisplay = 768,
1139         .vsync_start = 768 + 16,
1140         .vsync_end = 768 + 16 + 8,
1141         .vtotal = 768 + 16 + 8 + 16,
1142         .vrefresh = 60,
1143 };
1144 
1145 static const struct panel_desc chunghwa_claa101wb01 = {
1146         .modes = &chunghwa_claa101wb01_mode,
1147         .num_modes = 1,
1148         .bpc = 6,
1149         .size = {
1150                 .width = 223,
1151                 .height = 125,
1152         },
1153 };
1154 
1155 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1156         .clock = 33260,
1157         .hdisplay = 800,
1158         .hsync_start = 800 + 40,
1159         .hsync_end = 800 + 40 + 128,
1160         .htotal = 800 + 40 + 128 + 88,
1161         .vdisplay = 480,
1162         .vsync_start = 480 + 10,
1163         .vsync_end = 480 + 10 + 2,
1164         .vtotal = 480 + 10 + 2 + 33,
1165         .vrefresh = 60,
1166         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1167 };
1168 
1169 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1170         .modes = &dataimage_scf0700c48ggu18_mode,
1171         .num_modes = 1,
1172         .bpc = 8,
1173         .size = {
1174                 .width = 152,
1175                 .height = 91,
1176         },
1177         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1178         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1179 };
1180 
1181 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1182         .pixelclock = { 45000000, 51200000, 57000000 },
1183         .hactive = { 1024, 1024, 1024 },
1184         .hfront_porch = { 100, 106, 113 },
1185         .hback_porch = { 100, 106, 113 },
1186         .hsync_len = { 100, 108, 114 },
1187         .vactive = { 600, 600, 600 },
1188         .vfront_porch = { 8, 11, 15 },
1189         .vback_porch = { 8, 11, 15 },
1190         .vsync_len = { 9, 13, 15 },
1191         .flags = DISPLAY_FLAGS_DE_HIGH,
1192 };
1193 
1194 static const struct panel_desc dlc_dlc0700yzg_1 = {
1195         .timings = &dlc_dlc0700yzg_1_timing,
1196         .num_timings = 1,
1197         .bpc = 6,
1198         .size = {
1199                 .width = 154,
1200                 .height = 86,
1201         },
1202         .delay = {
1203                 .prepare = 30,
1204                 .enable = 200,
1205                 .disable = 200,
1206         },
1207         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1208 };
1209 
1210 static const struct display_timing dlc_dlc1010gig_timing = {
1211         .pixelclock = { 68900000, 71100000, 73400000 },
1212         .hactive = { 1280, 1280, 1280 },
1213         .hfront_porch = { 43, 53, 63 },
1214         .hback_porch = { 43, 53, 63 },
1215         .hsync_len = { 44, 54, 64 },
1216         .vactive = { 800, 800, 800 },
1217         .vfront_porch = { 5, 8, 11 },
1218         .vback_porch = { 5, 8, 11 },
1219         .vsync_len = { 5, 7, 11 },
1220         .flags = DISPLAY_FLAGS_DE_HIGH,
1221 };
1222 
1223 static const struct panel_desc dlc_dlc1010gig = {
1224         .timings = &dlc_dlc1010gig_timing,
1225         .num_timings = 1,
1226         .bpc = 8,
1227         .size = {
1228                 .width = 216,
1229                 .height = 135,
1230         },
1231         .delay = {
1232                 .prepare = 60,
1233                 .enable = 150,
1234                 .disable = 100,
1235                 .unprepare = 60,
1236         },
1237         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238 };
1239 
1240 static const struct drm_display_mode edt_et035012dm6_mode = {
1241         .clock = 6500,
1242         .hdisplay = 320,
1243         .hsync_start = 320 + 20,
1244         .hsync_end = 320 + 20 + 30,
1245         .htotal = 320 + 20 + 68,
1246         .vdisplay = 240,
1247         .vsync_start = 240 + 4,
1248         .vsync_end = 240 + 4 + 4,
1249         .vtotal = 240 + 4 + 4 + 14,
1250         .vrefresh = 60,
1251         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1252 };
1253 
1254 static const struct panel_desc edt_et035012dm6 = {
1255         .modes = &edt_et035012dm6_mode,
1256         .num_modes = 1,
1257         .bpc = 8,
1258         .size = {
1259                 .width = 70,
1260                 .height = 52,
1261         },
1262         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1263         .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1264 };
1265 
1266 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1267         .clock = 9000,
1268         .hdisplay = 480,
1269         .hsync_start = 480 + 2,
1270         .hsync_end = 480 + 2 + 41,
1271         .htotal = 480 + 2 + 41 + 2,
1272         .vdisplay = 272,
1273         .vsync_start = 272 + 2,
1274         .vsync_end = 272 + 2 + 10,
1275         .vtotal = 272 + 2 + 10 + 2,
1276         .vrefresh = 60,
1277         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1278 };
1279 
1280 static const struct panel_desc edt_etm0430g0dh6 = {
1281         .modes = &edt_etm0430g0dh6_mode,
1282         .num_modes = 1,
1283         .bpc = 6,
1284         .size = {
1285                 .width = 95,
1286                 .height = 54,
1287         },
1288 };
1289 
1290 static const struct drm_display_mode edt_et057090dhu_mode = {
1291         .clock = 25175,
1292         .hdisplay = 640,
1293         .hsync_start = 640 + 16,
1294         .hsync_end = 640 + 16 + 30,
1295         .htotal = 640 + 16 + 30 + 114,
1296         .vdisplay = 480,
1297         .vsync_start = 480 + 10,
1298         .vsync_end = 480 + 10 + 3,
1299         .vtotal = 480 + 10 + 3 + 32,
1300         .vrefresh = 60,
1301         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1302 };
1303 
1304 static const struct panel_desc edt_et057090dhu = {
1305         .modes = &edt_et057090dhu_mode,
1306         .num_modes = 1,
1307         .bpc = 6,
1308         .size = {
1309                 .width = 115,
1310                 .height = 86,
1311         },
1312         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1313         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1314 };
1315 
1316 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1317         .clock = 33260,
1318         .hdisplay = 800,
1319         .hsync_start = 800 + 40,
1320         .hsync_end = 800 + 40 + 128,
1321         .htotal = 800 + 40 + 128 + 88,
1322         .vdisplay = 480,
1323         .vsync_start = 480 + 10,
1324         .vsync_end = 480 + 10 + 2,
1325         .vtotal = 480 + 10 + 2 + 33,
1326         .vrefresh = 60,
1327         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1328 };
1329 
1330 static const struct panel_desc edt_etm0700g0dh6 = {
1331         .modes = &edt_etm0700g0dh6_mode,
1332         .num_modes = 1,
1333         .bpc = 6,
1334         .size = {
1335                 .width = 152,
1336                 .height = 91,
1337         },
1338         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1339         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1340 };
1341 
1342 static const struct panel_desc edt_etm0700g0bdh6 = {
1343         .modes = &edt_etm0700g0dh6_mode,
1344         .num_modes = 1,
1345         .bpc = 6,
1346         .size = {
1347                 .width = 152,
1348                 .height = 91,
1349         },
1350         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1351         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1352 };
1353 
1354 static const struct display_timing evervision_vgg804821_timing = {
1355         .pixelclock = { 27600000, 33300000, 50000000 },
1356         .hactive = { 800, 800, 800 },
1357         .hfront_porch = { 40, 66, 70 },
1358         .hback_porch = { 40, 67, 70 },
1359         .hsync_len = { 40, 67, 70 },
1360         .vactive = { 480, 480, 480 },
1361         .vfront_porch = { 6, 10, 10 },
1362         .vback_porch = { 7, 11, 11 },
1363         .vsync_len = { 7, 11, 11 },
1364         .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1365                  DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1366                  DISPLAY_FLAGS_SYNC_NEGEDGE,
1367 };
1368 
1369 static const struct panel_desc evervision_vgg804821 = {
1370         .timings = &evervision_vgg804821_timing,
1371         .num_timings = 1,
1372         .bpc = 8,
1373         .size = {
1374                 .width = 108,
1375                 .height = 64,
1376         },
1377         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1378         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1379 };
1380 
1381 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1382         .clock = 32260,
1383         .hdisplay = 800,
1384         .hsync_start = 800 + 168,
1385         .hsync_end = 800 + 168 + 64,
1386         .htotal = 800 + 168 + 64 + 88,
1387         .vdisplay = 480,
1388         .vsync_start = 480 + 37,
1389         .vsync_end = 480 + 37 + 2,
1390         .vtotal = 480 + 37 + 2 + 8,
1391         .vrefresh = 60,
1392 };
1393 
1394 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1395         .modes = &foxlink_fl500wvr00_a0t_mode,
1396         .num_modes = 1,
1397         .bpc = 8,
1398         .size = {
1399                 .width = 108,
1400                 .height = 65,
1401         },
1402         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1403 };
1404 
1405 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1406         .clock          = 67185,
1407         .hdisplay       = 800,
1408         .hsync_start    = 800 + 20,
1409         .hsync_end      = 800 + 20 + 24,
1410         .htotal         = 800 + 20 + 24 + 20,
1411         .vdisplay       = 1280,
1412         .vsync_start    = 1280 + 4,
1413         .vsync_end      = 1280 + 4 + 8,
1414         .vtotal         = 1280 + 4 + 8 + 4,
1415         .vrefresh       = 60,
1416         .flags          = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1417 };
1418 
1419 static const struct panel_desc friendlyarm_hd702e = {
1420         .modes = &friendlyarm_hd702e_mode,
1421         .num_modes = 1,
1422         .size = {
1423                 .width  = 94,
1424                 .height = 151,
1425         },
1426 };
1427 
1428 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1429         .clock = 9000,
1430         .hdisplay = 480,
1431         .hsync_start = 480 + 5,
1432         .hsync_end = 480 + 5 + 1,
1433         .htotal = 480 + 5 + 1 + 40,
1434         .vdisplay = 272,
1435         .vsync_start = 272 + 8,
1436         .vsync_end = 272 + 8 + 1,
1437         .vtotal = 272 + 8 + 1 + 8,
1438         .vrefresh = 60,
1439 };
1440 
1441 static const struct panel_desc giantplus_gpg482739qs5 = {
1442         .modes = &giantplus_gpg482739qs5_mode,
1443         .num_modes = 1,
1444         .bpc = 8,
1445         .size = {
1446                 .width = 95,
1447                 .height = 54,
1448         },
1449         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1450 };
1451 
1452 static const struct display_timing giantplus_gpm940b0_timing = {
1453         .pixelclock = { 13500000, 27000000, 27500000 },
1454         .hactive = { 320, 320, 320 },
1455         .hfront_porch = { 14, 686, 718 },
1456         .hback_porch = { 50, 70, 255 },
1457         .hsync_len = { 1, 1, 1 },
1458         .vactive = { 240, 240, 240 },
1459         .vfront_porch = { 1, 1, 179 },
1460         .vback_porch = { 1, 21, 31 },
1461         .vsync_len = { 1, 1, 6 },
1462         .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1463 };
1464 
1465 static const struct panel_desc giantplus_gpm940b0 = {
1466         .timings = &giantplus_gpm940b0_timing,
1467         .num_timings = 1,
1468         .bpc = 8,
1469         .size = {
1470                 .width = 60,
1471                 .height = 45,
1472         },
1473         .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1474         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1475 };
1476 
1477 static const struct display_timing hannstar_hsd070pww1_timing = {
1478         .pixelclock = { 64300000, 71100000, 82000000 },
1479         .hactive = { 1280, 1280, 1280 },
1480         .hfront_porch = { 1, 1, 10 },
1481         .hback_porch = { 1, 1, 10 },
1482         /*
1483          * According to the data sheet, the minimum horizontal blanking interval
1484          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1485          * minimum working horizontal blanking interval to be 60 clocks.
1486          */
1487         .hsync_len = { 58, 158, 661 },
1488         .vactive = { 800, 800, 800 },
1489         .vfront_porch = { 1, 1, 10 },
1490         .vback_porch = { 1, 1, 10 },
1491         .vsync_len = { 1, 21, 203 },
1492         .flags = DISPLAY_FLAGS_DE_HIGH,
1493 };
1494 
1495 static const struct panel_desc hannstar_hsd070pww1 = {
1496         .timings = &hannstar_hsd070pww1_timing,
1497         .num_timings = 1,
1498         .bpc = 6,
1499         .size = {
1500                 .width = 151,
1501                 .height = 94,
1502         },
1503         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1504 };
1505 
1506 static const struct display_timing hannstar_hsd100pxn1_timing = {
1507         .pixelclock = { 55000000, 65000000, 75000000 },
1508         .hactive = { 1024, 1024, 1024 },
1509         .hfront_porch = { 40, 40, 40 },
1510         .hback_porch = { 220, 220, 220 },
1511         .hsync_len = { 20, 60, 100 },
1512         .vactive = { 768, 768, 768 },
1513         .vfront_porch = { 7, 7, 7 },
1514         .vback_porch = { 21, 21, 21 },
1515         .vsync_len = { 10, 10, 10 },
1516         .flags = DISPLAY_FLAGS_DE_HIGH,
1517 };
1518 
1519 static const struct panel_desc hannstar_hsd100pxn1 = {
1520         .timings = &hannstar_hsd100pxn1_timing,
1521         .num_timings = 1,
1522         .bpc = 6,
1523         .size = {
1524                 .width = 203,
1525                 .height = 152,
1526         },
1527         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1528 };
1529 
1530 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1531         .clock = 33333,
1532         .hdisplay = 800,
1533         .hsync_start = 800 + 85,
1534         .hsync_end = 800 + 85 + 86,
1535         .htotal = 800 + 85 + 86 + 85,
1536         .vdisplay = 480,
1537         .vsync_start = 480 + 16,
1538         .vsync_end = 480 + 16 + 13,
1539         .vtotal = 480 + 16 + 13 + 16,
1540         .vrefresh = 60,
1541 };
1542 
1543 static const struct panel_desc hitachi_tx23d38vm0caa = {
1544         .modes = &hitachi_tx23d38vm0caa_mode,
1545         .num_modes = 1,
1546         .bpc = 6,
1547         .size = {
1548                 .width = 195,
1549                 .height = 117,
1550         },
1551         .delay = {
1552                 .enable = 160,
1553                 .disable = 160,
1554         },
1555 };
1556 
1557 static const struct drm_display_mode innolux_at043tn24_mode = {
1558         .clock = 9000,
1559         .hdisplay = 480,
1560         .hsync_start = 480 + 2,
1561         .hsync_end = 480 + 2 + 41,
1562         .htotal = 480 + 2 + 41 + 2,
1563         .vdisplay = 272,
1564         .vsync_start = 272 + 2,
1565         .vsync_end = 272 + 2 + 10,
1566         .vtotal = 272 + 2 + 10 + 2,
1567         .vrefresh = 60,
1568         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1569 };
1570 
1571 static const struct panel_desc innolux_at043tn24 = {
1572         .modes = &innolux_at043tn24_mode,
1573         .num_modes = 1,
1574         .bpc = 8,
1575         .size = {
1576                 .width = 95,
1577                 .height = 54,
1578         },
1579         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1580         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1581 };
1582 
1583 static const struct drm_display_mode innolux_at070tn92_mode = {
1584         .clock = 33333,
1585         .hdisplay = 800,
1586         .hsync_start = 800 + 210,
1587         .hsync_end = 800 + 210 + 20,
1588         .htotal = 800 + 210 + 20 + 46,
1589         .vdisplay = 480,
1590         .vsync_start = 480 + 22,
1591         .vsync_end = 480 + 22 + 10,
1592         .vtotal = 480 + 22 + 23 + 10,
1593         .vrefresh = 60,
1594 };
1595 
1596 static const struct panel_desc innolux_at070tn92 = {
1597         .modes = &innolux_at070tn92_mode,
1598         .num_modes = 1,
1599         .size = {
1600                 .width = 154,
1601                 .height = 86,
1602         },
1603         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1604 };
1605 
1606 static const struct display_timing innolux_g070y2_l01_timing = {
1607         .pixelclock = { 28000000, 29500000, 32000000 },
1608         .hactive = { 800, 800, 800 },
1609         .hfront_porch = { 61, 91, 141 },
1610         .hback_porch = { 60, 90, 140 },
1611         .hsync_len = { 12, 12, 12 },
1612         .vactive = { 480, 480, 480 },
1613         .vfront_porch = { 4, 9, 30 },
1614         .vback_porch = { 4, 8, 28 },
1615         .vsync_len = { 2, 2, 2 },
1616         .flags = DISPLAY_FLAGS_DE_HIGH,
1617 };
1618 
1619 static const struct panel_desc innolux_g070y2_l01 = {
1620         .timings = &innolux_g070y2_l01_timing,
1621         .num_timings = 1,
1622         .bpc = 6,
1623         .size = {
1624                 .width = 152,
1625                 .height = 91,
1626         },
1627         .delay = {
1628                 .prepare = 10,
1629                 .enable = 100,
1630                 .disable = 100,
1631                 .unprepare = 800,
1632         },
1633         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1634 };
1635 
1636 static const struct display_timing innolux_g101ice_l01_timing = {
1637         .pixelclock = { 60400000, 71100000, 74700000 },
1638         .hactive = { 1280, 1280, 1280 },
1639         .hfront_porch = { 41, 80, 100 },
1640         .hback_porch = { 40, 79, 99 },
1641         .hsync_len = { 1, 1, 1 },
1642         .vactive = { 800, 800, 800 },
1643         .vfront_porch = { 5, 11, 14 },
1644         .vback_porch = { 4, 11, 14 },
1645         .vsync_len = { 1, 1, 1 },
1646         .flags = DISPLAY_FLAGS_DE_HIGH,
1647 };
1648 
1649 static const struct panel_desc innolux_g101ice_l01 = {
1650         .timings = &innolux_g101ice_l01_timing,
1651         .num_timings = 1,
1652         .bpc = 8,
1653         .size = {
1654                 .width = 217,
1655                 .height = 135,
1656         },
1657         .delay = {
1658                 .enable = 200,
1659                 .disable = 200,
1660         },
1661         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1662 };
1663 
1664 static const struct display_timing innolux_g121i1_l01_timing = {
1665         .pixelclock = { 67450000, 71000000, 74550000 },
1666         .hactive = { 1280, 1280, 1280 },
1667         .hfront_porch = { 40, 80, 160 },
1668         .hback_porch = { 39, 79, 159 },
1669         .hsync_len = { 1, 1, 1 },
1670         .vactive = { 800, 800, 800 },
1671         .vfront_porch = { 5, 11, 100 },
1672         .vback_porch = { 4, 11, 99 },
1673         .vsync_len = { 1, 1, 1 },
1674 };
1675 
1676 static const struct panel_desc innolux_g121i1_l01 = {
1677         .timings = &innolux_g121i1_l01_timing,
1678         .num_timings = 1,
1679         .bpc = 6,
1680         .size = {
1681                 .width = 261,
1682                 .height = 163,
1683         },
1684         .delay = {
1685                 .enable = 200,
1686                 .disable = 20,
1687         },
1688         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1689 };
1690 
1691 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1692         .clock = 65000,
1693         .hdisplay = 1024,
1694         .hsync_start = 1024 + 0,
1695         .hsync_end = 1024 + 1,
1696         .htotal = 1024 + 0 + 1 + 320,
1697         .vdisplay = 768,
1698         .vsync_start = 768 + 38,
1699         .vsync_end = 768 + 38 + 1,
1700         .vtotal = 768 + 38 + 1 + 0,
1701         .vrefresh = 60,
1702         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1703 };
1704 
1705 static const struct panel_desc innolux_g121x1_l03 = {
1706         .modes = &innolux_g121x1_l03_mode,
1707         .num_modes = 1,
1708         .bpc = 6,
1709         .size = {
1710                 .width = 246,
1711                 .height = 185,
1712         },
1713         .delay = {
1714                 .enable = 200,
1715                 .unprepare = 200,
1716                 .disable = 400,
1717         },
1718 };
1719 
1720 /*
1721  * Datasheet specifies that at 60 Hz refresh rate:
1722  * - total horizontal time: { 1506, 1592, 1716 }
1723  * - total vertical time: { 788, 800, 868 }
1724  *
1725  * ...but doesn't go into exactly how that should be split into a front
1726  * porch, back porch, or sync length.  For now we'll leave a single setting
1727  * here which allows a bit of tweaking of the pixel clock at the expense of
1728  * refresh rate.
1729  */
1730 static const struct display_timing innolux_n116bge_timing = {
1731         .pixelclock = { 72600000, 76420000, 80240000 },
1732         .hactive = { 1366, 1366, 1366 },
1733         .hfront_porch = { 136, 136, 136 },
1734         .hback_porch = { 60, 60, 60 },
1735         .hsync_len = { 30, 30, 30 },
1736         .vactive = { 768, 768, 768 },
1737         .vfront_porch = { 8, 8, 8 },
1738         .vback_porch = { 12, 12, 12 },
1739         .vsync_len = { 12, 12, 12 },
1740         .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1741 };
1742 
1743 static const struct panel_desc innolux_n116bge = {
1744         .timings = &innolux_n116bge_timing,
1745         .num_timings = 1,
1746         .bpc = 6,
1747         .size = {
1748                 .width = 256,
1749                 .height = 144,
1750         },
1751 };
1752 
1753 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1754         .clock = 69300,
1755         .hdisplay = 1366,
1756         .hsync_start = 1366 + 16,
1757         .hsync_end = 1366 + 16 + 34,
1758         .htotal = 1366 + 16 + 34 + 50,
1759         .vdisplay = 768,
1760         .vsync_start = 768 + 2,
1761         .vsync_end = 768 + 2 + 6,
1762         .vtotal = 768 + 2 + 6 + 12,
1763         .vrefresh = 60,
1764 };
1765 
1766 static const struct panel_desc innolux_n156bge_l21 = {
1767         .modes = &innolux_n156bge_l21_mode,
1768         .num_modes = 1,
1769         .bpc = 6,
1770         .size = {
1771                 .width = 344,
1772                 .height = 193,
1773         },
1774 };
1775 
1776 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1777         .clock = 206016,
1778         .hdisplay = 2160,
1779         .hsync_start = 2160 + 48,
1780         .hsync_end = 2160 + 48 + 32,
1781         .htotal = 2160 + 48 + 32 + 80,
1782         .vdisplay = 1440,
1783         .vsync_start = 1440 + 3,
1784         .vsync_end = 1440 + 3 + 10,
1785         .vtotal = 1440 + 3 + 10 + 27,
1786         .vrefresh = 60,
1787         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1788 };
1789 
1790 static const struct panel_desc innolux_p120zdg_bf1 = {
1791         .modes = &innolux_p120zdg_bf1_mode,
1792         .num_modes = 1,
1793         .bpc = 8,
1794         .size = {
1795                 .width = 254,
1796                 .height = 169,
1797         },
1798         .delay = {
1799                 .hpd_absent_delay = 200,
1800                 .unprepare = 500,
1801         },
1802 };
1803 
1804 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1805         .clock = 51501,
1806         .hdisplay = 1024,
1807         .hsync_start = 1024 + 128,
1808         .hsync_end = 1024 + 128 + 64,
1809         .htotal = 1024 + 128 + 64 + 128,
1810         .vdisplay = 600,
1811         .vsync_start = 600 + 16,
1812         .vsync_end = 600 + 16 + 4,
1813         .vtotal = 600 + 16 + 4 + 16,
1814         .vrefresh = 60,
1815 };
1816 
1817 static const struct panel_desc innolux_zj070na_01p = {
1818         .modes = &innolux_zj070na_01p_mode,
1819         .num_modes = 1,
1820         .bpc = 6,
1821         .size = {
1822                 .width = 154,
1823                 .height = 90,
1824         },
1825 };
1826 
1827 static const struct display_timing koe_tx14d24vm1bpa_timing = {
1828         .pixelclock = { 5580000, 5850000, 6200000 },
1829         .hactive = { 320, 320, 320 },
1830         .hfront_porch = { 30, 30, 30 },
1831         .hback_porch = { 30, 30, 30 },
1832         .hsync_len = { 1, 5, 17 },
1833         .vactive = { 240, 240, 240 },
1834         .vfront_porch = { 6, 6, 6 },
1835         .vback_porch = { 5, 5, 5 },
1836         .vsync_len = { 1, 2, 11 },
1837         .flags = DISPLAY_FLAGS_DE_HIGH,
1838 };
1839 
1840 static const struct panel_desc koe_tx14d24vm1bpa = {
1841         .timings = &koe_tx14d24vm1bpa_timing,
1842         .num_timings = 1,
1843         .bpc = 6,
1844         .size = {
1845                 .width = 115,
1846                 .height = 86,
1847         },
1848 };
1849 
1850 static const struct display_timing koe_tx31d200vm0baa_timing = {
1851         .pixelclock = { 39600000, 43200000, 48000000 },
1852         .hactive = { 1280, 1280, 1280 },
1853         .hfront_porch = { 16, 36, 56 },
1854         .hback_porch = { 16, 36, 56 },
1855         .hsync_len = { 8, 8, 8 },
1856         .vactive = { 480, 480, 480 },
1857         .vfront_porch = { 6, 21, 33 },
1858         .vback_porch = { 6, 21, 33 },
1859         .vsync_len = { 8, 8, 8 },
1860         .flags = DISPLAY_FLAGS_DE_HIGH,
1861 };
1862 
1863 static const struct panel_desc koe_tx31d200vm0baa = {
1864         .timings = &koe_tx31d200vm0baa_timing,
1865         .num_timings = 1,
1866         .bpc = 6,
1867         .size = {
1868                 .width = 292,
1869                 .height = 109,
1870         },
1871         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1872 };
1873 
1874 static const struct display_timing kyo_tcg121xglp_timing = {
1875         .pixelclock = { 52000000, 65000000, 71000000 },
1876         .hactive = { 1024, 1024, 1024 },
1877         .hfront_porch = { 2, 2, 2 },
1878         .hback_porch = { 2, 2, 2 },
1879         .hsync_len = { 86, 124, 244 },
1880         .vactive = { 768, 768, 768 },
1881         .vfront_porch = { 2, 2, 2 },
1882         .vback_porch = { 2, 2, 2 },
1883         .vsync_len = { 6, 34, 73 },
1884         .flags = DISPLAY_FLAGS_DE_HIGH,
1885 };
1886 
1887 static const struct panel_desc kyo_tcg121xglp = {
1888         .timings = &kyo_tcg121xglp_timing,
1889         .num_timings = 1,
1890         .bpc = 8,
1891         .size = {
1892                 .width = 246,
1893                 .height = 184,
1894         },
1895         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1896 };
1897 
1898 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1899         .clock = 7000,
1900         .hdisplay = 320,
1901         .hsync_start = 320 + 20,
1902         .hsync_end = 320 + 20 + 30,
1903         .htotal = 320 + 20 + 30 + 38,
1904         .vdisplay = 240,
1905         .vsync_start = 240 + 4,
1906         .vsync_end = 240 + 4 + 3,
1907         .vtotal = 240 + 4 + 3 + 15,
1908         .vrefresh = 60,
1909 };
1910 
1911 static const struct panel_desc lemaker_bl035_rgb_002 = {
1912         .modes = &lemaker_bl035_rgb_002_mode,
1913         .num_modes = 1,
1914         .size = {
1915                 .width = 70,
1916                 .height = 52,
1917         },
1918         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1919         .bus_flags = DRM_BUS_FLAG_DE_LOW,
1920 };
1921 
1922 static const struct drm_display_mode lg_lb070wv8_mode = {
1923         .clock = 33246,
1924         .hdisplay = 800,
1925         .hsync_start = 800 + 88,
1926         .hsync_end = 800 + 88 + 80,
1927         .htotal = 800 + 88 + 80 + 88,
1928         .vdisplay = 480,
1929         .vsync_start = 480 + 10,
1930         .vsync_end = 480 + 10 + 25,
1931         .vtotal = 480 + 10 + 25 + 10,
1932         .vrefresh = 60,
1933 };
1934 
1935 static const struct panel_desc lg_lb070wv8 = {
1936         .modes = &lg_lb070wv8_mode,
1937         .num_modes = 1,
1938         .bpc = 16,
1939         .size = {
1940                 .width = 151,
1941                 .height = 91,
1942         },
1943         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1944 };
1945 
1946 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1947         .clock = 200000,
1948         .hdisplay = 1536,
1949         .hsync_start = 1536 + 12,
1950         .hsync_end = 1536 + 12 + 16,
1951         .htotal = 1536 + 12 + 16 + 48,
1952         .vdisplay = 2048,
1953         .vsync_start = 2048 + 8,
1954         .vsync_end = 2048 + 8 + 4,
1955         .vtotal = 2048 + 8 + 4 + 8,
1956         .vrefresh = 60,
1957         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1958 };
1959 
1960 static const struct panel_desc lg_lp079qx1_sp0v = {
1961         .modes = &lg_lp079qx1_sp0v_mode,
1962         .num_modes = 1,
1963         .size = {
1964                 .width = 129,
1965                 .height = 171,
1966         },
1967 };
1968 
1969 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1970         .clock = 205210,
1971         .hdisplay = 2048,
1972         .hsync_start = 2048 + 150,
1973         .hsync_end = 2048 + 150 + 5,
1974         .htotal = 2048 + 150 + 5 + 5,
1975         .vdisplay = 1536,
1976         .vsync_start = 1536 + 3,
1977         .vsync_end = 1536 + 3 + 1,
1978         .vtotal = 1536 + 3 + 1 + 9,
1979         .vrefresh = 60,
1980 };
1981 
1982 static const struct panel_desc lg_lp097qx1_spa1 = {
1983         .modes = &lg_lp097qx1_spa1_mode,
1984         .num_modes = 1,
1985         .size = {
1986                 .width = 208,
1987                 .height = 147,
1988         },
1989 };
1990 
1991 static const struct drm_display_mode lg_lp120up1_mode = {
1992         .clock = 162300,
1993         .hdisplay = 1920,
1994         .hsync_start = 1920 + 40,
1995         .hsync_end = 1920 + 40 + 40,
1996         .htotal = 1920 + 40 + 40+ 80,
1997         .vdisplay = 1280,
1998         .vsync_start = 1280 + 4,
1999         .vsync_end = 1280 + 4 + 4,
2000         .vtotal = 1280 + 4 + 4 + 12,
2001         .vrefresh = 60,
2002 };
2003 
2004 static const struct panel_desc lg_lp120up1 = {
2005         .modes = &lg_lp120up1_mode,
2006         .num_modes = 1,
2007         .bpc = 8,
2008         .size = {
2009                 .width = 267,
2010                 .height = 183,
2011         },
2012 };
2013 
2014 static const struct drm_display_mode lg_lp129qe_mode = {
2015         .clock = 285250,
2016         .hdisplay = 2560,
2017         .hsync_start = 2560 + 48,
2018         .hsync_end = 2560 + 48 + 32,
2019         .htotal = 2560 + 48 + 32 + 80,
2020         .vdisplay = 1700,
2021         .vsync_start = 1700 + 3,
2022         .vsync_end = 1700 + 3 + 10,
2023         .vtotal = 1700 + 3 + 10 + 36,
2024         .vrefresh = 60,
2025 };
2026 
2027 static const struct panel_desc lg_lp129qe = {
2028         .modes = &lg_lp129qe_mode,
2029         .num_modes = 1,
2030         .bpc = 8,
2031         .size = {
2032                 .width = 272,
2033                 .height = 181,
2034         },
2035 };
2036 
2037 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2038         .clock = 30400,
2039         .hdisplay = 800,
2040         .hsync_start = 800 + 0,
2041         .hsync_end = 800 + 1,
2042         .htotal = 800 + 0 + 1 + 160,
2043         .vdisplay = 480,
2044         .vsync_start = 480 + 0,
2045         .vsync_end = 480 + 48 + 1,
2046         .vtotal = 480 + 48 + 1 + 0,
2047         .vrefresh = 60,
2048         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2049 };
2050 
2051 static const struct drm_display_mode logicpd_type_28_mode = {
2052         .clock = 9000,
2053         .hdisplay = 480,
2054         .hsync_start = 480 + 3,
2055         .hsync_end = 480 + 3 + 42,
2056         .htotal = 480 + 3 + 42 + 2,
2057 
2058         .vdisplay = 272,
2059         .vsync_start = 272 + 2,
2060         .vsync_end = 272 + 2 + 11,
2061         .vtotal = 272 + 2 + 11 + 3,
2062         .vrefresh = 60,
2063         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2064 };
2065 
2066 static const struct panel_desc logicpd_type_28 = {
2067         .modes = &logicpd_type_28_mode,
2068         .num_modes = 1,
2069         .bpc = 8,
2070         .size = {
2071                 .width = 105,
2072                 .height = 67,
2073         },
2074         .delay = {
2075                 .prepare = 200,
2076                 .enable = 200,
2077                 .unprepare = 200,
2078                 .disable = 200,
2079         },
2080         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2081         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2082                      DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2083 };
2084 
2085 static const struct panel_desc mitsubishi_aa070mc01 = {
2086         .modes = &mitsubishi_aa070mc01_mode,
2087         .num_modes = 1,
2088         .bpc = 8,
2089         .size = {
2090                 .width = 152,
2091                 .height = 91,
2092         },
2093 
2094         .delay = {
2095                 .enable = 200,
2096                 .unprepare = 200,
2097                 .disable = 400,
2098         },
2099         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2100         .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2101 };
2102 
2103 static const struct display_timing nec_nl12880bc20_05_timing = {
2104         .pixelclock = { 67000000, 71000000, 75000000 },
2105         .hactive = { 1280, 1280, 1280 },
2106         .hfront_porch = { 2, 30, 30 },
2107         .hback_porch = { 6, 100, 100 },
2108         .hsync_len = { 2, 30, 30 },
2109         .vactive = { 800, 800, 800 },
2110         .vfront_porch = { 5, 5, 5 },
2111         .vback_porch = { 11, 11, 11 },
2112         .vsync_len = { 7, 7, 7 },
2113 };
2114 
2115 static const struct panel_desc nec_nl12880bc20_05 = {
2116         .timings = &nec_nl12880bc20_05_timing,
2117         .num_timings = 1,
2118         .bpc = 8,
2119         .size = {
2120                 .width = 261,
2121                 .height = 163,
2122         },
2123         .delay = {
2124                 .enable = 50,
2125                 .disable = 50,
2126         },
2127         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2128 };
2129 
2130 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2131         .clock = 10870,
2132         .hdisplay = 480,
2133         .hsync_start = 480 + 2,
2134         .hsync_end = 480 + 2 + 41,
2135         .htotal = 480 + 2 + 41 + 2,
2136         .vdisplay = 272,
2137         .vsync_start = 272 + 2,
2138         .vsync_end = 272 + 2 + 4,
2139         .vtotal = 272 + 2 + 4 + 2,
2140         .vrefresh = 74,
2141         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2142 };
2143 
2144 static const struct panel_desc nec_nl4827hc19_05b = {
2145         .modes = &nec_nl4827hc19_05b_mode,
2146         .num_modes = 1,
2147         .bpc = 8,
2148         .size = {
2149                 .width = 95,
2150                 .height = 54,
2151         },
2152         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2153         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2154 };
2155 
2156 static const struct drm_display_mode netron_dy_e231732_mode = {
2157         .clock = 66000,
2158         .hdisplay = 1024,
2159         .hsync_start = 1024 + 160,
2160         .hsync_end = 1024 + 160 + 70,
2161         .htotal = 1024 + 160 + 70 + 90,
2162         .vdisplay = 600,
2163         .vsync_start = 600 + 127,
2164         .vsync_end = 600 + 127 + 20,
2165         .vtotal = 600 + 127 + 20 + 3,
2166         .vrefresh = 60,
2167 };
2168 
2169 static const struct panel_desc netron_dy_e231732 = {
2170         .modes = &netron_dy_e231732_mode,
2171         .num_modes = 1,
2172         .size = {
2173                 .width = 154,
2174                 .height = 87,
2175         },
2176         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2177 };
2178 
2179 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2180         .clock = 9000,
2181         .hdisplay = 480,
2182         .hsync_start = 480 + 2,
2183         .hsync_end = 480 + 2 + 41,
2184         .htotal = 480 + 2 + 41 + 2,
2185         .vdisplay = 272,
2186         .vsync_start = 272 + 2,
2187         .vsync_end = 272 + 2 + 10,
2188         .vtotal = 272 + 2 + 10 + 2,
2189         .vrefresh = 60,
2190         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2191 };
2192 
2193 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2194         .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2195         .num_modes = 1,
2196         .bpc = 8,
2197         .size = {
2198                 .width = 95,
2199                 .height = 54,
2200         },
2201         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2202         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2203                      DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2204 };
2205 
2206 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2207         .pixelclock = { 130000000, 148350000, 163000000 },
2208         .hactive = { 1920, 1920, 1920 },
2209         .hfront_porch = { 80, 100, 100 },
2210         .hback_porch = { 100, 120, 120 },
2211         .hsync_len = { 50, 60, 60 },
2212         .vactive = { 1080, 1080, 1080 },
2213         .vfront_porch = { 12, 30, 30 },
2214         .vback_porch = { 4, 10, 10 },
2215         .vsync_len = { 4, 5, 5 },
2216 };
2217 
2218 static const struct panel_desc nlt_nl192108ac18_02d = {
2219         .timings = &nlt_nl192108ac18_02d_timing,
2220         .num_timings = 1,
2221         .bpc = 8,
2222         .size = {
2223                 .width = 344,
2224                 .height = 194,
2225         },
2226         .delay = {
2227                 .unprepare = 500,
2228         },
2229         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2230 };
2231 
2232 static const struct drm_display_mode nvd_9128_mode = {
2233         .clock = 29500,
2234         .hdisplay = 800,
2235         .hsync_start = 800 + 130,
2236         .hsync_end = 800 + 130 + 98,
2237         .htotal = 800 + 0 + 130 + 98,
2238         .vdisplay = 480,
2239         .vsync_start = 480 + 10,
2240         .vsync_end = 480 + 10 + 50,
2241         .vtotal = 480 + 0 + 10 + 50,
2242 };
2243 
2244 static const struct panel_desc nvd_9128 = {
2245         .modes = &nvd_9128_mode,
2246         .num_modes = 1,
2247         .bpc = 8,
2248         .size = {
2249                 .width = 156,
2250                 .height = 88,
2251         },
2252         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2253 };
2254 
2255 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2256         .pixelclock = { 30000000, 30000000, 40000000 },
2257         .hactive = { 800, 800, 800 },
2258         .hfront_porch = { 40, 40, 40 },
2259         .hback_porch = { 40, 40, 40 },
2260         .hsync_len = { 1, 48, 48 },
2261         .vactive = { 480, 480, 480 },
2262         .vfront_porch = { 13, 13, 13 },
2263         .vback_porch = { 29, 29, 29 },
2264         .vsync_len = { 3, 3, 3 },
2265         .flags = DISPLAY_FLAGS_DE_HIGH,
2266 };
2267 
2268 static const struct panel_desc okaya_rs800480t_7x0gp = {
2269         .timings = &okaya_rs800480t_7x0gp_timing,
2270         .num_timings = 1,
2271         .bpc = 6,
2272         .size = {
2273                 .width = 154,
2274                 .height = 87,
2275         },
2276         .delay = {
2277                 .prepare = 41,
2278                 .enable = 50,
2279                 .unprepare = 41,
2280                 .disable = 50,
2281         },
2282         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2283 };
2284 
2285 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2286         .clock = 9000,
2287         .hdisplay = 480,
2288         .hsync_start = 480 + 5,
2289         .hsync_end = 480 + 5 + 30,
2290         .htotal = 480 + 5 + 30 + 10,
2291         .vdisplay = 272,
2292         .vsync_start = 272 + 8,
2293         .vsync_end = 272 + 8 + 5,
2294         .vtotal = 272 + 8 + 5 + 3,
2295         .vrefresh = 60,
2296 };
2297 
2298 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2299         .modes = &olimex_lcd_olinuxino_43ts_mode,
2300         .num_modes = 1,
2301         .size = {
2302                 .width = 95,
2303                 .height = 54,
2304         },
2305         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2306 };
2307 
2308 /*
2309  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2310  * pixel clocks, but this is the timing that was being used in the Adafruit
2311  * installation instructions.
2312  */
2313 static const struct drm_display_mode ontat_yx700wv03_mode = {
2314         .clock = 29500,
2315         .hdisplay = 800,
2316         .hsync_start = 824,
2317         .hsync_end = 896,
2318         .htotal = 992,
2319         .vdisplay = 480,
2320         .vsync_start = 483,
2321         .vsync_end = 493,
2322         .vtotal = 500,
2323         .vrefresh = 60,
2324         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2325 };
2326 
2327 /*
2328  * Specification at:
2329  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2330  */
2331 static const struct panel_desc ontat_yx700wv03 = {
2332         .modes = &ontat_yx700wv03_mode,
2333         .num_modes = 1,
2334         .bpc = 8,
2335         .size = {
2336                 .width = 154,
2337                 .height = 83,
2338         },
2339         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2340 };
2341 
2342 static const struct drm_display_mode ortustech_com37h3m_mode  = {
2343         .clock = 22153,
2344         .hdisplay = 480,
2345         .hsync_start = 480 + 8,
2346         .hsync_end = 480 + 8 + 10,
2347         .htotal = 480 + 8 + 10 + 10,
2348         .vdisplay = 640,
2349         .vsync_start = 640 + 4,
2350         .vsync_end = 640 + 4 + 3,
2351         .vtotal = 640 + 4 + 3 + 4,
2352         .vrefresh = 60,
2353         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2354 };
2355 
2356 static const struct panel_desc ortustech_com37h3m = {
2357         .modes = &ortustech_com37h3m_mode,
2358         .num_modes = 1,
2359         .bpc = 8,
2360         .size = {
2361                 .width = 56,    /* 56.16mm */
2362                 .height = 75,   /* 74.88mm */
2363         },
2364         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2365         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2366                      DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2367 };
2368 
2369 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
2370         .clock = 25000,
2371         .hdisplay = 480,
2372         .hsync_start = 480 + 10,
2373         .hsync_end = 480 + 10 + 10,
2374         .htotal = 480 + 10 + 10 + 15,
2375         .vdisplay = 800,
2376         .vsync_start = 800 + 3,
2377         .vsync_end = 800 + 3 + 3,
2378         .vtotal = 800 + 3 + 3 + 3,
2379         .vrefresh = 60,
2380 };
2381 
2382 static const struct panel_desc ortustech_com43h4m85ulc = {
2383         .modes = &ortustech_com43h4m85ulc_mode,
2384         .num_modes = 1,
2385         .bpc = 8,
2386         .size = {
2387                 .width = 56,
2388                 .height = 93,
2389         },
2390         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2391         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2392 };
2393 
2394 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode  = {
2395         .clock = 33000,
2396         .hdisplay = 800,
2397         .hsync_start = 800 + 210,
2398         .hsync_end = 800 + 210 + 30,
2399         .htotal = 800 + 210 + 30 + 16,
2400         .vdisplay = 480,
2401         .vsync_start = 480 + 22,
2402         .vsync_end = 480 + 22 + 13,
2403         .vtotal = 480 + 22 + 13 + 10,
2404         .vrefresh = 60,
2405         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2406 };
2407 
2408 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2409         .modes = &osddisplays_osd070t1718_19ts_mode,
2410         .num_modes = 1,
2411         .bpc = 8,
2412         .size = {
2413                 .width = 152,
2414                 .height = 91,
2415         },
2416         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2417         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2418 };
2419 
2420 static const struct drm_display_mode pda_91_00156_a0_mode = {
2421         .clock = 33300,
2422         .hdisplay = 800,
2423         .hsync_start = 800 + 1,
2424         .hsync_end = 800 + 1 + 64,
2425         .htotal = 800 + 1 + 64 + 64,
2426         .vdisplay = 480,
2427         .vsync_start = 480 + 1,
2428         .vsync_end = 480 + 1 + 23,
2429         .vtotal = 480 + 1 + 23 + 22,
2430         .vrefresh = 60,
2431 };
2432 
2433 static const struct panel_desc pda_91_00156_a0  = {
2434         .modes = &pda_91_00156_a0_mode,
2435         .num_modes = 1,
2436         .size = {
2437                 .width = 152,
2438                 .height = 91,
2439         },
2440         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2441 };
2442 
2443 
2444 static const struct drm_display_mode qd43003c0_40_mode = {
2445         .clock = 9000,
2446         .hdisplay = 480,
2447         .hsync_start = 480 + 8,
2448         .hsync_end = 480 + 8 + 4,
2449         .htotal = 480 + 8 + 4 + 39,
2450         .vdisplay = 272,
2451         .vsync_start = 272 + 4,
2452         .vsync_end = 272 + 4 + 10,
2453         .vtotal = 272 + 4 + 10 + 2,
2454         .vrefresh = 60,
2455 };
2456 
2457 static const struct panel_desc qd43003c0_40 = {
2458         .modes = &qd43003c0_40_mode,
2459         .num_modes = 1,
2460         .bpc = 8,
2461         .size = {
2462                 .width = 95,
2463                 .height = 53,
2464         },
2465         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2466 };
2467 
2468 static const struct display_timing rocktech_rk070er9427_timing = {
2469         .pixelclock = { 26400000, 33300000, 46800000 },
2470         .hactive = { 800, 800, 800 },
2471         .hfront_porch = { 16, 210, 354 },
2472         .hback_porch = { 46, 46, 46 },
2473         .hsync_len = { 1, 1, 1 },
2474         .vactive = { 480, 480, 480 },
2475         .vfront_porch = { 7, 22, 147 },
2476         .vback_porch = { 23, 23, 23 },
2477         .vsync_len = { 1, 1, 1 },
2478         .flags = DISPLAY_FLAGS_DE_HIGH,
2479 };
2480 
2481 static const struct panel_desc rocktech_rk070er9427 = {
2482         .timings = &rocktech_rk070er9427_timing,
2483         .num_timings = 1,
2484         .bpc = 6,
2485         .size = {
2486                 .width = 154,
2487                 .height = 86,
2488         },
2489         .delay = {
2490                 .prepare = 41,
2491                 .enable = 50,
2492                 .unprepare = 41,
2493                 .disable = 50,
2494         },
2495         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2496 };
2497 
2498 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2499         .clock = 271560,
2500         .hdisplay = 2560,
2501         .hsync_start = 2560 + 48,
2502         .hsync_end = 2560 + 48 + 32,
2503         .htotal = 2560 + 48 + 32 + 80,
2504         .vdisplay = 1600,
2505         .vsync_start = 1600 + 2,
2506         .vsync_end = 1600 + 2 + 5,
2507         .vtotal = 1600 + 2 + 5 + 57,
2508         .vrefresh = 60,
2509 };
2510 
2511 static const struct panel_desc samsung_lsn122dl01_c01 = {
2512         .modes = &samsung_lsn122dl01_c01_mode,
2513         .num_modes = 1,
2514         .size = {
2515                 .width = 263,
2516                 .height = 164,
2517         },
2518 };
2519 
2520 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2521         .clock = 54030,
2522         .hdisplay = 1024,
2523         .hsync_start = 1024 + 24,
2524         .hsync_end = 1024 + 24 + 136,
2525         .htotal = 1024 + 24 + 136 + 160,
2526         .vdisplay = 600,
2527         .vsync_start = 600 + 3,
2528         .vsync_end = 600 + 3 + 6,
2529         .vtotal = 600 + 3 + 6 + 61,
2530         .vrefresh = 60,
2531 };
2532 
2533 static const struct panel_desc samsung_ltn101nt05 = {
2534         .modes = &samsung_ltn101nt05_mode,
2535         .num_modes = 1,
2536         .bpc = 6,
2537         .size = {
2538                 .width = 223,
2539                 .height = 125,
2540         },
2541 };
2542 
2543 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2544         .clock = 76300,
2545         .hdisplay = 1366,
2546         .hsync_start = 1366 + 64,
2547         .hsync_end = 1366 + 64 + 48,
2548         .htotal = 1366 + 64 + 48 + 128,
2549         .vdisplay = 768,
2550         .vsync_start = 768 + 2,
2551         .vsync_end = 768 + 2 + 5,
2552         .vtotal = 768 + 2 + 5 + 17,
2553         .vrefresh = 60,
2554 };
2555 
2556 static const struct panel_desc samsung_ltn140at29_301 = {
2557         .modes = &samsung_ltn140at29_301_mode,
2558         .num_modes = 1,
2559         .bpc = 6,
2560         .size = {
2561                 .width = 320,
2562                 .height = 187,
2563         },
2564 };
2565 
2566 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2567         .clock = 168480,
2568         .hdisplay = 1920,
2569         .hsync_start = 1920 + 48,
2570         .hsync_end = 1920 + 48 + 32,
2571         .htotal = 1920 + 48 + 32 + 80,
2572         .vdisplay = 1280,
2573         .vsync_start = 1280 + 3,
2574         .vsync_end = 1280 + 3 + 10,
2575         .vtotal = 1280 + 3 + 10 + 57,
2576         .vrefresh = 60,
2577         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2578 };
2579 
2580 static const struct panel_desc sharp_ld_d5116z01b = {
2581         .modes = &sharp_ld_d5116z01b_mode,
2582         .num_modes = 1,
2583         .bpc = 8,
2584         .size = {
2585                 .width = 260,
2586                 .height = 120,
2587         },
2588         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2589         .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2590 };
2591 
2592 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2593         .clock = 33260,
2594         .hdisplay = 800,
2595         .hsync_start = 800 + 64,
2596         .hsync_end = 800 + 64 + 128,
2597         .htotal = 800 + 64 + 128 + 64,
2598         .vdisplay = 480,
2599         .vsync_start = 480 + 8,
2600         .vsync_end = 480 + 8 + 2,
2601         .vtotal = 480 + 8 + 2 + 35,
2602         .vrefresh = 60,
2603         .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2604 };
2605 
2606 static const struct panel_desc sharp_lq070y3dg3b = {
2607         .modes = &sharp_lq070y3dg3b_mode,
2608         .num_modes = 1,
2609         .bpc = 8,
2610         .size = {
2611                 .width = 152,   /* 152.4mm */
2612                 .height = 91,   /* 91.4mm */
2613         },
2614         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2615         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2616                      DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2617 };
2618 
2619 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2620         .clock = 5500,
2621         .hdisplay = 240,
2622         .hsync_start = 240 + 16,
2623         .hsync_end = 240 + 16 + 7,
2624         .htotal = 240 + 16 + 7 + 5,
2625         .vdisplay = 320,
2626         .vsync_start = 320 + 9,
2627         .vsync_end = 320 + 9 + 1,
2628         .vtotal = 320 + 9 + 1 + 7,
2629         .vrefresh = 60,
2630 };
2631 
2632 static const struct panel_desc sharp_lq035q7db03 = {
2633         .modes = &sharp_lq035q7db03_mode,
2634         .num_modes = 1,
2635         .bpc = 6,
2636         .size = {
2637                 .width = 54,
2638                 .height = 72,
2639         },
2640         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2641 };
2642 
2643 static const struct display_timing sharp_lq101k1ly04_timing = {
2644         .pixelclock = { 60000000, 65000000, 80000000 },
2645         .hactive = { 1280, 1280, 1280 },
2646         .hfront_porch = { 20, 20, 20 },
2647         .hback_porch = { 20, 20, 20 },
2648         .hsync_len = { 10, 10, 10 },
2649         .vactive = { 800, 800, 800 },
2650         .vfront_porch = { 4, 4, 4 },
2651         .vback_porch = { 4, 4, 4 },
2652         .vsync_len = { 4, 4, 4 },
2653         .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2654 };
2655 
2656 static const struct panel_desc sharp_lq101k1ly04 = {
2657         .timings = &sharp_lq101k1ly04_timing,
2658         .num_timings = 1,
2659         .bpc = 8,
2660         .size = {
2661                 .width = 217,
2662                 .height = 136,
2663         },
2664         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2665 };
2666 
2667 static const struct display_timing sharp_lq123p1jx31_timing = {
2668         .pixelclock = { 252750000, 252750000, 266604720 },
2669         .hactive = { 2400, 2400, 2400 },
2670         .hfront_porch = { 48, 48, 48 },
2671         .hback_porch = { 80, 80, 84 },
2672         .hsync_len = { 32, 32, 32 },
2673         .vactive = { 1600, 1600, 1600 },
2674         .vfront_porch = { 3, 3, 3 },
2675         .vback_porch = { 33, 33, 120 },
2676         .vsync_len = { 10, 10, 10 },
2677         .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2678 };
2679 
2680 static const struct panel_desc sharp_lq123p1jx31 = {
2681         .timings = &sharp_lq123p1jx31_timing,
2682         .num_timings = 1,
2683         .bpc = 8,
2684         .size = {
2685                 .width = 259,
2686                 .height = 173,
2687         },
2688         .delay = {
2689                 .prepare = 110,
2690                 .enable = 50,
2691                 .unprepare = 550,
2692         },
2693 };
2694 
2695 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2696         .clock = 71100,
2697         .hdisplay = 1024,
2698         .hsync_start = 1024 + 168,
2699         .hsync_end = 1024 + 168 + 64,
2700         .htotal = 1024 + 168 + 64 + 88,
2701         .vdisplay = 768,
2702         .vsync_start = 768 + 37,
2703         .vsync_end = 768 + 37 + 2,
2704         .vtotal = 768 + 37 + 2 + 8,
2705         .vrefresh = 60,
2706 };
2707 
2708 static const struct panel_desc sharp_lq150x1lg11 = {
2709         .modes = &sharp_lq150x1lg11_mode,
2710         .num_modes = 1,
2711         .bpc = 6,
2712         .size = {
2713                 .width = 304,
2714                 .height = 228,
2715         },
2716         .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2717 };
2718 
2719 static const struct display_timing sharp_ls020b1dd01d_timing = {
2720         .pixelclock = { 2000000, 4200000, 5000000 },
2721         .hactive = { 240, 240, 240 },
2722         .hfront_porch = { 66, 66, 66 },
2723         .hback_porch = { 1, 1, 1 },
2724         .hsync_len = { 1, 1, 1 },
2725         .vactive = { 160, 160, 160 },
2726         .vfront_porch = { 52, 52, 52 },
2727         .vback_porch = { 6, 6, 6 },
2728         .vsync_len = { 10, 10, 10 },
2729         .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2730 };
2731 
2732 static const struct panel_desc sharp_ls020b1dd01d = {
2733         .timings = &sharp_ls020b1dd01d_timing,
2734         .num_timings = 1,
2735         .bpc = 6,
2736         .size = {
2737                 .width = 42,
2738                 .height = 28,
2739         },
2740         .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2741         .bus_flags = DRM_BUS_FLAG_DE_HIGH
2742                    | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2743                    | DRM_BUS_FLAG_SHARP_SIGNALS,
2744 };
2745 
2746 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2747         .clock = 33300,
2748         .hdisplay = 800,
2749         .hsync_start = 800 + 1,
2750         .hsync_end = 800 + 1 + 64,
2751         .htotal = 800 + 1 + 64 + 64,
2752         .vdisplay = 480,
2753         .vsync_start = 480 + 1,
2754         .vsync_end = 480 + 1 + 23,
2755         .vtotal = 480 + 1 + 23 + 22,
2756         .vrefresh = 60,
2757 };
2758 
2759 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2760         .modes = &shelly_sca07010_bfn_lnn_mode,
2761         .num_modes = 1,
2762         .size = {
2763                 .width = 152,
2764                 .height = 91,
2765         },
2766         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2767 };
2768 
2769 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2770         .clock = 147000,
2771         .hdisplay = 1920,
2772         .hsync_start = 1920 + 16,
2773         .hsync_end = 1920 + 16 + 16,
2774         .htotal = 1920 + 16 + 16 + 32,
2775         .vdisplay = 1200,
2776         .vsync_start = 1200 + 15,
2777         .vsync_end = 1200 + 15 + 2,
2778         .vtotal = 1200 + 15 + 2 + 18,
2779         .vrefresh = 60,
2780         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2781 };
2782 
2783 static const struct panel_desc starry_kr122ea0sra = {
2784         .modes = &starry_kr122ea0sra_mode,
2785         .num_modes = 1,
2786         .size = {
2787                 .width = 263,
2788                 .height = 164,
2789         },
2790         .delay = {
2791                 .prepare = 10 + 200,
2792                 .enable = 50,
2793                 .unprepare = 10 + 500,
2794         },
2795 };
2796 
2797 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2798         .clock = 30000,
2799         .hdisplay = 800,
2800         .hsync_start = 800 + 39,
2801         .hsync_end = 800 + 39 + 47,
2802         .htotal = 800 + 39 + 47 + 39,
2803         .vdisplay = 480,
2804         .vsync_start = 480 + 13,
2805         .vsync_end = 480 + 13 + 2,
2806         .vtotal = 480 + 13 + 2 + 29,
2807         .vrefresh = 62,
2808 };
2809 
2810 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2811         .modes = &tfc_s9700rtwv43tr_01b_mode,
2812         .num_modes = 1,
2813         .bpc = 8,
2814         .size = {
2815                 .width = 155,
2816                 .height = 90,
2817         },
2818         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2819         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2820 };
2821 
2822 static const struct display_timing tianma_tm070jdhg30_timing = {
2823         .pixelclock = { 62600000, 68200000, 78100000 },
2824         .hactive = { 1280, 1280, 1280 },
2825         .hfront_porch = { 15, 64, 159 },
2826         .hback_porch = { 5, 5, 5 },
2827         .hsync_len = { 1, 1, 256 },
2828         .vactive = { 800, 800, 800 },
2829         .vfront_porch = { 3, 40, 99 },
2830         .vback_porch = { 2, 2, 2 },
2831         .vsync_len = { 1, 1, 128 },
2832         .flags = DISPLAY_FLAGS_DE_HIGH,
2833 };
2834 
2835 static const struct panel_desc tianma_tm070jdhg30 = {
2836         .timings = &tianma_tm070jdhg30_timing,
2837         .num_timings = 1,
2838         .bpc = 8,
2839         .size = {
2840                 .width = 151,
2841                 .height = 95,
2842         },
2843         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2844 };
2845 
2846 static const struct display_timing tianma_tm070rvhg71_timing = {
2847         .pixelclock = { 27700000, 29200000, 39600000 },
2848         .hactive = { 800, 800, 800 },
2849         .hfront_porch = { 12, 40, 212 },
2850         .hback_porch = { 88, 88, 88 },
2851         .hsync_len = { 1, 1, 40 },
2852         .vactive = { 480, 480, 480 },
2853         .vfront_porch = { 1, 13, 88 },
2854         .vback_porch = { 32, 32, 32 },
2855         .vsync_len = { 1, 1, 3 },
2856         .flags = DISPLAY_FLAGS_DE_HIGH,
2857 };
2858 
2859 static const struct panel_desc tianma_tm070rvhg71 = {
2860         .timings = &tianma_tm070rvhg71_timing,
2861         .num_timings = 1,
2862         .bpc = 8,
2863         .size = {
2864                 .width = 154,
2865                 .height = 86,
2866         },
2867         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2868 };
2869 
2870 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2871         {
2872                 .clock = 10000,
2873                 .hdisplay = 320,
2874                 .hsync_start = 320 + 50,
2875                 .hsync_end = 320 + 50 + 6,
2876                 .htotal = 320 + 50 + 6 + 38,
2877                 .vdisplay = 240,
2878                 .vsync_start = 240 + 3,
2879                 .vsync_end = 240 + 3 + 1,
2880                 .vtotal = 240 + 3 + 1 + 17,
2881                 .vrefresh = 60,
2882                 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2883         },
2884 };
2885 
2886 static const struct panel_desc ti_nspire_cx_lcd_panel = {
2887         .modes = ti_nspire_cx_lcd_mode,
2888         .num_modes = 1,
2889         .bpc = 8,
2890         .size = {
2891                 .width = 65,
2892                 .height = 49,
2893         },
2894         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2895         .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2896 };
2897 
2898 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2899         {
2900                 .clock = 10000,
2901                 .hdisplay = 320,
2902                 .hsync_start = 320 + 6,
2903                 .hsync_end = 320 + 6 + 6,
2904                 .htotal = 320 + 6 + 6 + 6,
2905                 .vdisplay = 240,
2906                 .vsync_start = 240 + 0,
2907                 .vsync_end = 240 + 0 + 1,
2908                 .vtotal = 240 + 0 + 1 + 0,
2909                 .vrefresh = 60,
2910                 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2911         },
2912 };
2913 
2914 static const struct panel_desc ti_nspire_classic_lcd_panel = {
2915         .modes = ti_nspire_classic_lcd_mode,
2916         .num_modes = 1,
2917         /* The grayscale panel has 8 bit for the color .. Y (black) */
2918         .bpc = 8,
2919         .size = {
2920                 .width = 71,
2921                 .height = 53,
2922         },
2923         /* This is the grayscale bus format */
2924         .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2925         .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2926 };
2927 
2928 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2929         .clock = 79500,
2930         .hdisplay = 1280,
2931         .hsync_start = 1280 + 192,
2932         .hsync_end = 1280 + 192 + 128,
2933         .htotal = 1280 + 192 + 128 + 64,
2934         .vdisplay = 768,
2935         .vsync_start = 768 + 20,
2936         .vsync_end = 768 + 20 + 7,
2937         .vtotal = 768 + 20 + 7 + 3,
2938         .vrefresh = 60,
2939 };
2940 
2941 static const struct panel_desc toshiba_lt089ac29000 = {
2942         .modes = &toshiba_lt089ac29000_mode,
2943         .num_modes = 1,
2944         .size = {
2945                 .width = 194,
2946                 .height = 116,
2947         },
2948         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2949         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2950 };
2951 
2952 static const struct drm_display_mode tpk_f07a_0102_mode = {
2953         .clock = 33260,
2954         .hdisplay = 800,
2955         .hsync_start = 800 + 40,
2956         .hsync_end = 800 + 40 + 128,
2957         .htotal = 800 + 40 + 128 + 88,
2958         .vdisplay = 480,
2959         .vsync_start = 480 + 10,
2960         .vsync_end = 480 + 10 + 2,
2961         .vtotal = 480 + 10 + 2 + 33,
2962         .vrefresh = 60,
2963 };
2964 
2965 static const struct panel_desc tpk_f07a_0102 = {
2966         .modes = &tpk_f07a_0102_mode,
2967         .num_modes = 1,
2968         .size = {
2969                 .width = 152,
2970                 .height = 91,
2971         },
2972         .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2973 };
2974 
2975 static const struct drm_display_mode tpk_f10a_0102_mode = {
2976         .clock = 45000,
2977         .hdisplay = 1024,
2978         .hsync_start = 1024 + 176,
2979         .hsync_end = 1024 + 176 + 5,
2980         .htotal = 1024 + 176 + 5 + 88,
2981         .vdisplay = 600,
2982         .vsync_start = 600 + 20,
2983         .vsync_end = 600 + 20 + 5,
2984         .vtotal = 600 + 20 + 5 + 25,
2985         .vrefresh = 60,
2986 };
2987 
2988 static const struct panel_desc tpk_f10a_0102 = {
2989         .modes = &tpk_f10a_0102_mode,
2990         .num_modes = 1,
2991         .size = {
2992                 .width = 223,
2993                 .height = 125,
2994         },
2995 };
2996 
2997 static const struct display_timing urt_umsh_8596md_timing = {
2998         .pixelclock = { 33260000, 33260000, 33260000 },
2999         .hactive = { 800, 800, 800 },
3000         .hfront_porch = { 41, 41, 41 },
3001         .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3002         .hsync_len = { 71, 128, 128 },
3003         .vactive = { 480, 480, 480 },
3004         .vfront_porch = { 10, 10, 10 },
3005         .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3006         .vsync_len = { 2, 2, 2 },
3007         .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3008                 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3009 };
3010 
3011 static const struct panel_desc urt_umsh_8596md_lvds = {
3012         .timings = &urt_umsh_8596md_timing,
3013         .num_timings = 1,
3014         .bpc = 6,
3015         .size = {
3016                 .width = 152,
3017                 .height = 91,
3018         },
3019         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3020 };
3021 
3022 static const struct panel_desc urt_umsh_8596md_parallel = {
3023         .timings = &urt_umsh_8596md_timing,
3024         .num_timings = 1,
3025         .bpc = 6,
3026         .size = {
3027                 .width = 152,
3028                 .height = 91,
3029         },
3030         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3031 };
3032 
3033 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3034         .clock = 33333,
3035         .hdisplay = 800,
3036         .hsync_start = 800 + 210,
3037         .hsync_end = 800 + 210 + 20,
3038         .htotal = 800 + 210 + 20 + 46,
3039         .vdisplay =  480,
3040         .vsync_start = 480 + 22,
3041         .vsync_end = 480 + 22 + 10,
3042         .vtotal = 480 + 22 + 10 + 23,
3043         .vrefresh = 60,
3044         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3045 };
3046 
3047 static const struct panel_desc vl050_8048nt_c01 = {
3048         .modes = &vl050_8048nt_c01_mode,
3049         .num_modes = 1,
3050         .bpc = 8,
3051         .size = {
3052                 .width = 120,
3053                 .height = 76,
3054         },
3055         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3056         .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3057 };
3058 
3059 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3060         .clock = 6410,
3061         .hdisplay = 320,
3062         .hsync_start = 320 + 20,
3063         .hsync_end = 320 + 20 + 30,
3064         .htotal = 320 + 20 + 30 + 38,
3065         .vdisplay = 240,
3066         .vsync_start = 240 + 4,
3067         .vsync_end = 240 + 4 + 3,
3068         .vtotal = 240 + 4 + 3 + 15,
3069         .vrefresh = 60,
3070         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3071 };
3072 
3073 static const struct panel_desc winstar_wf35ltiacd = {
3074         .modes = &winstar_wf35ltiacd_mode,
3075         .num_modes = 1,
3076         .bpc = 8,
3077         .size = {
3078                 .width = 70,
3079                 .height = 53,
3080         },
3081         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3082 };
3083 
3084 static const struct drm_display_mode arm_rtsm_mode[] = {
3085         {
3086                 .clock = 65000,
3087                 .hdisplay = 1024,
3088                 .hsync_start = 1024 + 24,
3089                 .hsync_end = 1024 + 24 + 136,
3090                 .htotal = 1024 + 24 + 136 + 160,
3091                 .vdisplay = 768,
3092                 .vsync_start = 768 + 3,
3093                 .vsync_end = 768 + 3 + 6,
3094                 .vtotal = 768 + 3 + 6 + 29,
3095                 .vrefresh = 60,
3096                 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3097         },
3098 };
3099 
3100 static const struct panel_desc arm_rtsm = {
3101         .modes = arm_rtsm_mode,
3102         .num_modes = 1,
3103         .bpc = 8,
3104         .size = {
3105                 .width = 400,
3106                 .height = 300,
3107         },
3108         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3109 };
3110 
3111 static const struct of_device_id platform_of_match[] = {
3112         {
3113                 .compatible = "ampire,am-480272h3tmqw-t01h",
3114                 .data = &ampire_am_480272h3tmqw_t01h,
3115         }, {
3116                 .compatible = "ampire,am800480r3tmqwa1h",
3117                 .data = &ampire_am800480r3tmqwa1h,
3118         }, {
3119                 .compatible = "arm,rtsm-display",
3120                 .data = &arm_rtsm,
3121         }, {
3122                 .compatible = "armadeus,st0700-adapt",
3123                 .data = &armadeus_st0700_adapt,
3124         }, {
3125                 .compatible = "auo,b101aw03",
3126                 .data = &auo_b101aw03,
3127         }, {
3128                 .compatible = "auo,b101ean01",
3129                 .data = &auo_b101ean01,
3130         }, {
3131                 .compatible = "auo,b101xtn01",
3132                 .data = &auo_b101xtn01,
3133         }, {
3134                 .compatible = "auo,b116xw03",
3135                 .data = &auo_b116xw03,
3136         }, {
3137                 .compatible = "auo,b133htn01",
3138                 .data = &auo_b133htn01,
3139         }, {
3140                 .compatible = "auo,b133xtn01",
3141                 .data = &auo_b133xtn01,
3142         }, {
3143                 .compatible = "auo,g070vvn01",
3144                 .data = &auo_g070vvn01,
3145         }, {
3146                 .compatible = "auo,g101evn010",
3147                 .data = &auo_g101evn010,
3148         }, {
3149                 .compatible = "auo,g104sn02",
3150                 .data = &auo_g104sn02,
3151         }, {
3152                 .compatible = "auo,g133han01",
3153                 .data = &auo_g133han01,
3154         }, {
3155                 .compatible = "auo,g185han01",
3156                 .data = &auo_g185han01,
3157         }, {
3158                 .compatible = "auo,p320hvn03",
3159                 .data = &auo_p320hvn03,
3160         }, {
3161                 .compatible = "auo,t215hvn01",
3162                 .data = &auo_t215hvn01,
3163         }, {
3164                 .compatible = "avic,tm070ddh03",
3165                 .data = &avic_tm070ddh03,
3166         }, {
3167                 .compatible = "bananapi,s070wv20-ct16",
3168                 .data = &bananapi_s070wv20_ct16,
3169         }, {
3170                 .compatible = "boe,hv070wsa-100",
3171                 .data = &boe_hv070wsa
3172         }, {
3173                 .compatible = "boe,nv101wxmn51",
3174                 .data = &boe_nv101wxmn51,
3175         }, {
3176                 .compatible = "cdtech,s043wq26h-ct7",
3177                 .data = &cdtech_s043wq26h_ct7,
3178         }, {
3179                 .compatible = "cdtech,s070wv95-ct16",
3180                 .data = &cdtech_s070wv95_ct16,
3181         }, {
3182                 .compatible = "chunghwa,claa070wp03xg",
3183                 .data = &chunghwa_claa070wp03xg,
3184         }, {
3185                 .compatible = "chunghwa,claa101wa01a",
3186                 .data = &chunghwa_claa101wa01a
3187         }, {
3188                 .compatible = "chunghwa,claa101wb01",
3189                 .data = &chunghwa_claa101wb01
3190         }, {
3191                 .compatible = "dataimage,scf0700c48ggu18",
3192                 .data = &dataimage_scf0700c48ggu18,
3193         }, {
3194                 .compatible = "dlc,dlc0700yzg-1",
3195                 .data = &dlc_dlc0700yzg_1,
3196         }, {
3197                 .compatible = "dlc,dlc1010gig",
3198                 .data = &dlc_dlc1010gig,
3199         }, {
3200                 .compatible = "edt,et035012dm6",
3201                 .data = &edt_et035012dm6,
3202         }, {
3203                 .compatible = "edt,etm0430g0dh6",
3204                 .data = &edt_etm0430g0dh6,
3205         }, {
3206                 .compatible = "edt,et057090dhu",
3207                 .data = &edt_et057090dhu,
3208         }, {
3209                 .compatible = "edt,et070080dh6",
3210                 .data = &edt_etm0700g0dh6,
3211         }, {
3212                 .compatible = "edt,etm0700g0dh6",
3213                 .data = &edt_etm0700g0dh6,
3214         }, {
3215                 .compatible = "edt,etm0700g0bdh6",
3216                 .data = &edt_etm0700g0bdh6,
3217         }, {
3218                 .compatible = "edt,etm0700g0edh6",
3219                 .data = &edt_etm0700g0bdh6,
3220         }, {
3221                 .compatible = "evervision,vgg804821",
3222                 .data = &evervision_vgg804821,
3223         }, {
3224                 .compatible = "foxlink,fl500wvr00-a0t",
3225                 .data = &foxlink_fl500wvr00_a0t,
3226         }, {
3227                 .compatible = "friendlyarm,hd702e",
3228                 .data = &friendlyarm_hd702e,
3229         }, {
3230                 .compatible = "giantplus,gpg482739qs5",
3231                 .data = &giantplus_gpg482739qs5
3232         }, {
3233                 .compatible = "giantplus,gpm940b0",
3234                 .data = &giantplus_gpm940b0,
3235         }, {
3236                 .compatible = "hannstar,hsd070pww1",
3237                 .data = &hannstar_hsd070pww1,
3238         }, {
3239                 .compatible = "hannstar,hsd100pxn1",
3240                 .data = &hannstar_hsd100pxn1,
3241         }, {
3242                 .compatible = "hit,tx23d38vm0caa",
3243                 .data = &hitachi_tx23d38vm0caa
3244         }, {
3245                 .compatible = "innolux,at043tn24",
3246                 .data = &innolux_at043tn24,
3247         }, {
3248                 .compatible = "innolux,at070tn92",
3249                 .data = &innolux_at070tn92,
3250         }, {
3251                 .compatible = "innolux,g070y2-l01",
3252                 .data = &innolux_g070y2_l01,
3253         }, {
3254                 .compatible = "innolux,g101ice-l01",
3255                 .data = &innolux_g101ice_l01
3256         }, {
3257                 .compatible = "innolux,g121i1-l01",
3258                 .data = &innolux_g121i1_l01
3259         }, {
3260                 .compatible = "innolux,g121x1-l03",
3261                 .data = &innolux_g121x1_l03,
3262         }, {
3263                 .compatible = "innolux,n116bge",
3264                 .data = &innolux_n116bge,
3265         }, {
3266                 .compatible = "innolux,n156bge-l21",
3267                 .data = &innolux_n156bge_l21,
3268         }, {
3269                 .compatible = "innolux,p120zdg-bf1",
3270                 .data = &innolux_p120zdg_bf1,
3271         }, {
3272                 .compatible = "innolux,zj070na-01p",
3273                 .data = &innolux_zj070na_01p,
3274         }, {
3275                 .compatible = "koe,tx14d24vm1bpa",
3276                 .data = &koe_tx14d24vm1bpa,
3277         }, {
3278                 .compatible = "koe,tx31d200vm0baa",
3279                 .data = &koe_tx31d200vm0baa,
3280         }, {
3281                 .compatible = "kyo,tcg121xglp",
3282                 .data = &kyo_tcg121xglp,
3283         }, {
3284                 .compatible = "lemaker,bl035-rgb-002",
3285                 .data = &lemaker_bl035_rgb_002,
3286         }, {
3287                 .compatible = "lg,lb070wv8",
3288                 .data = &lg_lb070wv8,
3289         }, {
3290                 .compatible = "lg,lp079qx1-sp0v",
3291                 .data = &lg_lp079qx1_sp0v,
3292         }, {
3293                 .compatible = "lg,lp097qx1-spa1",
3294                 .data = &lg_lp097qx1_spa1,
3295         }, {
3296                 .compatible = "lg,lp120up1",
3297                 .data = &lg_lp120up1,
3298         }, {
3299                 .compatible = "lg,lp129qe",
3300                 .data = &lg_lp129qe,
3301         }, {
3302                 .compatible = "logicpd,type28",
3303                 .data = &logicpd_type_28,
3304         }, {
3305                 .compatible = "mitsubishi,aa070mc01-ca1",
3306                 .data = &mitsubishi_aa070mc01,
3307         }, {
3308                 .compatible = "nec,nl12880bc20-05",
3309                 .data = &nec_nl12880bc20_05,
3310         }, {
3311                 .compatible = "nec,nl4827hc19-05b",
3312                 .data = &nec_nl4827hc19_05b,
3313         }, {
3314                 .compatible = "netron-dy,e231732",
3315                 .data = &netron_dy_e231732,
3316         }, {
3317                 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3318                 .data = &newhaven_nhd_43_480272ef_atxl,
3319         }, {
3320                 .compatible = "nlt,nl192108ac18-02d",
3321                 .data = &nlt_nl192108ac18_02d,
3322         }, {
3323                 .compatible = "nvd,9128",
3324                 .data = &nvd_9128,
3325         }, {
3326                 .compatible = "okaya,rs800480t-7x0gp",
3327                 .data = &okaya_rs800480t_7x0gp,
3328         }, {
3329                 .compatible = "olimex,lcd-olinuxino-43-ts",
3330                 .data = &olimex_lcd_olinuxino_43ts,
3331         }, {
3332                 .compatible = "ontat,yx700wv03",
3333                 .data = &ontat_yx700wv03,
3334         }, {
3335                 .compatible = "ortustech,com37h3m05dtc",
3336                 .data = &ortustech_com37h3m,
3337         }, {
3338                 .compatible = "ortustech,com37h3m99dtc",
3339                 .data = &ortustech_com37h3m,
3340         }, {
3341                 .compatible = "ortustech,com43h4m85ulc",
3342                 .data = &ortustech_com43h4m85ulc,
3343         }, {
3344                 .compatible = "osddisplays,osd070t1718-19ts",
3345                 .data = &osddisplays_osd070t1718_19ts,
3346         }, {
3347                 .compatible = "pda,91-00156-a0",
3348                 .data = &pda_91_00156_a0,
3349         }, {
3350                 .compatible = "qiaodian,qd43003c0-40",
3351                 .data = &qd43003c0_40,
3352         }, {
3353                 .compatible = "rocktech,rk070er9427",
3354                 .data = &rocktech_rk070er9427,
3355         }, {
3356                 .compatible = "samsung,lsn122dl01-c01",
3357                 .data = &samsung_lsn122dl01_c01,
3358         }, {
3359                 .compatible = "samsung,ltn101nt05",
3360                 .data = &samsung_ltn101nt05,
3361         }, {
3362                 .compatible = "samsung,ltn140at29-301",
3363                 .data = &samsung_ltn140at29_301,
3364         }, {
3365                 .compatible = "sharp,ld-d5116z01b",
3366                 .data = &sharp_ld_d5116z01b,
3367         }, {
3368                 .compatible = "sharp,lq035q7db03",
3369                 .data = &sharp_lq035q7db03,
3370         }, {
3371                 .compatible = "sharp,lq070y3dg3b",
3372                 .data = &sharp_lq070y3dg3b,
3373         }, {
3374                 .compatible = "sharp,lq101k1ly04",
3375                 .data = &sharp_lq101k1ly04,
3376         }, {
3377                 .compatible = "sharp,lq123p1jx31",
3378                 .data = &sharp_lq123p1jx31,
3379         }, {
3380                 .compatible = "sharp,lq150x1lg11",
3381                 .data = &sharp_lq150x1lg11,
3382         }, {
3383                 .compatible = "sharp,ls020b1dd01d",
3384                 .data = &sharp_ls020b1dd01d,
3385         }, {
3386                 .compatible = "shelly,sca07010-bfn-lnn",
3387                 .data = &shelly_sca07010_bfn_lnn,
3388         }, {
3389                 .compatible = "starry,kr122ea0sra",
3390                 .data = &starry_kr122ea0sra,
3391         }, {
3392                 .compatible = "tfc,s9700rtwv43tr-01b",
3393                 .data = &tfc_s9700rtwv43tr_01b,
3394         }, {
3395                 .compatible = "tianma,tm070jdhg30",
3396                 .data = &tianma_tm070jdhg30,
3397         }, {
3398                 .compatible = "tianma,tm070rvhg71",
3399                 .data = &tianma_tm070rvhg71,
3400         }, {
3401                 .compatible = "ti,nspire-cx-lcd-panel",
3402                 .data = &ti_nspire_cx_lcd_panel,
3403         }, {
3404                 .compatible = "ti,nspire-classic-lcd-panel",
3405                 .data = &ti_nspire_classic_lcd_panel,
3406         }, {
3407                 .compatible = "toshiba,lt089ac29000",
3408                 .data = &toshiba_lt089ac29000,
3409         }, {
3410                 .compatible = "tpk,f07a-0102",
3411                 .data = &tpk_f07a_0102,
3412         }, {
3413                 .compatible = "tpk,f10a-0102",
3414                 .data = &tpk_f10a_0102,
3415         }, {
3416                 .compatible = "urt,umsh-8596md-t",
3417                 .data = &urt_umsh_8596md_parallel,
3418         }, {
3419                 .compatible = "urt,umsh-8596md-1t",
3420                 .data = &urt_umsh_8596md_parallel,
3421         }, {
3422                 .compatible = "urt,umsh-8596md-7t",
3423                 .data = &urt_umsh_8596md_parallel,
3424         }, {
3425                 .compatible = "urt,umsh-8596md-11t",
3426                 .data = &urt_umsh_8596md_lvds,
3427         }, {
3428                 .compatible = "urt,umsh-8596md-19t",
3429                 .data = &urt_umsh_8596md_lvds,
3430         }, {
3431                 .compatible = "urt,umsh-8596md-20t",
3432                 .data = &urt_umsh_8596md_parallel,
3433         }, {
3434                 .compatible = "vxt,vl050-8048nt-c01",
3435                 .data = &vl050_8048nt_c01,
3436         }, {
3437                 .compatible = "winstar,wf35ltiacd",
3438                 .data = &winstar_wf35ltiacd,
3439         }, {
3440                 /* sentinel */
3441         }
3442 };
3443 MODULE_DEVICE_TABLE(of, platform_of_match);
3444 
3445 static int panel_simple_platform_probe(struct platform_device *pdev)
3446 {
3447         const struct of_device_id *id;
3448 
3449         id = of_match_node(platform_of_match, pdev->dev.of_node);
3450         if (!id)
3451                 return -ENODEV;
3452 
3453         return panel_simple_probe(&pdev->dev, id->data);
3454 }
3455 
3456 static int panel_simple_platform_remove(struct platform_device *pdev)
3457 {
3458         return panel_simple_remove(&pdev->dev);
3459 }
3460 
3461 static void panel_simple_platform_shutdown(struct platform_device *pdev)
3462 {
3463         panel_simple_shutdown(&pdev->dev);
3464 }
3465 
3466 static struct platform_driver panel_simple_platform_driver = {
3467         .driver = {
3468                 .name = "panel-simple",
3469                 .of_match_table = platform_of_match,
3470         },
3471         .probe = panel_simple_platform_probe,
3472         .remove = panel_simple_platform_remove,
3473         .shutdown = panel_simple_platform_shutdown,
3474 };
3475 
3476 struct panel_desc_dsi {
3477         struct panel_desc desc;
3478 
3479         unsigned long flags;
3480         enum mipi_dsi_pixel_format format;
3481         unsigned int lanes;
3482 };
3483 
3484 static const struct drm_display_mode auo_b080uan01_mode = {
3485         .clock = 154500,
3486         .hdisplay = 1200,
3487         .hsync_start = 1200 + 62,
3488         .hsync_end = 1200 + 62 + 4,
3489         .htotal = 1200 + 62 + 4 + 62,
3490         .vdisplay = 1920,
3491         .vsync_start = 1920 + 9,
3492         .vsync_end = 1920 + 9 + 2,
3493         .vtotal = 1920 + 9 + 2 + 8,
3494         .vrefresh = 60,
3495 };
3496 
3497 static const struct panel_desc_dsi auo_b080uan01 = {
3498         .desc = {
3499                 .modes = &auo_b080uan01_mode,
3500                 .num_modes = 1,
3501                 .bpc = 8,
3502                 .size = {
3503                         .width = 108,
3504                         .height = 272,
3505                 },
3506         },
3507         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3508         .format = MIPI_DSI_FMT_RGB888,
3509         .lanes = 4,
3510 };
3511 
3512 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3513         .clock = 160000,
3514         .hdisplay = 1200,
3515         .hsync_start = 1200 + 120,
3516         .hsync_end = 1200 + 120 + 20,
3517         .htotal = 1200 + 120 + 20 + 21,
3518         .vdisplay = 1920,
3519         .vsync_start = 1920 + 21,
3520         .vsync_end = 1920 + 21 + 3,
3521         .vtotal = 1920 + 21 + 3 + 18,
3522         .vrefresh = 60,
3523         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3524 };
3525 
3526 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3527         .desc = {
3528                 .modes = &boe_tv080wum_nl0_mode,
3529                 .num_modes = 1,
3530                 .size = {
3531                         .width = 107,
3532                         .height = 172,
3533                 },
3534         },
3535         .flags = MIPI_DSI_MODE_VIDEO |
3536                  MIPI_DSI_MODE_VIDEO_BURST |
3537                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3538         .format = MIPI_DSI_FMT_RGB888,
3539         .lanes = 4,
3540 };
3541 
3542 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3543         .clock = 71000,
3544         .hdisplay = 800,
3545         .hsync_start = 800 + 32,
3546         .hsync_end = 800 + 32 + 1,
3547         .htotal = 800 + 32 + 1 + 57,
3548         .vdisplay = 1280,
3549         .vsync_start = 1280 + 28,
3550         .vsync_end = 1280 + 28 + 1,
3551         .vtotal = 1280 + 28 + 1 + 14,
3552         .vrefresh = 60,
3553 };
3554 
3555 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3556         .desc = {
3557                 .modes = &lg_ld070wx3_sl01_mode,
3558                 .num_modes = 1,
3559                 .bpc = 8,
3560                 .size = {
3561                         .width = 94,
3562                         .height = 151,
3563                 },
3564         },
3565         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3566         .format = MIPI_DSI_FMT_RGB888,
3567         .lanes = 4,
3568 };
3569 
3570 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3571         .clock = 67000,
3572         .hdisplay = 720,
3573         .hsync_start = 720 + 12,
3574         .hsync_end = 720 + 12 + 4,
3575         .htotal = 720 + 12 + 4 + 112,
3576         .vdisplay = 1280,
3577         .vsync_start = 1280 + 8,
3578         .vsync_end = 1280 + 8 + 4,
3579         .vtotal = 1280 + 8 + 4 + 12,
3580         .vrefresh = 60,
3581 };
3582 
3583 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3584         .desc = {
3585                 .modes = &lg_lh500wx1_sd03_mode,
3586                 .num_modes = 1,
3587                 .bpc = 8,
3588                 .size = {
3589                         .width = 62,
3590                         .height = 110,
3591                 },
3592         },
3593         .flags = MIPI_DSI_MODE_VIDEO,
3594         .format = MIPI_DSI_FMT_RGB888,
3595         .lanes = 4,
3596 };
3597 
3598 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3599         .clock = 157200,
3600         .hdisplay = 1920,
3601         .hsync_start = 1920 + 154,
3602         .hsync_end = 1920 + 154 + 16,
3603         .htotal = 1920 + 154 + 16 + 32,
3604         .vdisplay = 1200,
3605         .vsync_start = 1200 + 17,
3606         .vsync_end = 1200 + 17 + 2,
3607         .vtotal = 1200 + 17 + 2 + 16,
3608         .vrefresh = 60,
3609 };
3610 
3611 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3612         .desc = {
3613                 .modes = &panasonic_vvx10f004b00_mode,
3614                 .num_modes = 1,
3615                 .bpc = 8,
3616                 .size = {
3617                         .width = 217,
3618                         .height = 136,
3619                 },
3620         },
3621         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3622                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
3623         .format = MIPI_DSI_FMT_RGB888,
3624         .lanes = 4,
3625 };
3626 
3627 static const struct drm_display_mode lg_acx467akm_7_mode = {
3628         .clock = 150000,
3629         .hdisplay = 1080,
3630         .hsync_start = 1080 + 2,
3631         .hsync_end = 1080 + 2 + 2,
3632         .htotal = 1080 + 2 + 2 + 2,
3633         .vdisplay = 1920,
3634         .vsync_start = 1920 + 2,
3635         .vsync_end = 1920 + 2 + 2,
3636         .vtotal = 1920 + 2 + 2 + 2,
3637         .vrefresh = 60,
3638 };
3639 
3640 static const struct panel_desc_dsi lg_acx467akm_7 = {
3641         .desc = {
3642                 .modes = &lg_acx467akm_7_mode,
3643                 .num_modes = 1,
3644                 .bpc = 8,
3645                 .size = {
3646                         .width = 62,
3647                         .height = 110,
3648                 },
3649         },
3650         .flags = 0,
3651         .format = MIPI_DSI_FMT_RGB888,
3652         .lanes = 4,
3653 };
3654 
3655 static const struct drm_display_mode osd101t2045_53ts_mode = {
3656         .clock = 154500,
3657         .hdisplay = 1920,
3658         .hsync_start = 1920 + 112,
3659         .hsync_end = 1920 + 112 + 16,
3660         .htotal = 1920 + 112 + 16 + 32,
3661         .vdisplay = 1200,
3662         .vsync_start = 1200 + 16,
3663         .vsync_end = 1200 + 16 + 2,
3664         .vtotal = 1200 + 16 + 2 + 16,
3665         .vrefresh = 60,
3666         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3667 };
3668 
3669 static const struct panel_desc_dsi osd101t2045_53ts = {
3670         .desc = {
3671                 .modes = &osd101t2045_53ts_mode,
3672                 .num_modes = 1,
3673                 .bpc = 8,
3674                 .size = {
3675                         .width = 217,
3676                         .height = 136,
3677                 },
3678         },
3679         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3680                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3681                  MIPI_DSI_MODE_EOT_PACKET,
3682         .format = MIPI_DSI_FMT_RGB888,
3683         .lanes = 4,
3684 };
3685 
3686 static const struct of_device_id dsi_of_match[] = {
3687         {
3688                 .compatible = "auo,b080uan01",
3689                 .data = &auo_b080uan01
3690         }, {
3691                 .compatible = "boe,tv080wum-nl0",
3692                 .data = &boe_tv080wum_nl0
3693         }, {
3694                 .compatible = "lg,ld070wx3-sl01",
3695                 .data = &lg_ld070wx3_sl01
3696         }, {
3697                 .compatible = "lg,lh500wx1-sd03",
3698                 .data = &lg_lh500wx1_sd03
3699         }, {
3700                 .compatible = "panasonic,vvx10f004b00",
3701                 .data = &panasonic_vvx10f004b00
3702         }, {
3703                 .compatible = "lg,acx467akm-7",
3704                 .data = &lg_acx467akm_7
3705         }, {
3706                 .compatible = "osddisplays,osd101t2045-53ts",
3707                 .data = &osd101t2045_53ts
3708         }, {
3709                 /* sentinel */
3710         }
3711 };
3712 MODULE_DEVICE_TABLE(of, dsi_of_match);
3713 
3714 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3715 {
3716         const struct panel_desc_dsi *desc;
3717         const struct of_device_id *id;
3718         int err;
3719 
3720         id = of_match_node(dsi_of_match, dsi->dev.of_node);
3721         if (!id)
3722                 return -ENODEV;
3723 
3724         desc = id->data;
3725 
3726         err = panel_simple_probe(&dsi->dev, &desc->desc);
3727         if (err < 0)
3728                 return err;
3729 
3730         dsi->mode_flags = desc->flags;
3731         dsi->format = desc->format;
3732         dsi->lanes = desc->lanes;
3733 
3734         err = mipi_dsi_attach(dsi);
3735         if (err) {
3736                 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3737 
3738                 drm_panel_remove(&panel->base);
3739         }
3740 
3741         return err;
3742 }
3743 
3744 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3745 {
3746         int err;
3747 
3748         err = mipi_dsi_detach(dsi);
3749         if (err < 0)
3750                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3751 
3752         return panel_simple_remove(&dsi->dev);
3753 }
3754 
3755 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3756 {
3757         panel_simple_shutdown(&dsi->dev);
3758 }
3759 
3760 static struct mipi_dsi_driver panel_simple_dsi_driver = {
3761         .driver = {
3762                 .name = "panel-simple-dsi",
3763                 .of_match_table = dsi_of_match,
3764         },
3765         .probe = panel_simple_dsi_probe,
3766         .remove = panel_simple_dsi_remove,
3767         .shutdown = panel_simple_dsi_shutdown,
3768 };
3769 
3770 static int __init panel_simple_init(void)
3771 {
3772         int err;
3773 
3774         err = platform_driver_register(&panel_simple_platform_driver);
3775         if (err < 0)
3776                 return err;
3777 
3778         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3779                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3780                 if (err < 0)
3781                         return err;
3782         }
3783 
3784         return 0;
3785 }
3786 module_init(panel_simple_init);
3787 
3788 static void __exit panel_simple_exit(void)
3789 {
3790         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3791                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3792 
3793         platform_driver_unregister(&panel_simple_platform_driver);
3794 }
3795 module_exit(panel_simple_exit);
3796 
3797 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3798 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3799 MODULE_LICENSE("GPL and additional rights");

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