root/drivers/gpu/drm/nouveau/nvkm/engine/disp/basenv50.c

DEFINITIONS

1. nv50_disp_base_new_
2. nv50_disp_base_new

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "channv50.h"
  25 #include "head.h"
  26 
  27 #include <core/client.h>
  28 
  29 #include <nvif/cl507c.h>
  30 #include <nvif/unpack.h>
  31 
  32 int
  33 nv50_disp_base_new_(const struct nv50_disp_chan_func *func,
  34                     const struct nv50_disp_chan_mthd *mthd,
  35                     struct nv50_disp *disp, int chid,
  36                     const struct nvkm_oclass *oclass, void *argv, u32 argc,
  37                     struct nvkm_object **pobject)
  38 {
  39         union {
  40                 struct nv50_disp_base_channel_dma_v0 v0;
  41         } *args = argv;
  42         struct nvkm_object *parent = oclass->parent;
  43         int head, ret = -ENOSYS;
  44         u64 push;
  45 
  46         nvif_ioctl(parent, "create disp base channel dma size %d\n", argc);
  47         if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
  48                 nvif_ioctl(parent, "create disp base channel dma vers %d "
  49                                    "pushbuf %016llx head %d\n",
  50                            args->v0.version, args->v0.pushbuf, args->v0.head);
  51                 if (!nvkm_head_find(&disp->base, args->v0.head))
  52                         return -EINVAL;
  53                 push = args->v0.pushbuf;
  54                 head = args->v0.head;
  55         } else
  56                 return ret;
  57 
  58         return nv50_disp_dmac_new_(func, mthd, disp, chid + head,
  59                                    head, push, oclass, pobject);
  60 }
  61 
  62 static const struct nv50_disp_mthd_list
  63 nv50_disp_base_mthd_base = {
  64         .mthd = 0x0000,
  65         .addr = 0x000000,
  66         .data = {
  67                 { 0x0080, 0x000000 },
  68                 { 0x0084, 0x0008c4 },
  69                 { 0x0088, 0x0008d0 },
  70                 { 0x008c, 0x0008dc },
  71                 { 0x0090, 0x0008e4 },
  72                 { 0x0094, 0x610884 },
  73                 { 0x00a0, 0x6108a0 },
  74                 { 0x00a4, 0x610878 },
  75                 { 0x00c0, 0x61086c },
  76                 { 0x00e0, 0x610858 },
  77                 { 0x00e4, 0x610860 },
  78                 { 0x00e8, 0x6108ac },
  79                 { 0x00ec, 0x6108b4 },
  80                 { 0x0100, 0x610894 },
  81                 { 0x0110, 0x6108bc },
  82                 { 0x0114, 0x61088c },
  83                 {}
  84         }
  85 };
  86 
  87 const struct nv50_disp_mthd_list
  88 nv50_disp_base_mthd_image = {
  89         .mthd = 0x0400,
  90         .addr = 0x000000,
  91         .data = {
  92                 { 0x0800, 0x6108f0 },
  93                 { 0x0804, 0x6108fc },
  94                 { 0x0808, 0x61090c },
  95                 { 0x080c, 0x610914 },
  96                 { 0x0810, 0x610904 },
  97                 {}
  98         }
  99 };
 100 
 101 static const struct nv50_disp_chan_mthd
 102 nv50_disp_base_mthd = {
 103         .name = "Base",
 104         .addr = 0x000540,
 105         .prev = 0x000004,
 106         .data = {
 107                 { "Global", 1, &nv50_disp_base_mthd_base },
 108                 {  "Image", 2, &nv50_disp_base_mthd_image },
 109                 {}
 110         }
 111 };
 112 
 113 int
 114 nv50_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
 115                    struct nv50_disp *disp, struct nvkm_object **pobject)
 116 {
 117         return nv50_disp_base_new_(&nv50_disp_dmac_func, &nv50_disp_base_mthd,
 118                                    disp, 1, oclass, argv, argc, pobject);
 119 }