root/drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c

DEFINITIONS

1. gv100_disp_curs_idle
2. gv100_disp_curs_intr
3. gv100_disp_curs_fini
4. gv100_disp_curs_init
5. gv100_disp_curs_new

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "channv50.h"
  23 
  24 #include <subdev/timer.h>
  25 
  26 static int
  27 gv100_disp_curs_idle(struct nv50_disp_chan *chan)
  28 {
  29         struct nvkm_device *device = chan->disp->base.engine.subdev.device;
  30         const u32 soff = (chan->chid.ctrl - 1) * 0x04;
  31         nvkm_msec(device, 2000,
  32                 u32 stat = nvkm_rd32(device, 0x610664 + soff);
  33                 if ((stat & 0x00070000) == 0x00040000)
  34                         return 0;
  35         );
  36         return -EBUSY;
  37 }
  38 
  39 static void
  40 gv100_disp_curs_intr(struct nv50_disp_chan *chan, bool en)
  41 {
  42         struct nvkm_device *device = chan->disp->base.engine.subdev.device;
  43         const u32 mask = 0x00010000 << chan->head;
  44         const u32 data = en ? mask : 0;
  45         nvkm_mask(device, 0x611dac, mask, data);
  46 }
  47 
  48 static void
  49 gv100_disp_curs_fini(struct nv50_disp_chan *chan)
  50 {
  51         struct nvkm_device *device = chan->disp->base.engine.subdev.device;
  52         const u32 hoff = chan->chid.ctrl * 4;
  53         nvkm_mask(device, 0x6104e0 + hoff, 0x00000010, 0x00000010);
  54         gv100_disp_curs_idle(chan);
  55         nvkm_mask(device, 0x6104e0 + hoff, 0x00000001, 0x00000000);
  56 }
  57 
  58 static int
  59 gv100_disp_curs_init(struct nv50_disp_chan *chan)
  60 {
  61         struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
  62         struct nvkm_device *device = subdev->device;
  63         nvkm_wr32(device, 0x6104e0 + chan->chid.ctrl * 4, 0x00000001);
  64         return gv100_disp_curs_idle(chan);
  65 }
  66 
  67 static const struct nv50_disp_chan_func
  68 gv100_disp_curs = {
  69         .init = gv100_disp_curs_init,
  70         .fini = gv100_disp_curs_fini,
  71         .intr = gv100_disp_curs_intr,
  72         .user = gv100_disp_chan_user,
  73 };
  74 
  75 int
  76 gv100_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
  77                     struct nv50_disp *disp, struct nvkm_object **pobject)
  78 {
  79         return nv50_disp_curs_new_(&gv100_disp_curs, disp, 73, 73,
  80                                    oclass, argv, argc, pobject);
  81 }