root/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c

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DEFINITIONS

This source file includes following definitions.
  1. nv04_disp_root
  2. nv04_disp_intr
  3. nv04_disp_new

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25 #include "head.h"
  26 
  27 static const struct nvkm_disp_oclass *
  28 nv04_disp_root(struct nvkm_disp *disp)
  29 {
  30         return &nv04_disp_root_oclass;
  31 }
  32 
  33 static void
  34 nv04_disp_intr(struct nvkm_disp *disp)
  35 {
  36         struct nvkm_subdev *subdev = &disp->engine.subdev;
  37         struct nvkm_device *device = subdev->device;
  38         u32 crtc0 = nvkm_rd32(device, 0x600100);
  39         u32 crtc1 = nvkm_rd32(device, 0x602100);
  40         u32 pvideo;
  41 
  42         if (crtc0 & 0x00000001) {
  43                 nvkm_disp_vblank(disp, 0);
  44                 nvkm_wr32(device, 0x600100, 0x00000001);
  45         }
  46 
  47         if (crtc1 & 0x00000001) {
  48                 nvkm_disp_vblank(disp, 1);
  49                 nvkm_wr32(device, 0x602100, 0x00000001);
  50         }
  51 
  52         if (device->chipset >= 0x10 && device->chipset <= 0x40) {
  53                 pvideo = nvkm_rd32(device, 0x8100);
  54                 if (pvideo & ~0x11)
  55                         nvkm_info(subdev, "PVIDEO intr: %08x\n", pvideo);
  56                 nvkm_wr32(device, 0x8100, pvideo);
  57         }
  58 }
  59 
  60 static const struct nvkm_disp_func
  61 nv04_disp = {
  62         .intr = nv04_disp_intr,
  63         .root = nv04_disp_root,
  64 };
  65 
  66 int
  67 nv04_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
  68 {
  69         int ret, i;
  70 
  71         ret = nvkm_disp_new_(&nv04_disp, device, index, pdisp);
  72         if (ret)
  73                 return ret;
  74 
  75         for (i = 0; i < 2; i++) {
  76                 ret = nv04_head_new(*pdisp, i);
  77                 if (ret)
  78                         return ret;
  79         }
  80 
  81         return 0;
  82 }

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