drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
nv50_disp_core_new_
nv50_disp_core_fini
nv50_disp_core_init
nv50_disp_core_new
   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "channv50.h"
  25 
  26 #include <core/client.h>
  27 #include <subdev/timer.h>
  28 
  29 #include <nvif/cl507d.h>
  30 #include <nvif/unpack.h>
  31 
  32 int
  33 nv50_disp_core_new_(const struct nv50_disp_chan_func *func,
  34                     const struct nv50_disp_chan_mthd *mthd,
  35                     struct nv50_disp *disp, int chid,
  36                     const struct nvkm_oclass *oclass, void *argv, u32 argc,
  37                     struct nvkm_object **pobject)
  38 {
  39         union {
  40                 struct nv50_disp_core_channel_dma_v0 v0;
  41         } *args = argv;
  42         struct nvkm_object *parent = oclass->parent;
  43         u64 push;
  44         int ret = -ENOSYS;
  45 
  46         nvif_ioctl(parent, "create disp core channel dma size %d\n", argc);
  47         if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
  48                 nvif_ioctl(parent, "create disp core channel dma vers %d "
  49                                    "pushbuf %016llx\n",
  50                            args->v0.version, args->v0.pushbuf);
  51                 push = args->v0.pushbuf;
  52         } else
  53                 return ret;
  54 
  55         return nv50_disp_dmac_new_(func, mthd, disp, chid, 0,
  56                                    push, oclass, pobject);
  57 }
  58 
  59 const struct nv50_disp_mthd_list
  60 nv50_disp_core_mthd_base = {
  61         .mthd = 0x0000,
  62         .addr = 0x000000,
  63         .data = {
  64                 { 0x0080, 0x000000 },
  65                 { 0x0084, 0x610bb8 },
  66                 { 0x0088, 0x610b9c },
  67                 { 0x008c, 0x000000 },
  68                 {}
  69         }
  70 };
  71 
  72 static const struct nv50_disp_mthd_list
  73 nv50_disp_core_mthd_dac = {
  74         .mthd = 0x0080,
  75         .addr = 0x000008,
  76         .data = {
  77                 { 0x0400, 0x610b58 },
  78                 { 0x0404, 0x610bdc },
  79                 { 0x0420, 0x610828 },
  80                 {}
  81         }
  82 };
  83 
  84 const struct nv50_disp_mthd_list
  85 nv50_disp_core_mthd_sor = {
  86         .mthd = 0x0040,
  87         .addr = 0x000008,
  88         .data = {
  89                 { 0x0600, 0x610b70 },
  90                 {}
  91         }
  92 };
  93 
  94 const struct nv50_disp_mthd_list
  95 nv50_disp_core_mthd_pior = {
  96         .mthd = 0x0040,
  97         .addr = 0x000008,
  98         .data = {
  99                 { 0x0700, 0x610b80 },
 100                 {}
 101         }
 102 };
 103 
 104 static const struct nv50_disp_mthd_list
 105 nv50_disp_core_mthd_head = {
 106         .mthd = 0x0400,
 107         .addr = 0x000540,
 108         .data = {
 109                 { 0x0800, 0x610ad8 },
 110                 { 0x0804, 0x610ad0 },
 111                 { 0x0808, 0x610a48 },
 112                 { 0x080c, 0x610a78 },
 113                 { 0x0810, 0x610ac0 },
 114                 { 0x0814, 0x610af8 },
 115                 { 0x0818, 0x610b00 },
 116                 { 0x081c, 0x610ae8 },
 117                 { 0x0820, 0x610af0 },
 118                 { 0x0824, 0x610b08 },
 119                 { 0x0828, 0x610b10 },
 120                 { 0x082c, 0x610a68 },
 121                 { 0x0830, 0x610a60 },
 122                 { 0x0834, 0x000000 },
 123                 { 0x0838, 0x610a40 },
 124                 { 0x0840, 0x610a24 },
 125                 { 0x0844, 0x610a2c },
 126                 { 0x0848, 0x610aa8 },
 127                 { 0x084c, 0x610ab0 },
 128                 { 0x0860, 0x610a84 },
 129                 { 0x0864, 0x610a90 },
 130                 { 0x0868, 0x610b18 },
 131                 { 0x086c, 0x610b20 },
 132                 { 0x0870, 0x610ac8 },
 133                 { 0x0874, 0x610a38 },
 134                 { 0x0880, 0x610a58 },
 135                 { 0x0884, 0x610a9c },
 136                 { 0x08a0, 0x610a70 },
 137                 { 0x08a4, 0x610a50 },
 138                 { 0x08a8, 0x610ae0 },
 139                 { 0x08c0, 0x610b28 },
 140                 { 0x08c4, 0x610b30 },
 141                 { 0x08c8, 0x610b40 },
 142                 { 0x08d4, 0x610b38 },
 143                 { 0x08d8, 0x610b48 },
 144                 { 0x08dc, 0x610b50 },
 145                 { 0x0900, 0x610a18 },
 146                 { 0x0904, 0x610ab8 },
 147                 {}
 148         }
 149 };
 150 
 151 static const struct nv50_disp_chan_mthd
 152 nv50_disp_core_mthd = {
 153         .name = "Core",
 154         .addr = 0x000000,
 155         .prev = 0x000004,
 156         .data = {
 157                 { "Global", 1, &nv50_disp_core_mthd_base },
 158                 {    "DAC", 3, &nv50_disp_core_mthd_dac  },
 159                 {    "SOR", 2, &nv50_disp_core_mthd_sor  },
 160                 {   "PIOR", 3, &nv50_disp_core_mthd_pior },
 161                 {   "HEAD", 2, &nv50_disp_core_mthd_head },
 162                 {}
 163         }
 164 };
 165 
 166 static void
 167 nv50_disp_core_fini(struct nv50_disp_chan *chan)
 168 {
 169         struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
 170         struct nvkm_device *device = subdev->device;
 171 
 172         /* deactivate channel */
 173         nvkm_mask(device, 0x610200, 0x00000010, 0x00000000);
 174         nvkm_mask(device, 0x610200, 0x00000003, 0x00000000);
 175         if (nvkm_msec(device, 2000,
 176                 if (!(nvkm_rd32(device, 0x610200) & 0x001e0000))
 177                         break;
 178         ) < 0) {
 179                 nvkm_error(subdev, "core fini: %08x\n",
 180                            nvkm_rd32(device, 0x610200));
 181         }
 182 }
 183 
 184 static int
 185 nv50_disp_core_init(struct nv50_disp_chan *chan)
 186 {
 187         struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
 188         struct nvkm_device *device = subdev->device;
 189 
 190         /* attempt to unstick channel from some unknown state */
 191         if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000)
 192                 nvkm_mask(device, 0x610200, 0x00800000, 0x00800000);
 193         if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000)
 194                 nvkm_mask(device, 0x610200, 0x00600000, 0x00600000);
 195 
 196         /* initialise channel for dma command submission */
 197         nvkm_wr32(device, 0x610204, chan->push);
 198         nvkm_wr32(device, 0x610208, 0x00010000);
 199         nvkm_wr32(device, 0x61020c, 0x00000000);
 200         nvkm_mask(device, 0x610200, 0x00000010, 0x00000010);
 201         nvkm_wr32(device, 0x640000, 0x00000000);
 202         nvkm_wr32(device, 0x610200, 0x01000013);
 203 
 204         /* wait for it to go inactive */
 205         if (nvkm_msec(device, 2000,
 206                 if (!(nvkm_rd32(device, 0x610200) & 0x80000000))
 207                         break;
 208         ) < 0) {
 209                 nvkm_error(subdev, "core init: %08x\n",
 210                            nvkm_rd32(device, 0x610200));
 211                 return -EBUSY;
 212         }
 213 
 214         return 0;
 215 }
 216 
 217 const struct nv50_disp_chan_func
 218 nv50_disp_core_func = {
 219         .init = nv50_disp_core_init,
 220         .fini = nv50_disp_core_fini,
 221         .intr = nv50_disp_chan_intr,
 222         .user = nv50_disp_chan_user,
 223         .bind = nv50_disp_dmac_bind,
 224 };
 225 
 226 int
 227 nv50_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
 228                    struct nv50_disp *disp, struct nvkm_object **pobject)
 229 {
 230         return nv50_disp_core_new_(&nv50_disp_core_func, &nv50_disp_core_mthd,
 231                                    disp, 0, oclass, argv, argc, pobject);
 232 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c

DEFINITIONS
