This source file includes following definitions.
- gt215_hdmi_ctrl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 #include "hdmi.h"
25
26 void
27 gt215_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet,
28 u8 rekey, u8 *avi, u8 avi_size, u8 *vendor, u8 vendor_size)
29 {
30 struct nvkm_device *device = ior->disp->engine.subdev.device;
31 const u32 ctrl = 0x40000000 * enable |
32 0x1f000000 |
33 max_ac_packet << 16 |
34 rekey;
35 const u32 soff = nv50_ior_base(ior);
36 struct packed_hdmi_infoframe avi_infoframe;
37 struct packed_hdmi_infoframe vendor_infoframe;
38
39 pack_hdmi_infoframe(&avi_infoframe, avi, avi_size);
40 pack_hdmi_infoframe(&vendor_infoframe, vendor, vendor_size);
41
42 if (!(ctrl & 0x40000000)) {
43 nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000);
44 nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000);
45 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
46 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
47 return;
48 }
49
50
51 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
52 if (avi_size) {
53 nvkm_wr32(device, 0x61c528 + soff, avi_infoframe.header);
54 nvkm_wr32(device, 0x61c52c + soff, avi_infoframe.subpack0_low);
55 nvkm_wr32(device, 0x61c530 + soff, avi_infoframe.subpack0_high);
56 nvkm_wr32(device, 0x61c534 + soff, avi_infoframe.subpack1_low);
57 nvkm_wr32(device, 0x61c538 + soff, avi_infoframe.subpack1_high);
58 nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001);
59 }
60
61
62 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
63 nvkm_wr32(device, 0x61c508 + soff, 0x000a0184);
64 nvkm_wr32(device, 0x61c50c + soff, 0x00000071);
65 nvkm_wr32(device, 0x61c510 + soff, 0x00000000);
66 nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000001);
67
68
69 nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010000);
70 if (vendor_size) {
71 nvkm_wr32(device, 0x61c544 + soff, vendor_infoframe.header);
72 nvkm_wr32(device, 0x61c548 + soff, vendor_infoframe.subpack0_low);
73 nvkm_wr32(device, 0x61c54c + soff, vendor_infoframe.subpack0_high);
74
75
76
77 nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010001);
78 }
79
80 nvkm_mask(device, 0x61c5d0 + soff, 0x00070001, 0x00010001);
81 nvkm_mask(device, 0x61c568 + soff, 0x00010101, 0x00000000);
82 nvkm_mask(device, 0x61c578 + soff, 0x80000000, 0x80000000);
83
84
85 nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000);
86 nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000);
87 nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000);
88
89
90 nvkm_mask(device, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
91 }