root/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c

DEFINITIONS

1. gp100_gr_zbc_clear_color
2. gp100_gr_zbc_clear_depth
3. gp100_gr_init_shader_exceptions
4. gp100_gr_init_419c9c
5. gp100_gr_init_fecs_exceptions
6. gp100_gr_init_rop_active_fbps
7. gp100_gr_new

   1 /*
   2  * Copyright 2016 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24 #include "gf100.h"
  25 #include "ctxgf100.h"
  26 
  27 #include <nvif/class.h>
  28 
  29 /*******************************************************************************
  30  * PGRAPH engine/subdev functions
  31  ******************************************************************************/
  32 void
  33 gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
  34 {
  35         struct nvkm_device *device = gr->base.engine.subdev.device;
  36         const int znum =  zbc - 1;
  37         const u32 zoff = znum * 4;
  38 
  39         if (gr->zbc_color[zbc].format) {
  40                 nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]);
  41                 nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]);
  42                 nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]);
  43                 nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]);
  44         }
  45 
  46         nvkm_mask(device, 0x418100 + ((znum / 4) * 4),
  47                           0x0000007f << ((znum % 4) * 7),
  48                           gr->zbc_color[zbc].format << ((znum % 4) * 7));
  49 }
  50 
  51 void
  52 gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
  53 {
  54         struct nvkm_device *device = gr->base.engine.subdev.device;
  55         const int znum =  zbc - 1;
  56         const u32 zoff = znum * 4;
  57 
  58         if (gr->zbc_depth[zbc].format)
  59                 nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds);
  60         nvkm_mask(device, 0x41814c + ((znum / 4) * 4),
  61                           0x0000007f << ((znum % 4) * 7),
  62                           gr->zbc_depth[zbc].format << ((znum % 4) * 7));
  63 }
  64 
  65 static const struct gf100_gr_func_zbc
  66 gp100_gr_zbc = {
  67         .clear_color = gp100_gr_zbc_clear_color,
  68         .clear_depth = gp100_gr_zbc_clear_depth,
  69 };
  70 
  71 void
  72 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
  73 {
  74         struct nvkm_device *device = gr->base.engine.subdev.device;
  75         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
  76         nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
  77 }
  78 
  79 static void
  80 gp100_gr_init_419c9c(struct gf100_gr *gr)
  81 {
  82         struct nvkm_device *device = gr->base.engine.subdev.device;
  83         nvkm_mask(device, 0x419c9c, 0x00010000, 0x00010000);
  84         nvkm_mask(device, 0x419c9c, 0x00020000, 0x00020000);
  85 }
  86 
  87 void
  88 gp100_gr_init_fecs_exceptions(struct gf100_gr *gr)
  89 {
  90         nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000f0002);
  91 }
  92 
  93 void
  94 gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
  95 {
  96         struct nvkm_device *device = gr->base.engine.subdev.device;
  97         /*XXX: otherwise identical to gm200 aside from mask.. do everywhere? */
  98         const u32 fbp_count = nvkm_rd32(device, 0x12006c) & 0x0000000f;
  99         nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
 100         nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
 101 }
 102 
 103 static const struct gf100_gr_func
 104 gp100_gr = {
 105         .oneinit_tiles = gm200_gr_oneinit_tiles,
 106         .oneinit_sm_id = gm200_gr_oneinit_sm_id,
 107         .init = gf100_gr_init,
 108         .init_gpc_mmu = gm200_gr_init_gpc_mmu,
 109         .init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
 110         .init_zcull = gf117_gr_init_zcull,
 111         .init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
 112         .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
 113         .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
 114         .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
 115         .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
 116         .init_419cc0 = gf100_gr_init_419cc0,
 117         .init_419c9c = gp100_gr_init_419c9c,
 118         .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
 119         .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
 120         .init_504430 = gm107_gr_init_504430,
 121         .init_shader_exceptions = gp100_gr_init_shader_exceptions,
 122         .trap_mp = gf100_gr_trap_mp,
 123         .rops = gm200_gr_rops,
 124         .gpc_nr = 6,
 125         .tpc_nr = 5,
 126         .ppc_nr = 2,
 127         .grctx = &gp100_grctx,
 128         .zbc = &gp100_gr_zbc,
 129         .sclass = {
 130                 { -1, -1, FERMI_TWOD_A },
 131                 { -1, -1, KEPLER_INLINE_TO_MEMORY_B },
 132                 { -1, -1, PASCAL_A, &gf100_fermi },
 133                 { -1, -1, PASCAL_COMPUTE_A },
 134                 {}
 135         }
 136 };
 137 
 138 int
 139 gp100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 140 {
 141         return gm200_gr_new_(&gp100_gr, device, index, pgr);
 142 }