This source file includes following definitions.
- gv100_grctx_generate_attrib
- gv100_grctx_generate_rop_mapping
- gv100_grctx_generate_r400088
- gv100_grctx_generate_sm_id
- gv100_grctx_generate_unkn
- gv100_grctx_unkn88c
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22 #include "ctxgf100.h"
23
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26
27
28 static const struct gf100_gr_init
29 gv100_grctx_init_sw_veid_bundle_init_0[] = {
30 { 0x00001000, 64, 0x00100000, 0x00000008 },
31 { 0x00000941, 64, 0x00100000, 0x00000000 },
32 { 0x0000097e, 64, 0x00100000, 0x00000000 },
33 { 0x0000097f, 64, 0x00100000, 0x00000100 },
34 { 0x0000035c, 64, 0x00100000, 0x00000000 },
35 { 0x0000035d, 64, 0x00100000, 0x00000000 },
36 { 0x00000a08, 64, 0x00100000, 0x00000000 },
37 { 0x00000a09, 64, 0x00100000, 0x00000000 },
38 { 0x00000a0a, 64, 0x00100000, 0x00000000 },
39 { 0x00000352, 64, 0x00100000, 0x00000000 },
40 { 0x00000353, 64, 0x00100000, 0x00000000 },
41 { 0x00000358, 64, 0x00100000, 0x00000000 },
42 { 0x00000359, 64, 0x00100000, 0x00000000 },
43 { 0x00000370, 64, 0x00100000, 0x00000000 },
44 { 0x00000371, 64, 0x00100000, 0x00000000 },
45 { 0x00000372, 64, 0x00100000, 0x000fffff },
46 { 0x00000366, 64, 0x00100000, 0x00000000 },
47 { 0x00000367, 64, 0x00100000, 0x00000000 },
48 { 0x00000368, 64, 0x00100000, 0x00000fff },
49 { 0x00000623, 64, 0x00100000, 0x00000000 },
50 { 0x00000624, 64, 0x00100000, 0x00000000 },
51 { 0x0001e100, 1, 0x00000001, 0x02000001 },
52 {}
53 };
54
55 static const struct gf100_gr_pack
56 gv100_grctx_pack_sw_veid_bundle_init[] = {
57 { gv100_grctx_init_sw_veid_bundle_init_0 },
58 {}
59 };
60
61 static void
62 gv100_grctx_generate_attrib(struct gf100_grctx *info)
63 {
64 struct gf100_gr *gr = info->gr;
65 const struct gf100_grctx_func *grctx = gr->func->grctx;
66 const u32 alpha = grctx->alpha_nr;
67 const u32 attrib = grctx->attrib_nr;
68 const u32 gfxp = grctx->gfxp_nr;
69 const int s = 12;
70 const int max_batches = 0xffff;
71 u32 size = grctx->alpha_nr_max * gr->tpc_total;
72 u32 ao = 0;
73 u32 bo = ao + size;
74 int gpc, ppc, b, n = 0;
75
76 size += grctx->gfxp_nr * gr->tpc_total;
77 size = ((size * 0x20) + 128) & ~127;
78 b = mmio_vram(info, size, (1 << s), false);
79
80 mmio_refn(info, 0x418810, 0x80000000, s, b);
81 mmio_refn(info, 0x419848, 0x10000000, s, b);
82 mmio_refn(info, 0x419c2c, 0x10000000, s, b);
83 mmio_refn(info, 0x419e00, 0x00000000, s, b);
84 mmio_wr32(info, 0x419e04, 0x80000000 | size >> 7);
85 mmio_wr32(info, 0x405830, attrib);
86 mmio_wr32(info, 0x40585c, alpha);
87 mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
88
89 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
90 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
91 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
92 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
93 const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc];
94 const u32 u = 0x418ea0 + (n * 0x04);
95 const u32 o = PPC_UNIT(gpc, ppc, 0);
96 if (!(gr->ppc_mask[gpc] & (1 << ppc)))
97 continue;
98 mmio_wr32(info, o + 0xc0, gs);
99 mmio_wr32(info, o + 0xf4, bo);
100 mmio_wr32(info, o + 0xf0, bs);
101 bo += gs;
102 mmio_wr32(info, o + 0xe4, as);
103 mmio_wr32(info, o + 0xf8, ao);
104 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
105 mmio_wr32(info, u, bs);
106 }
107 }
108
109 mmio_wr32(info, 0x4181e4, 0x00000100);
110 mmio_wr32(info, 0x41befc, 0x00000100);
111 }
112
113 static void
114 gv100_grctx_generate_rop_mapping(struct gf100_gr *gr)
115 {
116 struct nvkm_device *device = gr->base.engine.subdev.device;
117 u32 data;
118 int i, j;
119
120
121 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) |
122 gr->screen_tile_row_offset);
123 for (i = 0; i < 11; i++) {
124 for (data = 0, j = 0; j < 6; j++)
125 data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5);
126 nvkm_wr32(device, 0x418b08 + (i * 4), data);
127 nvkm_wr32(device, 0x41bf00 + (i * 4), data);
128 nvkm_wr32(device, 0x40780c + (i * 4), data);
129 }
130
131
132 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) |
133 gr->screen_tile_row_offset);
134 for (i = 0, j = 1; i < 5; i++, j += 4) {
135 u8 v19 = (1 << (j + 0)) % gr->tpc_total;
136 u8 v20 = (1 << (j + 1)) % gr->tpc_total;
137 u8 v21 = (1 << (j + 2)) % gr->tpc_total;
138 u8 v22 = (1 << (j + 3)) % gr->tpc_total;
139 nvkm_wr32(device, 0x41bfb0 + (i * 4), (v22 << 24) |
140 (v21 << 16) |
141 (v20 << 8) |
142 v19);
143 }
144
145
146 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) |
147 gr->screen_tile_row_offset);
148 }
149
150 static void
151 gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on)
152 {
153 struct nvkm_device *device = gr->base.engine.subdev.device;
154 nvkm_mask(device, 0x400088, 0x00060000, on ? 0x00060000 : 0x00000000);
155 }
156
157 static void
158 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
159 {
160 struct nvkm_device *device = gr->base.engine.subdev.device;
161 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm);
162 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm);
163 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm);
164 }
165
166 static void
167 gv100_grctx_generate_unkn(struct gf100_gr *gr)
168 {
169 struct nvkm_device *device = gr->base.engine.subdev.device;
170 nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010);
171 nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004);
172 nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000);
173 nvkm_mask(device, 0x405800, 0x08000000, 0x08000000);
174 nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008);
175 }
176
177 static void
178 gv100_grctx_unkn88c(struct gf100_gr *gr, bool on)
179 {
180 struct nvkm_device *device = gr->base.engine.subdev.device;
181 const u32 mask = 0x00000010, data = on ? mask : 0x00000000;
182 nvkm_mask(device, 0x40988c, mask, data);
183 nvkm_rd32(device, 0x40988c);
184 nvkm_mask(device, 0x41a88c, mask, data);
185 nvkm_rd32(device, 0x41a88c);
186 nvkm_mask(device, 0x408a14, mask, data);
187 nvkm_rd32(device, 0x408a14);
188 }
189
190 const struct gf100_grctx_func
191 gv100_grctx = {
192 .unkn88c = gv100_grctx_unkn88c,
193 .main = gf100_grctx_generate_main,
194 .unkn = gv100_grctx_generate_unkn,
195 .sw_veid_bundle_init = gv100_grctx_pack_sw_veid_bundle_init,
196 .bundle = gm107_grctx_generate_bundle,
197 .bundle_size = 0x3000,
198 .bundle_min_gpm_fifo_depth = 0x180,
199 .bundle_token_limit = 0x1680,
200 .pagepool = gp100_grctx_generate_pagepool,
201 .pagepool_size = 0x20000,
202 .attrib = gv100_grctx_generate_attrib,
203 .attrib_nr_max = 0x6c0,
204 .attrib_nr = 0x480,
205 .alpha_nr_max = 0xc00,
206 .alpha_nr = 0x800,
207 .gfxp_nr = 0xd10,
208 .sm_id = gv100_grctx_generate_sm_id,
209 .rop_mapping = gv100_grctx_generate_rop_mapping,
210 .dist_skip_table = gm200_grctx_generate_dist_skip_table,
211 .r406500 = gm200_grctx_generate_r406500,
212 .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
213 .smid_config = gp100_grctx_generate_smid_config,
214 .r400088 = gv100_grctx_generate_r400088,
215 };