drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c

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This source file includes following definitions.
gk20a_gr_av_to_init
gk20a_gr_aiv_to_init
gk20a_gr_av_to_method
gk20a_gr_wait_mem_scrubbing
gk20a_gr_set_hww_esr_report_mask
gk20a_gr_init
gk20a_gr_new
   1 /*
   2  * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "gf100.h"
  23 #include "ctxgf100.h"
  24 
  25 #include <subdev/timer.h>
  26 
  27 #include <nvif/class.h>
  28 
  29 struct gk20a_fw_av
  30 {
  31         u32 addr;
  32         u32 data;
  33 };
  34 
  35 int
  36 gk20a_gr_av_to_init(struct gf100_gr *gr, const char *fw_name,
  37                     struct gf100_gr_pack **ppack)
  38 {
  39         struct gf100_gr_fuc fuc;
  40         struct gf100_gr_init *init;
  41         struct gf100_gr_pack *pack;
  42         int nent;
  43         int ret;
  44         int i;
  45 
  46         ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
  47         if (ret)
  48                 return ret;
  49 
  50         nent = (fuc.size / sizeof(struct gk20a_fw_av));
  51         pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
  52         if (!pack) {
  53                 ret = -ENOMEM;
  54                 goto end;
  55         }
  56 
  57         init = (void *)(pack + 2);
  58         pack[0].init = init;
  59 
  60         for (i = 0; i < nent; i++) {
  61                 struct gf100_gr_init *ent = &init[i];
  62                 struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc.data)[i];
  63 
  64                 ent->addr = av->addr;
  65                 ent->data = av->data;
  66                 ent->count = 1;
  67                 ent->pitch = 1;
  68         }
  69 
  70         *ppack = pack;
  71 
  72 end:
  73         gf100_gr_dtor_fw(&fuc);
  74         return ret;
  75 }
  76 
  77 struct gk20a_fw_aiv
  78 {
  79         u32 addr;
  80         u32 index;
  81         u32 data;
  82 };
  83 
  84 int
  85 gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *fw_name,
  86                      struct gf100_gr_pack **ppack)
  87 {
  88         struct gf100_gr_fuc fuc;
  89         struct gf100_gr_init *init;
  90         struct gf100_gr_pack *pack;
  91         int nent;
  92         int ret;
  93         int i;
  94 
  95         ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
  96         if (ret)
  97                 return ret;
  98 
  99         nent = (fuc.size / sizeof(struct gk20a_fw_aiv));
 100         pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
 101         if (!pack) {
 102                 ret = -ENOMEM;
 103                 goto end;
 104         }
 105 
 106         init = (void *)(pack + 2);
 107         pack[0].init = init;
 108 
 109         for (i = 0; i < nent; i++) {
 110                 struct gf100_gr_init *ent = &init[i];
 111                 struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)fuc.data)[i];
 112 
 113                 ent->addr = av->addr;
 114                 ent->data = av->data;
 115                 ent->count = 1;
 116                 ent->pitch = 1;
 117         }
 118 
 119         *ppack = pack;
 120 
 121 end:
 122         gf100_gr_dtor_fw(&fuc);
 123         return ret;
 124 }
 125 
 126 int
 127 gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name,
 128                       struct gf100_gr_pack **ppack)
 129 {
 130         struct gf100_gr_fuc fuc;
 131         struct gf100_gr_init *init;
 132         struct gf100_gr_pack *pack;
 133         /* We don't suppose we will initialize more than 16 classes here... */
 134         static const unsigned int max_classes = 16;
 135         u32 classidx = 0, prevclass = 0;
 136         int nent;
 137         int ret;
 138         int i;
 139 
 140         ret = gf100_gr_ctor_fw(gr, fw_name, &fuc);
 141         if (ret)
 142                 return ret;
 143 
 144         nent = (fuc.size / sizeof(struct gk20a_fw_av));
 145 
 146         pack = vzalloc((sizeof(*pack) * (max_classes + 1)) +
 147                        (sizeof(*init) * (nent + max_classes + 1)));
 148         if (!pack) {
 149                 ret = -ENOMEM;
 150                 goto end;
 151         }
 152 
 153         init = (void *)(pack + max_classes + 1);
 154 
 155         for (i = 0; i < nent; i++, init++) {
 156                 struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc.data)[i];
 157                 u32 class = av->addr & 0xffff;
 158                 u32 addr = (av->addr & 0xffff0000) >> 14;
 159 
 160                 if (prevclass != class) {
 161                         if (prevclass) /* Add terminator to the method list. */
 162                                 init++;
 163                         pack[classidx].init = init;
 164                         pack[classidx].type = class;
 165                         prevclass = class;
 166                         if (++classidx >= max_classes) {
 167                                 vfree(pack);
 168                                 ret = -ENOSPC;
 169                                 goto end;
 170                         }
 171                 }
 172 
 173                 init->addr = addr;
 174                 init->data = av->data;
 175                 init->count = 1;
 176                 init->pitch = 1;
 177         }
 178 
 179         *ppack = pack;
 180 
 181 end:
 182         gf100_gr_dtor_fw(&fuc);
 183         return ret;
 184 }
 185 
 186 static int
 187 gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
 188 {
 189         struct nvkm_subdev *subdev = &gr->base.engine.subdev;
 190         struct nvkm_device *device = subdev->device;
 191 
 192         if (nvkm_msec(device, 2000,
 193                 if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
 194                         break;
 195         ) < 0) {
 196                 nvkm_error(subdev, "FECS mem scrubbing timeout\n");
 197                 return -ETIMEDOUT;
 198         }
 199 
 200         if (nvkm_msec(device, 2000,
 201                 if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
 202                         break;
 203         ) < 0) {
 204                 nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
 205                 return -ETIMEDOUT;
 206         }
 207 
 208         return 0;
 209 }
 210 
 211 static void
 212 gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
 213 {
 214         struct nvkm_device *device = gr->base.engine.subdev.device;
 215         nvkm_wr32(device, 0x419e44, 0x1ffffe);
 216         nvkm_wr32(device, 0x419e4c, 0x7f);
 217 }
 218 
 219 int
 220 gk20a_gr_init(struct gf100_gr *gr)
 221 {
 222         struct nvkm_device *device = gr->base.engine.subdev.device;
 223         int ret;
 224 
 225         /* Clear SCC RAM */
 226         nvkm_wr32(device, 0x40802c, 0x1);
 227 
 228         gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
 229 
 230         ret = gk20a_gr_wait_mem_scrubbing(gr);
 231         if (ret)
 232                 return ret;
 233 
 234         ret = gf100_gr_wait_idle(gr);
 235         if (ret)
 236                 return ret;
 237 
 238         /* MMU debug buffer */
 239         if (gr->func->init_gpc_mmu)
 240                 gr->func->init_gpc_mmu(gr);
 241 
 242         /* Set the PE as stream master */
 243         nvkm_mask(device, 0x503018, 0x1, 0x1);
 244 
 245         /* Zcull init */
 246         gr->func->init_zcull(gr);
 247 
 248         gr->func->init_rop_active_fbps(gr);
 249 
 250         /* Enable FIFO access */
 251         nvkm_wr32(device, 0x400500, 0x00010001);
 252 
 253         /* Enable interrupts */
 254         nvkm_wr32(device, 0x400100, 0xffffffff);
 255         nvkm_wr32(device, 0x40013c, 0xffffffff);
 256 
 257         /* Enable FECS error interrupts */
 258         nvkm_wr32(device, 0x409c24, 0x000f0000);
 259 
 260         /* Enable hardware warning exceptions */
 261         nvkm_wr32(device, 0x404000, 0xc0000000);
 262         nvkm_wr32(device, 0x404600, 0xc0000000);
 263 
 264         if (gr->func->set_hww_esr_report_mask)
 265                 gr->func->set_hww_esr_report_mask(gr);
 266 
 267         /* Enable TPC exceptions per GPC */
 268         nvkm_wr32(device, 0x419d0c, 0x2);
 269         nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16);
 270 
 271         /* Reset and enable all exceptions */
 272         nvkm_wr32(device, 0x400108, 0xffffffff);
 273         nvkm_wr32(device, 0x400138, 0xffffffff);
 274         nvkm_wr32(device, 0x400118, 0xffffffff);
 275         nvkm_wr32(device, 0x400130, 0xffffffff);
 276         nvkm_wr32(device, 0x40011c, 0xffffffff);
 277         nvkm_wr32(device, 0x400134, 0xffffffff);
 278 
 279         gf100_gr_zbc_init(gr);
 280 
 281         return gf100_gr_init_ctxctl(gr);
 282 }
 283 
 284 static const struct gf100_gr_func
 285 gk20a_gr = {
 286         .oneinit_tiles = gf100_gr_oneinit_tiles,
 287         .oneinit_sm_id = gf100_gr_oneinit_sm_id,
 288         .init = gk20a_gr_init,
 289         .init_zcull = gf117_gr_init_zcull,
 290         .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
 291         .trap_mp = gf100_gr_trap_mp,
 292         .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
 293         .rops = gf100_gr_rops,
 294         .ppc_nr = 1,
 295         .grctx = &gk20a_grctx,
 296         .zbc = &gf100_gr_zbc,
 297         .sclass = {
 298                 { -1, -1, FERMI_TWOD_A },
 299                 { -1, -1, KEPLER_INLINE_TO_MEMORY_A },
 300                 { -1, -1, KEPLER_C, &gf100_fermi },
 301                 { -1, -1, KEPLER_COMPUTE_A },
 302                 {}
 303         }
 304 };
 305 
 306 int
 307 gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
 308 {
 309         struct gf100_gr *gr;
 310         int ret;
 311 
 312         if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
 313                 return -ENOMEM;
 314         *pgr = &gr->base;
 315 
 316         ret = gf100_gr_ctor(&gk20a_gr, device, index, gr);
 317         if (ret)
 318                 return ret;
 319 
 320         if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
 321             gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
 322             gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
 323             gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
 324                 return -ENODEV;
 325 
 326         ret = gk20a_gr_av_to_init(gr, "sw_nonctx", &gr->fuc_sw_nonctx);
 327         if (ret)
 328                 return ret;
 329 
 330         ret = gk20a_gr_aiv_to_init(gr, "sw_ctx", &gr->fuc_sw_ctx);
 331         if (ret)
 332                 return ret;
 333 
 334         ret = gk20a_gr_av_to_init(gr, "sw_bundle_init", &gr->fuc_bundle);
 335         if (ret)
 336                 return ret;
 337 
 338         ret = gk20a_gr_av_to_method(gr, "sw_method_init", &gr->fuc_method);
 339         if (ret)
 340                 return ret;
 341 
 342         return 0;
 343 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c

DEFINITIONS
