root/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c

DEFINITIONS

1. g84_cipher_oclass_bind
2. g84_cipher_cclass_bind
3. g84_cipher_intr
4. g84_cipher_init
5. g84_cipher_new

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <engine/cipher.h>
  25 #include <engine/fifo.h>
  26 
  27 #include <core/client.h>
  28 #include <core/enum.h>
  29 #include <core/gpuobj.h>
  30 
  31 #include <nvif/class.h>
  32 
  33 static int
  34 g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
  35                        int align, struct nvkm_gpuobj **pgpuobj)
  36 {
  37         int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16,
  38                                   align, false, parent, pgpuobj);
  39         if (ret == 0) {
  40                 nvkm_kmap(*pgpuobj);
  41                 nvkm_wo32(*pgpuobj, 0x00, object->oclass);
  42                 nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
  43                 nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
  44                 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
  45                 nvkm_done(*pgpuobj);
  46         }
  47         return ret;
  48 }
  49 
  50 static const struct nvkm_object_func
  51 g84_cipher_oclass_func = {
  52         .bind = g84_cipher_oclass_bind,
  53 };
  54 
  55 static int
  56 g84_cipher_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
  57                        int align, struct nvkm_gpuobj **pgpuobj)
  58 {
  59         return nvkm_gpuobj_new(object->engine->subdev.device, 256,
  60                                align, true, parent, pgpuobj);
  61 
  62 }
  63 
  64 static const struct nvkm_object_func
  65 g84_cipher_cclass = {
  66         .bind = g84_cipher_cclass_bind,
  67 };
  68 
  69 static const struct nvkm_bitfield
  70 g84_cipher_intr_mask[] = {
  71         { 0x00000001, "INVALID_STATE" },
  72         { 0x00000002, "ILLEGAL_MTHD" },
  73         { 0x00000004, "ILLEGAL_CLASS" },
  74         { 0x00000080, "QUERY" },
  75         { 0x00000100, "FAULT" },
  76         {}
  77 };
  78 
  79 static void
  80 g84_cipher_intr(struct nvkm_engine *cipher)
  81 {
  82         struct nvkm_subdev *subdev = &cipher->subdev;
  83         struct nvkm_device *device = subdev->device;
  84         struct nvkm_fifo *fifo = device->fifo;
  85         struct nvkm_fifo_chan *chan;
  86         u32 stat = nvkm_rd32(device, 0x102130);
  87         u32 mthd = nvkm_rd32(device, 0x102190);
  88         u32 data = nvkm_rd32(device, 0x102194);
  89         u32 inst = nvkm_rd32(device, 0x102188) & 0x7fffffff;
  90         unsigned long flags;
  91         char msg[128];
  92 
  93         chan = nvkm_fifo_chan_inst(fifo, (u64)inst << 12, &flags);
  94         if (stat) {
  95                 nvkm_snprintbf(msg, sizeof(msg), g84_cipher_intr_mask, stat);
  96                 nvkm_error(subdev,  "%08x [%s] ch %d [%010llx %s] "
  97                                     "mthd %04x data %08x\n", stat, msg,
  98                            chan ? chan->chid : -1, (u64)inst << 12,
  99                            chan ? chan->object.client->name : "unknown",
 100                            mthd, data);
 101         }
 102         nvkm_fifo_chan_put(fifo, flags, &chan);
 103 
 104         nvkm_wr32(device, 0x102130, stat);
 105         nvkm_wr32(device, 0x10200c, 0x10);
 106 }
 107 
 108 static int
 109 g84_cipher_init(struct nvkm_engine *cipher)
 110 {
 111         struct nvkm_device *device = cipher->subdev.device;
 112         nvkm_wr32(device, 0x102130, 0xffffffff);
 113         nvkm_wr32(device, 0x102140, 0xffffffbf);
 114         nvkm_wr32(device, 0x10200c, 0x00000010);
 115         return 0;
 116 }
 117 
 118 static const struct nvkm_engine_func
 119 g84_cipher = {
 120         .init = g84_cipher_init,
 121         .intr = g84_cipher_intr,
 122         .cclass = &g84_cipher_cclass,
 123         .sclass = {
 124                 { -1, -1, NV74_CIPHER, &g84_cipher_oclass_func },
 125                 {}
 126         }
 127 };
 128 
 129 int
 130 g84_cipher_new(struct nvkm_device *device, int index,
 131                struct nvkm_engine **pengine)
 132 {
 133         return nvkm_engine_new_(&g84_cipher, device, index, true, pengine);
 134 }