root/drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c

DEFINITIONS

1. tu102_fifo_runlist_commit
2. tu102_fifo_pbdma_init
3. tu102_fifo_new

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "gk104.h"
  23 #include "cgrp.h"
  24 #include "changk104.h"
  25 #include "user.h"
  26 
  27 #include <core/gpuobj.h>
  28 
  29 #include <nvif/class.h>
  30 
  31 static void
  32 tu102_fifo_runlist_commit(struct gk104_fifo *fifo, int runl,
  33                           struct nvkm_memory *mem, int nr)
  34 {
  35         struct nvkm_device *device = fifo->base.engine.subdev.device;
  36         u64 addr = nvkm_memory_addr(mem);
  37         /*XXX: target? */
  38 
  39         nvkm_wr32(device, 0x002b00 + (runl * 0x10), lower_32_bits(addr));
  40         nvkm_wr32(device, 0x002b04 + (runl * 0x10), upper_32_bits(addr));
  41         nvkm_wr32(device, 0x002b08 + (runl * 0x10), nr);
  42 
  43         /*XXX: how to wait? can you even wait? */
  44 }
  45 
  46 const struct gk104_fifo_runlist_func
  47 tu102_fifo_runlist = {
  48         .size = 16,
  49         .cgrp = gv100_fifo_runlist_cgrp,
  50         .chan = gv100_fifo_runlist_chan,
  51         .commit = tu102_fifo_runlist_commit,
  52 };
  53 
  54 static const struct nvkm_enum
  55 tu102_fifo_fault_engine[] = {
  56         { 0x01, "DISPLAY" },
  57         { 0x03, "PTP" },
  58         { 0x06, "PWR_PMU" },
  59         { 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
  60         { 0x09, "PERF" },
  61         { 0x1f, "PHYSICAL" },
  62         { 0x20, "HOST0" },
  63         { 0x21, "HOST1" },
  64         { 0x22, "HOST2" },
  65         { 0x23, "HOST3" },
  66         { 0x24, "HOST4" },
  67         { 0x25, "HOST5" },
  68         { 0x26, "HOST6" },
  69         { 0x27, "HOST7" },
  70         { 0x28, "HOST8" },
  71         { 0x29, "HOST9" },
  72         { 0x2a, "HOST10" },
  73         { 0x2b, "HOST11" },
  74         { 0x2c, "HOST12" },
  75         { 0x2d, "HOST13" },
  76         { 0x2e, "HOST14" },
  77         { 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR },
  78         { 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
  79         {}
  80 };
  81 
  82 static void
  83 tu102_fifo_pbdma_init(struct gk104_fifo *fifo)
  84 {
  85         struct nvkm_device *device = fifo->base.engine.subdev.device;
  86         const u32 mask = (1 << fifo->pbdma_nr) - 1;
  87         /*XXX: this is a bit of a guess at this point in time. */
  88         nvkm_mask(device, 0xb65000, 0x80000fff, 0x80000000 | mask);
  89 }
  90 
  91 static const struct gk104_fifo_pbdma_func
  92 tu102_fifo_pbdma = {
  93         .nr = gm200_fifo_pbdma_nr,
  94         .init = tu102_fifo_pbdma_init,
  95         .init_timeout = gk208_fifo_pbdma_init_timeout,
  96 };
  97 
  98 static const struct gk104_fifo_func
  99 tu102_fifo = {
 100         .pbdma = &tu102_fifo_pbdma,
 101         .fault.access = gv100_fifo_fault_access,
 102         .fault.engine = tu102_fifo_fault_engine,
 103         .fault.reason = gv100_fifo_fault_reason,
 104         .fault.hubclient = gv100_fifo_fault_hubclient,
 105         .fault.gpcclient = gv100_fifo_fault_gpcclient,
 106         .runlist = &tu102_fifo_runlist,
 107         .user = {{-1,-1,VOLTA_USERMODE_A       }, tu102_fifo_user_new   },
 108         .chan = {{ 0, 0,TURING_CHANNEL_GPFIFO_A}, tu102_fifo_gpfifo_new },
 109         .cgrp_force = true,
 110 };
 111 
 112 int
 113 tu102_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 114 {
 115         return gk104_fifo_new_(&tu102_fifo, device, index, 4096, pfifo);
 116 }