root/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c

DEFINITIONS

1. g84_fifo_dma_new

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "channv50.h"
  25 
  26 #include <core/client.h>
  27 #include <core/ramht.h>
  28 
  29 #include <nvif/class.h>
  30 #include <nvif/cl826e.h>
  31 #include <nvif/unpack.h>
  32 
  33 static int
  34 g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
  35                  void *data, u32 size, struct nvkm_object **pobject)
  36 {
  37         struct nvkm_object *parent = oclass->parent;
  38         union {
  39                 struct g82_channel_dma_v0 v0;
  40         } *args = data;
  41         struct nv50_fifo *fifo = nv50_fifo(base);
  42         struct nv50_fifo_chan *chan;
  43         int ret = -ENOSYS;
  44 
  45         nvif_ioctl(parent, "create channel dma size %d\n", size);
  46         if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
  47                 nvif_ioctl(parent, "create channel dma vers %d vmm %llx "
  48                                    "pushbuf %llx offset %016llx\n",
  49                            args->v0.version, args->v0.vmm, args->v0.pushbuf,
  50                            args->v0.offset);
  51                 if (!args->v0.pushbuf)
  52                         return -EINVAL;
  53         } else
  54                 return ret;
  55 
  56         if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
  57                 return -ENOMEM;
  58         *pobject = &chan->base.object;
  59 
  60         ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,
  61                                  oclass, chan);
  62         if (ret)
  63                 return ret;
  64 
  65         args->v0.chid = chan->base.chid;
  66 
  67         nvkm_kmap(chan->ramfc);
  68         nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
  69         nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
  70         nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
  71         nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
  72         nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
  73         nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
  74         nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
  75         nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
  76         nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
  77         nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
  78         nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
  79         nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
  80                                      (4 << 24) /* SEARCH_FULL */ |
  81                                      (chan->ramht->gpuobj->node->offset >> 4));
  82         nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10);
  83         nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12);
  84         nvkm_done(chan->ramfc);
  85         return 0;
  86 }
  87 
  88 const struct nvkm_fifo_chan_oclass
  89 g84_fifo_dma_oclass = {
  90         .base.oclass = G82_CHANNEL_DMA,
  91         .base.minver = 0,
  92         .base.maxver = 0,
  93         .ctor = g84_fifo_dma_new,
  94 };