drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
pll_limits_table
pll_map
pll_map_reg
pll_map_type
nvbios_pll_parse
   1 /*
   2  * Copyright 2005-2006 Erik Waling
   3  * Copyright 2006 Stephane Marchesin
   4  * Copyright 2007-2009 Stuart Bennett
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  20  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  21  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24 #include <subdev/bios.h>
  25 #include <subdev/bios/bit.h>
  26 #include <subdev/bios/bmp.h>
  27 #include <subdev/bios/pll.h>
  28 #include <subdev/vga.h>
  29 
  30 
  31 struct pll_mapping {
  32         u8  type;
  33         u32 reg;
  34 };
  35 
  36 static struct pll_mapping
  37 nv04_pll_mapping[] = {
  38         { PLL_CORE  , 0x680500 },
  39         { PLL_MEMORY, 0x680504 },
  40         { PLL_VPLL0 , 0x680508 },
  41         { PLL_VPLL1 , 0x680520 },
  42         {}
  43 };
  44 
  45 static struct pll_mapping
  46 nv40_pll_mapping[] = {
  47         { PLL_CORE  , 0x004000 },
  48         { PLL_MEMORY, 0x004020 },
  49         { PLL_VPLL0 , 0x680508 },
  50         { PLL_VPLL1 , 0x680520 },
  51         {}
  52 };
  53 
  54 static struct pll_mapping
  55 nv50_pll_mapping[] = {
  56         { PLL_CORE  , 0x004028 },
  57         { PLL_SHADER, 0x004020 },
  58         { PLL_UNK03 , 0x004000 },
  59         { PLL_MEMORY, 0x004008 },
  60         { PLL_UNK40 , 0x00e810 },
  61         { PLL_UNK41 , 0x00e818 },
  62         { PLL_UNK42 , 0x00e824 },
  63         { PLL_VPLL0 , 0x614100 },
  64         { PLL_VPLL1 , 0x614900 },
  65         {}
  66 };
  67 
  68 static struct pll_mapping
  69 g84_pll_mapping[] = {
  70         { PLL_CORE  , 0x004028 },
  71         { PLL_SHADER, 0x004020 },
  72         { PLL_MEMORY, 0x004008 },
  73         { PLL_VDEC  , 0x004030 },
  74         { PLL_UNK41 , 0x00e818 },
  75         { PLL_VPLL0 , 0x614100 },
  76         { PLL_VPLL1 , 0x614900 },
  77         {}
  78 };
  79 
  80 static u32
  81 pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
  82 {
  83         struct bit_entry bit_C;
  84         u32 data = 0x0000;
  85 
  86         if (!bit_entry(bios, 'C', &bit_C)) {
  87                 if (bit_C.version == 1 && bit_C.length >= 10)
  88                         data = nvbios_rd16(bios, bit_C.offset + 8);
  89                 if (bit_C.version == 2 && bit_C.length >= 4)
  90                         data = nvbios_rd32(bios, bit_C.offset + 0);
  91                 if (data) {
  92                         *ver = nvbios_rd08(bios, data + 0);
  93                         *hdr = nvbios_rd08(bios, data + 1);
  94                         *len = nvbios_rd08(bios, data + 2);
  95                         *cnt = nvbios_rd08(bios, data + 3);
  96                         return data;
  97                 }
  98         }
  99 
 100         if (bmp_version(bios) >= 0x0524) {
 101                 data = nvbios_rd16(bios, bios->bmp_offset + 142);
 102                 if (data) {
 103                         *ver = nvbios_rd08(bios, data + 0);
 104                         *hdr = 1;
 105                         *cnt = 1;
 106                         *len = 0x18;
 107                         return data;
 108                 }
 109         }
 110 
 111         *ver = 0x00;
 112         return data;
 113 }
 114 
 115 static struct pll_mapping *
 116 pll_map(struct nvkm_bios *bios)
 117 {
 118         struct nvkm_device *device = bios->subdev.device;
 119         switch (device->card_type) {
 120         case NV_04:
 121         case NV_10:
 122         case NV_11:
 123         case NV_20:
 124         case NV_30:
 125                 return nv04_pll_mapping;
 126                 break;
 127         case NV_40:
 128                 return nv40_pll_mapping;
 129         case NV_50:
 130                 if (device->chipset == 0x50)
 131                         return nv50_pll_mapping;
 132                 else
 133                 if (device->chipset <  0xa3 ||
 134                     device->chipset == 0xaa ||
 135                     device->chipset == 0xac)
 136                         return g84_pll_mapping;
 137                 /* fall through */
 138         default:
 139                 return NULL;
 140         }
 141 }
 142 
 143 static u32
 144 pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
 145 {
 146         struct pll_mapping *map;
 147         u8  hdr, cnt;
 148         u32 data;
 149 
 150         data = pll_limits_table(bios, ver, &hdr, &cnt, len);
 151         if (data && *ver >= 0x30) {
 152                 data += hdr;
 153                 while (cnt--) {
 154                         if (nvbios_rd32(bios, data + 3) == reg) {
 155                                 *type = nvbios_rd08(bios, data + 0);
 156                                 return data;
 157                         }
 158                         data += *len;
 159                 }
 160                 return 0x0000;
 161         }
 162 
 163         map = pll_map(bios);
 164         while (map && map->reg) {
 165                 if (map->reg == reg && *ver >= 0x20) {
 166                         u32 addr = (data += hdr);
 167                         *type = map->type;
 168                         while (cnt--) {
 169                                 if (nvbios_rd32(bios, data) == map->reg)
 170                                         return data;
 171                                 data += *len;
 172                         }
 173                         return addr;
 174                 } else
 175                 if (map->reg == reg) {
 176                         *type = map->type;
 177                         return data + 1;
 178                 }
 179                 map++;
 180         }
 181 
 182         return 0x0000;
 183 }
 184 
 185 static u32
 186 pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
 187 {
 188         struct pll_mapping *map;
 189         u8  hdr, cnt;
 190         u32 data;
 191 
 192         data = pll_limits_table(bios, ver, &hdr, &cnt, len);
 193         if (data && *ver >= 0x30) {
 194                 data += hdr;
 195                 while (cnt--) {
 196                         if (nvbios_rd08(bios, data + 0) == type) {
 197                                 if (*ver < 0x50)
 198                                         *reg = nvbios_rd32(bios, data + 3);
 199                                 else
 200                                         *reg = 0;
 201                                 return data;
 202                         }
 203                         data += *len;
 204                 }
 205                 return 0x0000;
 206         }
 207 
 208         map = pll_map(bios);
 209         while (map && map->reg) {
 210                 if (map->type == type && *ver >= 0x20) {
 211                         u32 addr = (data += hdr);
 212                         *reg = map->reg;
 213                         while (cnt--) {
 214                                 if (nvbios_rd32(bios, data) == map->reg)
 215                                         return data;
 216                                 data += *len;
 217                         }
 218                         return addr;
 219                 } else
 220                 if (map->type == type) {
 221                         *reg = map->reg;
 222                         return data + 1;
 223                 }
 224                 map++;
 225         }
 226 
 227         return 0x0000;
 228 }
 229 
 230 int
 231 nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info)
 232 {
 233         struct nvkm_subdev *subdev = &bios->subdev;
 234         struct nvkm_device *device = subdev->device;
 235         u8  ver, len;
 236         u32 reg = type;
 237         u32 data;
 238 
 239         if (type > PLL_MAX) {
 240                 reg  = type;
 241                 data = pll_map_reg(bios, reg, &type, &ver, &len);
 242         } else {
 243                 data = pll_map_type(bios, type, &reg, &ver, &len);
 244         }
 245 
 246         if (ver && !data)
 247                 return -ENOENT;
 248 
 249         memset(info, 0, sizeof(*info));
 250         info->type = type;
 251         info->reg = reg;
 252 
 253         switch (ver) {
 254         case 0x00:
 255                 break;
 256         case 0x10:
 257         case 0x11:
 258                 info->vco1.min_freq = nvbios_rd32(bios, data + 0);
 259                 info->vco1.max_freq = nvbios_rd32(bios, data + 4);
 260                 info->vco2.min_freq = nvbios_rd32(bios, data + 8);
 261                 info->vco2.max_freq = nvbios_rd32(bios, data + 12);
 262                 info->vco1.min_inputfreq = nvbios_rd32(bios, data + 16);
 263                 info->vco2.min_inputfreq = nvbios_rd32(bios, data + 20);
 264                 info->vco1.max_inputfreq = INT_MAX;
 265                 info->vco2.max_inputfreq = INT_MAX;
 266 
 267                 info->max_p = 0x7;
 268                 info->max_p_usable = 0x6;
 269 
 270                 /* these values taken from nv30/31/36 */
 271                 switch (bios->version.chip) {
 272                 case 0x36:
 273                         info->vco1.min_n = 0x5;
 274                         break;
 275                 default:
 276                         info->vco1.min_n = 0x1;
 277                         break;
 278                 }
 279                 info->vco1.max_n = 0xff;
 280                 info->vco1.min_m = 0x1;
 281                 info->vco1.max_m = 0xd;
 282 
 283                 /*
 284                  * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
 285                  * table version (apart from nv35)), N2 is compared to
 286                  * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
 287                  * save a comparison
 288                  */
 289                 info->vco2.min_n = 0x4;
 290                 switch (bios->version.chip) {
 291                 case 0x30:
 292                 case 0x35:
 293                         info->vco2.max_n = 0x1f;
 294                         break;
 295                 default:
 296                         info->vco2.max_n = 0x28;
 297                         break;
 298                 }
 299                 info->vco2.min_m = 0x1;
 300                 info->vco2.max_m = 0x4;
 301                 break;
 302         case 0x20:
 303         case 0x21:
 304                 info->vco1.min_freq = nvbios_rd16(bios, data + 4) * 1000;
 305                 info->vco1.max_freq = nvbios_rd16(bios, data + 6) * 1000;
 306                 info->vco2.min_freq = nvbios_rd16(bios, data + 8) * 1000;
 307                 info->vco2.max_freq = nvbios_rd16(bios, data + 10) * 1000;
 308                 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
 309                 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
 310                 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 16) * 1000;
 311                 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 18) * 1000;
 312                 info->vco1.min_n = nvbios_rd08(bios, data + 20);
 313                 info->vco1.max_n = nvbios_rd08(bios, data + 21);
 314                 info->vco1.min_m = nvbios_rd08(bios, data + 22);
 315                 info->vco1.max_m = nvbios_rd08(bios, data + 23);
 316                 info->vco2.min_n = nvbios_rd08(bios, data + 24);
 317                 info->vco2.max_n = nvbios_rd08(bios, data + 25);
 318                 info->vco2.min_m = nvbios_rd08(bios, data + 26);
 319                 info->vco2.max_m = nvbios_rd08(bios, data + 27);
 320 
 321                 info->max_p = nvbios_rd08(bios, data + 29);
 322                 info->max_p_usable = info->max_p;
 323                 if (bios->version.chip < 0x60)
 324                         info->max_p_usable = 0x6;
 325                 info->bias_p = nvbios_rd08(bios, data + 30);
 326 
 327                 if (len > 0x22)
 328                         info->refclk = nvbios_rd32(bios, data + 31);
 329                 break;
 330         case 0x30:
 331                 data = nvbios_rd16(bios, data + 1);
 332 
 333                 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
 334                 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
 335                 info->vco2.min_freq = nvbios_rd16(bios, data + 4) * 1000;
 336                 info->vco2.max_freq = nvbios_rd16(bios, data + 6) * 1000;
 337                 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 8) * 1000;
 338                 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 10) * 1000;
 339                 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 12) * 1000;
 340                 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 14) * 1000;
 341                 info->vco1.min_n = nvbios_rd08(bios, data + 16);
 342                 info->vco1.max_n = nvbios_rd08(bios, data + 17);
 343                 info->vco1.min_m = nvbios_rd08(bios, data + 18);
 344                 info->vco1.max_m = nvbios_rd08(bios, data + 19);
 345                 info->vco2.min_n = nvbios_rd08(bios, data + 20);
 346                 info->vco2.max_n = nvbios_rd08(bios, data + 21);
 347                 info->vco2.min_m = nvbios_rd08(bios, data + 22);
 348                 info->vco2.max_m = nvbios_rd08(bios, data + 23);
 349                 info->max_p_usable = info->max_p = nvbios_rd08(bios, data + 25);
 350                 info->bias_p = nvbios_rd08(bios, data + 27);
 351                 info->refclk = nvbios_rd32(bios, data + 28);
 352                 break;
 353         case 0x40:
 354                 info->refclk = nvbios_rd16(bios, data + 9) * 1000;
 355                 data = nvbios_rd16(bios, data + 1);
 356 
 357                 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000;
 358                 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000;
 359                 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 4) * 1000;
 360                 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 6) * 1000;
 361                 info->vco1.min_m = nvbios_rd08(bios, data + 8);
 362                 info->vco1.max_m = nvbios_rd08(bios, data + 9);
 363                 info->vco1.min_n = nvbios_rd08(bios, data + 10);
 364                 info->vco1.max_n = nvbios_rd08(bios, data + 11);
 365                 info->min_p = nvbios_rd08(bios, data + 12);
 366                 info->max_p = nvbios_rd08(bios, data + 13);
 367                 break;
 368         case 0x50:
 369                 info->refclk = nvbios_rd16(bios, data + 1) * 1000;
 370                 /* info->refclk_alt = nvbios_rd16(bios, data + 3) * 1000; */
 371                 info->vco1.min_freq = nvbios_rd16(bios, data + 5) * 1000;
 372                 info->vco1.max_freq = nvbios_rd16(bios, data + 7) * 1000;
 373                 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 9) * 1000;
 374                 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 11) * 1000;
 375                 info->vco1.min_m = nvbios_rd08(bios, data + 13);
 376                 info->vco1.max_m = nvbios_rd08(bios, data + 14);
 377                 info->vco1.min_n = nvbios_rd08(bios, data + 15);
 378                 info->vco1.max_n = nvbios_rd08(bios, data + 16);
 379                 info->min_p = nvbios_rd08(bios, data + 17);
 380                 info->max_p = nvbios_rd08(bios, data + 18);
 381                 break;
 382         default:
 383                 nvkm_error(subdev, "unknown pll limits version 0x%02x\n", ver);
 384                 return -EINVAL;
 385         }
 386 
 387         if (!info->refclk) {
 388                 info->refclk = device->crystal;
 389                 if (bios->version.chip == 0x51) {
 390                         u32 sel_clk = nvkm_rd32(device, 0x680524);
 391                         if ((info->reg == 0x680508 && sel_clk & 0x20) ||
 392                             (info->reg == 0x680520 && sel_clk & 0x80)) {
 393                                 if (nvkm_rdvgac(device, 0, 0x27) < 0xa3)
 394                                         info->refclk = 200000;
 395                                 else
 396                                         info->refclk = 25000;
 397                         }
 398                 }
 399         }
 400 
 401         /*
 402          * By now any valid limit table ought to have set a max frequency for
 403          * vco1, so if it's zero it's either a pre limit table bios, or one
 404          * with an empty limit table (seen on nv18)
 405          */
 406         if (!info->vco1.max_freq) {
 407                 info->vco1.max_freq = nvbios_rd32(bios, bios->bmp_offset + 67);
 408                 info->vco1.min_freq = nvbios_rd32(bios, bios->bmp_offset + 71);
 409                 if (bmp_version(bios) < 0x0506) {
 410                         info->vco1.max_freq = 256000;
 411                         info->vco1.min_freq = 128000;
 412                 }
 413 
 414                 info->vco1.min_inputfreq = 0;
 415                 info->vco1.max_inputfreq = INT_MAX;
 416                 info->vco1.min_n = 0x1;
 417                 info->vco1.max_n = 0xff;
 418                 info->vco1.min_m = 0x1;
 419 
 420                 if (device->crystal == 13500) {
 421                         /* nv05 does this, nv11 doesn't, nv10 unknown */
 422                         if (bios->version.chip < 0x11)
 423                                 info->vco1.min_m = 0x7;
 424                         info->vco1.max_m = 0xd;
 425                 } else {
 426                         if (bios->version.chip < 0x11)
 427                                 info->vco1.min_m = 0x8;
 428                         info->vco1.max_m = 0xe;
 429                 }
 430 
 431                 if (bios->version.chip <  0x17 ||
 432                     bios->version.chip == 0x1a ||
 433                     bios->version.chip == 0x20)
 434                         info->max_p = 4;
 435                 else
 436                         info->max_p = 5;
 437                 info->max_p_usable = info->max_p;
 438         }
 439 
 440         return 0;
 441 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c

DEFINITIONS
