root/drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c

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DEFINITIONS

This source file includes following definitions.
  1. g94_bus_hwsq_exec
  2. g94_bus_new

   1 /*
   2  * Copyright 2012 Nouveau Community
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Martin Peres <martin.peres@labri.fr>
  23  *          Ben Skeggs
  24  */
  25 #include "priv.h"
  26 
  27 #include <subdev/timer.h>
  28 
  29 static int
  30 g94_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
  31 {
  32         struct nvkm_device *device = bus->subdev.device;
  33         int i;
  34 
  35         nvkm_mask(device, 0x001098, 0x00000008, 0x00000000);
  36         nvkm_wr32(device, 0x001304, 0x00000000);
  37         nvkm_wr32(device, 0x001318, 0x00000000);
  38         for (i = 0; i < size; i++)
  39                 nvkm_wr32(device, 0x080000 + (i * 4), data[i]);
  40         nvkm_mask(device, 0x001098, 0x00000018, 0x00000018);
  41         nvkm_wr32(device, 0x00130c, 0x00000001);
  42 
  43         if (nvkm_msec(device, 2000,
  44                 if (!(nvkm_rd32(device, 0x001308) & 0x00000100))
  45                         break;
  46         ) < 0)
  47                 return -ETIMEDOUT;
  48 
  49         return 0;
  50 }
  51 
  52 static const struct nvkm_bus_func
  53 g94_bus = {
  54         .init = nv50_bus_init,
  55         .intr = nv50_bus_intr,
  56         .hwsq_exec = g94_bus_hwsq_exec,
  57         .hwsq_size = 128,
  58 };
  59 
  60 int
  61 g94_bus_new(struct nvkm_device *device, int index, struct nvkm_bus **pbus)
  62 {
  63         return nvkm_bus_new_(&g94_bus, device, index, pbus);
  64 }

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