root/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVKM_CLK_SEQ_H__
   3 #define __NVKM_CLK_SEQ_H__
   4 #include <subdev/bus/hwsq.h>
   5 
   6 #define clk_init(s,p)       hwsq_init(&(s)->base, (p))
   7 #define clk_exec(s,e)       hwsq_exec(&(s)->base, (e))
   8 #define clk_have(s,r)       ((s)->r_##r.addr != 0x000000)
   9 #define clk_rd32(s,r)       hwsq_rd32(&(s)->base, &(s)->r_##r)
  10 #define clk_wr32(s,r,d)     hwsq_wr32(&(s)->base, &(s)->r_##r, (d))
  11 #define clk_mask(s,r,m,d)   hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d))
  12 #define clk_setf(s,f,d)     hwsq_setf(&(s)->base, (f), (d))
  13 #define clk_wait(s,f,d)     hwsq_wait(&(s)->base, (f), (d))
  14 #define clk_nsec(s,n)       hwsq_nsec(&(s)->base, (n))
  15 #endif
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