root/drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h

/* [<][>][^][v][top][bottom][index][help] */

INCLUDED FROM


   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVKM_CLK_PRIV_H__
   3 #define __NVKM_CLK_PRIV_H__
   4 #define nvkm_clk(p) container_of((p), struct nvkm_clk, subdev)
   5 #include <subdev/clk.h>
   6 
   7 struct nvkm_clk_func {
   8         int (*init)(struct nvkm_clk *);
   9         void (*fini)(struct nvkm_clk *);
  10         int (*read)(struct nvkm_clk *, enum nv_clk_src);
  11         int (*calc)(struct nvkm_clk *, struct nvkm_cstate *);
  12         int (*prog)(struct nvkm_clk *);
  13         void (*tidy)(struct nvkm_clk *);
  14         struct nvkm_pstate *pstates;
  15         int nr_pstates;
  16         struct nvkm_domain domains[];
  17 };
  18 
  19 int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, int,
  20                   bool allow_reclock, struct nvkm_clk *);
  21 int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int,
  22                   bool allow_reclock, struct nvkm_clk **);
  23 
  24 int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,
  25                       struct nvkm_pll_vals *);
  26 int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
  27 #endif

/* [<][>][^][v][top][bottom][index][help] */