root/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c

DEFINITIONS

1. acr_ls_ucode_load_msgqueue
2. acr_ls_msgqueue_post_run
3. acr_ls_ucode_load_pmu
4. acr_ls_pmu_post_run
5. acr_ls_ucode_load_sec2
6. acr_ls_sec2_post_run

   1 /*
   2  * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 
  24 #include "ls_ucode.h"
  25 #include "acr.h"
  26 
  27 #include <core/firmware.h>
  28 #include <core/msgqueue.h>
  29 #include <subdev/pmu.h>
  30 #include <engine/sec2.h>
  31 #include <subdev/mc.h>
  32 #include <subdev/timer.h>
  33 
  34 /**
  35  * acr_ls_ucode_load_msgqueue - load and prepare a ucode img for a msgqueue fw
  36  *
  37  * Load the LS microcode, desc and signature and pack them into a single
  38  * blob.
  39  */
  40 static int
  41 acr_ls_ucode_load_msgqueue(const struct nvkm_subdev *subdev, const char *name,
  42                            int maxver, struct ls_ucode_img *img)
  43 {
  44         const struct firmware *image, *desc, *sig;
  45         char f[64];
  46         int ver, ret;
  47 
  48         snprintf(f, sizeof(f), "%s/image", name);
  49         ver = nvkm_firmware_get_version(subdev, f, 0, maxver, &image);
  50         if (ver < 0)
  51                 return ver;
  52         img->ucode_data = kmemdup(image->data, image->size, GFP_KERNEL);
  53         nvkm_firmware_put(image);
  54         if (!img->ucode_data)
  55                 return -ENOMEM;
  56 
  57         snprintf(f, sizeof(f), "%s/desc", name);
  58         ret = nvkm_firmware_get_version(subdev, f, ver, ver, &desc);
  59         if (ret < 0)
  60                 return ret;
  61         memcpy(&img->ucode_desc, desc->data, sizeof(img->ucode_desc));
  62         img->ucode_size = ALIGN(img->ucode_desc.app_start_offset + img->ucode_desc.app_size, 256);
  63         nvkm_firmware_put(desc);
  64 
  65         snprintf(f, sizeof(f), "%s/sig", name);
  66         ret = nvkm_firmware_get_version(subdev, f, ver, ver, &sig);
  67         if (ret < 0)
  68                 return ret;
  69         img->sig_size = sig->size;
  70         img->sig = kmemdup(sig->data, sig->size, GFP_KERNEL);
  71         nvkm_firmware_put(sig);
  72         if (!img->sig)
  73                 return -ENOMEM;
  74 
  75         return ver;
  76 }
  77 
  78 static int
  79 acr_ls_msgqueue_post_run(struct nvkm_msgqueue *queue,
  80                          struct nvkm_falcon *falcon, u32 addr_args)
  81 {
  82         struct nvkm_device *device = falcon->owner->device;
  83         u8 buf[NVKM_MSGQUEUE_CMDLINE_SIZE];
  84 
  85         memset(buf, 0, sizeof(buf));
  86         nvkm_msgqueue_write_cmdline(queue, buf);
  87         nvkm_falcon_load_dmem(falcon, buf, addr_args, sizeof(buf), 0);
  88         /* rearm the queue so it will wait for the init message */
  89         nvkm_msgqueue_reinit(queue);
  90 
  91         /* Enable interrupts */
  92         nvkm_falcon_wr32(falcon, 0x10, 0xff);
  93         nvkm_mc_intr_mask(device, falcon->owner->index, true);
  94 
  95         /* Start LS firmware on boot falcon */
  96         nvkm_falcon_start(falcon);
  97 
  98         return 0;
  99 }
 100 
 101 int
 102 acr_ls_ucode_load_pmu(const struct nvkm_secboot *sb, int maxver,
 103                       struct ls_ucode_img *img)
 104 {
 105         struct nvkm_pmu *pmu = sb->subdev.device->pmu;
 106         int ret;
 107 
 108         ret = acr_ls_ucode_load_msgqueue(&sb->subdev, "pmu", maxver, img);
 109         if (ret)
 110                 return ret;
 111 
 112         /* Allocate the PMU queue corresponding to the FW version */
 113         ret = nvkm_msgqueue_new(img->ucode_desc.app_version, pmu->falcon,
 114                                 sb, &pmu->queue);
 115         if (ret)
 116                 return ret;
 117 
 118         return 0;
 119 }
 120 
 121 int
 122 acr_ls_pmu_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb)
 123 {
 124         struct nvkm_device *device = sb->subdev.device;
 125         struct nvkm_pmu *pmu = device->pmu;
 126         u32 addr_args = pmu->falcon->data.limit - NVKM_MSGQUEUE_CMDLINE_SIZE;
 127         int ret;
 128 
 129         ret = acr_ls_msgqueue_post_run(pmu->queue, pmu->falcon, addr_args);
 130         if (ret)
 131                 return ret;
 132 
 133         nvkm_debug(&sb->subdev, "%s started\n",
 134                    nvkm_secboot_falcon_name[acr->boot_falcon]);
 135 
 136         return 0;
 137 }
 138 
 139 int
 140 acr_ls_ucode_load_sec2(const struct nvkm_secboot *sb, int maxver,
 141                        struct ls_ucode_img *img)
 142 {
 143         struct nvkm_sec2 *sec = sb->subdev.device->sec2;
 144         int ver, ret;
 145 
 146         ver = acr_ls_ucode_load_msgqueue(&sb->subdev, "sec2", maxver, img);
 147         if (ver < 0)
 148                 return ver;
 149 
 150         /* Allocate the PMU queue corresponding to the FW version */
 151         ret = nvkm_msgqueue_new(img->ucode_desc.app_version, sec->falcon,
 152                                 sb, &sec->queue);
 153         if (ret)
 154                 return ret;
 155 
 156         return ver;
 157 }
 158 
 159 int
 160 acr_ls_sec2_post_run(const struct nvkm_acr *acr, const struct nvkm_secboot *sb)
 161 {
 162         const struct nvkm_subdev *subdev = &sb->subdev;
 163         struct nvkm_device *device = subdev->device;
 164         struct nvkm_sec2 *sec = device->sec2;
 165         /* on SEC arguments are always at the beginning of EMEM */
 166         const u32 addr_args = 0x01000000;
 167         int ret;
 168 
 169         ret = acr_ls_msgqueue_post_run(sec->queue, sec->falcon, addr_args);
 170         if (ret)
 171                 return ret;
 172 
 173         nvkm_debug(&sb->subdev, "%s started\n",
 174                    nvkm_secboot_falcon_name[acr->boot_falcon]);
 175 
 176         return 0;
 177 }