root/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c

DEFINITIONS

1. gm20b_secboot_tegra_read_wpr
2. gm20b_secboot_tegra_read_wpr
3. gm20b_secboot_oneinit
4. gm20b_secboot_new

   1 /*
   2  * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #include "acr.h"
  24 #include "gm200.h"
  25 
  26 #define TEGRA210_MC_BASE                        0x70019000
  27 
  28 #ifdef CONFIG_ARCH_TEGRA
  29 #define MC_SECURITY_CARVEOUT2_CFG0              0xc58
  30 #define MC_SECURITY_CARVEOUT2_BOM_0             0xc5c
  31 #define MC_SECURITY_CARVEOUT2_BOM_HI_0          0xc60
  32 #define MC_SECURITY_CARVEOUT2_SIZE_128K         0xc64
  33 #define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED   (1 << 1)
  34 /**
  35  * gm20b_secboot_tegra_read_wpr() - read the WPR registers on Tegra
  36  *
  37  * On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region
  38  * is reserved from system memory by the bootloader and irreversibly locked.
  39  * This function reads the address and size of the pre-configured WPR region.
  40  */
  41 int
  42 gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
  43 {
  44         struct nvkm_secboot *sb = &gsb->base;
  45         void __iomem *mc;
  46         u32 cfg;
  47 
  48         mc = ioremap(mc_base, 0xd00);
  49         if (!mc) {
  50                 nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
  51                 return -ENOMEM;
  52         }
  53         sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
  54               ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);
  55         sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K)
  56                 << 17;
  57         cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0);
  58         iounmap(mc);
  59 
  60         /* Check that WPR settings are valid */
  61         if (sb->wpr_size == 0) {
  62                 nvkm_error(&sb->subdev, "WPR region is empty\n");
  63                 return -EINVAL;
  64         }
  65 
  66         if (!(cfg & TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED)) {
  67                 nvkm_error(&sb->subdev, "WPR region not locked\n");
  68                 return -EINVAL;
  69         }
  70 
  71         return 0;
  72 }
  73 #else
  74 int
  75 gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
  76 {
  77         nvkm_error(&gsb->base.subdev, "Tegra support not compiled in\n");
  78         return -EINVAL;
  79 }
  80 #endif
  81 
  82 static int
  83 gm20b_secboot_oneinit(struct nvkm_secboot *sb)
  84 {
  85         struct gm200_secboot *gsb = gm200_secboot(sb);
  86         int ret;
  87 
  88         ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA210_MC_BASE);
  89         if (ret)
  90                 return ret;
  91 
  92         return gm200_secboot_oneinit(sb);
  93 }
  94 
  95 static const struct nvkm_secboot_func
  96 gm20b_secboot = {
  97         .dtor = gm200_secboot_dtor,
  98         .oneinit = gm20b_secboot_oneinit,
  99         .fini = gm200_secboot_fini,
 100         .run_blob = gm200_secboot_run_blob,
 101 };
 102 
 103 int
 104 gm20b_secboot_new(struct nvkm_device *device, int index,
 105                   struct nvkm_secboot **psb)
 106 {
 107         int ret;
 108         struct gm200_secboot *gsb;
 109         struct nvkm_acr *acr;
 110 
 111         *psb = NULL;
 112         acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) |
 113                            BIT(NVKM_SECBOOT_FALCON_PMU));
 114         if (IS_ERR(acr))
 115                 return PTR_ERR(acr);
 116         /* Support the initial GM20B firmware release without PMU */
 117         acr->optional_falcons = BIT(NVKM_SECBOOT_FALCON_PMU);
 118 
 119         gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
 120         if (!gsb)
 121                 return -ENOMEM;
 122         *psb = &gsb->base;
 123 
 124         ret = nvkm_secboot_ctor(&gm20b_secboot, acr, device, index, &gsb->base);
 125         if (ret)
 126                 return ret;
 127 
 128         return 0;
 129 }
 130 
 131 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
 132 MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin");
 133 MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin");
 134 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
 135 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
 136 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
 137 MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
 138 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
 139 MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
 140 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
 141 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
 142 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
 143 MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");
 144 MODULE_FIRMWARE("nvidia/gm20b/pmu/desc.bin");
 145 MODULE_FIRMWARE("nvidia/gm20b/pmu/image.bin");
 146 MODULE_FIRMWARE("nvidia/gm20b/pmu/sig.bin");
 147 #endif