root/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c

DEFINITIONS

1. acr_r375_generate_pmu_bl_desc
2. acr_r375_new

   1 /*
   2  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #include "acr_r370.h"
  24 #include "acr_r367.h"
  25 
  26 #include <core/msgqueue.h>
  27 #include <subdev/pmu.h>
  28 
  29 static void
  30 acr_r375_generate_pmu_bl_desc(const struct nvkm_acr *acr,
  31                               const struct ls_ucode_img *img, u64 wpr_addr,
  32                               void *_desc)
  33 {
  34         const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
  35         const struct nvkm_pmu *pmu = acr->subdev->device->pmu;
  36         struct acr_r370_flcn_bl_desc *desc = _desc;
  37         u64 base, addr_code, addr_data;
  38         u32 addr_args;
  39 
  40         base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
  41         addr_code = base + pdesc->app_resident_code_offset;
  42         addr_data = base + pdesc->app_resident_data_offset;
  43         addr_args = pmu->falcon->data.limit;
  44         addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;
  45 
  46         desc->ctx_dma = FALCON_DMAIDX_UCODE;
  47         desc->code_dma_base = u64_to_flcn64(addr_code);
  48         desc->non_sec_code_off = pdesc->app_resident_code_offset;
  49         desc->non_sec_code_size = pdesc->app_resident_code_size;
  50         desc->code_entry_point = pdesc->app_imem_entry;
  51         desc->data_dma_base = u64_to_flcn64(addr_data);
  52         desc->data_size = pdesc->app_resident_data_size;
  53         desc->argc = 1;
  54         desc->argv = addr_args;
  55 }
  56 
  57 static const struct acr_r352_lsf_func
  58 acr_r375_ls_pmu_func_0 = {
  59         .generate_bl_desc = acr_r375_generate_pmu_bl_desc,
  60         .bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
  61 };
  62 
  63 const struct acr_r352_ls_func
  64 acr_r375_ls_pmu_func = {
  65         .load = acr_ls_ucode_load_pmu,
  66         .post_run = acr_ls_pmu_post_run,
  67         .version_max = 0,
  68         .version = {
  69                 &acr_r375_ls_pmu_func_0,
  70         }
  71 };
  72 
  73 const struct acr_r352_func
  74 acr_r375_func = {
  75         .fixup_hs_desc = acr_r367_fixup_hs_desc,
  76         .generate_hs_bl_desc = acr_r370_generate_hs_bl_desc,
  77         .hs_bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),
  78         .shadow_blob = true,
  79         .ls_ucode_img_load = acr_r367_ls_ucode_img_load,
  80         .ls_fill_headers = acr_r367_ls_fill_headers,
  81         .ls_write_wpr = acr_r367_ls_write_wpr,
  82         .ls_func = {
  83                 [NVKM_SECBOOT_FALCON_FECS] = &acr_r370_ls_fecs_func,
  84                 [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r370_ls_gpccs_func,
  85                 [NVKM_SECBOOT_FALCON_PMU] = &acr_r375_ls_pmu_func,
  86         },
  87 };
  88 
  89 struct nvkm_acr *
  90 acr_r375_new(enum nvkm_secboot_falcon boot_falcon,
  91              unsigned long managed_falcons)
  92 {
  93         return acr_r352_new_(&acr_r375_func, boot_falcon, managed_falcons);
  94 }