root/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c

DEFINITIONS

1. gp10b_secboot_oneinit
2. gp10b_secboot_new

   1 /*
   2  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  */
  22 
  23 #include "acr.h"
  24 #include "gm200.h"
  25 
  26 #define TEGRA186_MC_BASE                        0x02c10000
  27 
  28 static int
  29 gp10b_secboot_oneinit(struct nvkm_secboot *sb)
  30 {
  31         struct gm200_secboot *gsb = gm200_secboot(sb);
  32         int ret;
  33 
  34         ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA186_MC_BASE);
  35         if (ret)
  36                 return ret;
  37 
  38         return gm200_secboot_oneinit(sb);
  39 }
  40 
  41 static const struct nvkm_secboot_func
  42 gp10b_secboot = {
  43         .dtor = gm200_secboot_dtor,
  44         .oneinit = gp10b_secboot_oneinit,
  45         .fini = gm200_secboot_fini,
  46         .run_blob = gm200_secboot_run_blob,
  47 };
  48 
  49 int
  50 gp10b_secboot_new(struct nvkm_device *device, int index,
  51                   struct nvkm_secboot **psb)
  52 {
  53         int ret;
  54         struct gm200_secboot *gsb;
  55         struct nvkm_acr *acr;
  56 
  57         acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) |
  58                            BIT(NVKM_SECBOOT_FALCON_GPCCS) |
  59                            BIT(NVKM_SECBOOT_FALCON_PMU));
  60         if (IS_ERR(acr))
  61                 return PTR_ERR(acr);
  62 
  63         gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
  64         if (!gsb) {
  65                 psb = NULL;
  66                 return -ENOMEM;
  67         }
  68         *psb = &gsb->base;
  69 
  70         ret = nvkm_secboot_ctor(&gp10b_secboot, acr, device, index, &gsb->base);
  71         if (ret)
  72                 return ret;
  73 
  74         return 0;
  75 }
  76 
  77 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
  78 MODULE_FIRMWARE("nvidia/gp10b/acr/bl.bin");
  79 MODULE_FIRMWARE("nvidia/gp10b/acr/ucode_load.bin");
  80 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin");
  81 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin");
  82 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin");
  83 MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin");
  84 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin");
  85 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin");
  86 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin");
  87 MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin");
  88 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin");
  89 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin");
  90 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin");
  91 MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin");
  92 MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
  93 MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
  94 MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
  95 #endif