root/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVKM_CLK_H__
   3 #define __NVKM_CLK_H__
   4 #include <core/subdev.h>
   5 #include <core/notify.h>
   6 #include <subdev/pci.h>
   7 struct nvbios_pll;
   8 struct nvkm_pll_vals;
   9 
  10 #define NVKM_CLK_CSTATE_DEFAULT -1 /* POSTed default */
  11 #define NVKM_CLK_CSTATE_BASE    -2 /* pstate base */
  12 #define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */
  13 
  14 enum nv_clk_src {
  15         nv_clk_src_crystal,
  16         nv_clk_src_href,
  17 
  18         nv_clk_src_hclk,
  19         nv_clk_src_hclkm3,
  20         nv_clk_src_hclkm3d2,
  21         nv_clk_src_hclkm2d3, /* NVAA */
  22         nv_clk_src_hclkm4, /* NVAA */
  23         nv_clk_src_cclk, /* NVAA */
  24 
  25         nv_clk_src_host,
  26 
  27         nv_clk_src_sppll0,
  28         nv_clk_src_sppll1,
  29 
  30         nv_clk_src_mpllsrcref,
  31         nv_clk_src_mpllsrc,
  32         nv_clk_src_mpll,
  33         nv_clk_src_mdiv,
  34 
  35         nv_clk_src_core,
  36         nv_clk_src_core_intm,
  37         nv_clk_src_shader,
  38 
  39         nv_clk_src_mem,
  40 
  41         nv_clk_src_gpc,
  42         nv_clk_src_rop,
  43         nv_clk_src_hubk01,
  44         nv_clk_src_hubk06,
  45         nv_clk_src_hubk07,
  46         nv_clk_src_copy,
  47         nv_clk_src_pmu,
  48         nv_clk_src_disp,
  49         nv_clk_src_vdec,
  50 
  51         nv_clk_src_dom6,
  52 
  53         nv_clk_src_max,
  54 };
  55 
  56 struct nvkm_cstate {
  57         struct list_head head;
  58         u8  voltage;
  59         u32 domain[nv_clk_src_max];
  60         u8  id;
  61 };
  62 
  63 struct nvkm_pstate {
  64         struct list_head head;
  65         struct list_head list; /* c-states */
  66         struct nvkm_cstate base;
  67         u8 pstate;
  68         u8 fanspeed;
  69         enum nvkm_pcie_speed pcie_speed;
  70         u8 pcie_width;
  71 };
  72 
  73 struct nvkm_domain {
  74         enum nv_clk_src name;
  75         u8 bios; /* 0xff for none */
  76 #define NVKM_CLK_DOM_FLAG_CORE    0x01
  77 #define NVKM_CLK_DOM_FLAG_VPSTATE 0x02
  78         u8 flags;
  79         const char *mname;
  80         int mdiv;
  81 };
  82 
  83 struct nvkm_clk {
  84         const struct nvkm_clk_func *func;
  85         struct nvkm_subdev subdev;
  86 
  87         const struct nvkm_domain *domains;
  88         struct nvkm_pstate bstate;
  89 
  90         struct list_head states;
  91         int state_nr;
  92 
  93         struct work_struct work;
  94         wait_queue_head_t wait;
  95         atomic_t waiting;
  96 
  97         struct nvkm_notify pwrsrc_ntfy;
  98         int pwrsrc;
  99         int pstate; /* current */
 100         int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
 101         int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
 102         int astate; /* perfmon adjustment (base) */
 103         int dstate; /* display adjustment (min+) */
 104         u8  temp;
 105 
 106         bool allow_reclock;
 107 #define NVKM_CLK_BOOST_NONE 0x0
 108 #define NVKM_CLK_BOOST_BIOS 0x1
 109 #define NVKM_CLK_BOOST_FULL 0x2
 110         u8  boost_mode;
 111         u32 base_khz;
 112         u32 boost_khz;
 113 
 114         /*XXX: die, these are here *only* to support the completely
 115          *     bat-shit insane what-was-nouveau_hw.c code
 116          */
 117         int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk,
 118                         struct nvkm_pll_vals *pv);
 119         int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
 120 };
 121 
 122 int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src);
 123 int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr);
 124 int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait);
 125 int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel);
 126 int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature);
 127 
 128 int nv04_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 129 int nv40_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 130 int nv50_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 131 int g84_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 132 int mcp77_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 133 int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 134 int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 135 int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 136 int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 137 int gm20b_clk_new(struct nvkm_device *, int, struct nvkm_clk **);
 138 #endif